JPH04162630A - Semiconductor substrate - Google Patents

Semiconductor substrate

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Publication number
JPH04162630A
JPH04162630A JP29044090A JP29044090A JPH04162630A JP H04162630 A JPH04162630 A JP H04162630A JP 29044090 A JP29044090 A JP 29044090A JP 29044090 A JP29044090 A JP 29044090A JP H04162630 A JPH04162630 A JP H04162630A
Authority
JP
Japan
Prior art keywords
crystal silicon
silicon substrate
substrate
polycrystalline silicon
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29044090A
Other languages
Japanese (ja)
Inventor
Makoto Imura
誠 井村
Kenji Kusakabe
日下部 兼治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Silicon Corp
Mitsubishi Electric Corp
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Silicon Corp
Mitsubishi Electric Corp
Mitsubishi Materials Corp
Japan Silicon Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Silicon Corp, Mitsubishi Electric Corp, Mitsubishi Materials Corp, Japan Silicon Co Ltd filed Critical Mitsubishi Materials Silicon Corp
Priority to JP29044090A priority Critical patent/JPH04162630A/en
Publication of JPH04162630A publication Critical patent/JPH04162630A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To be endowed with sufficient mechanical strength and sufficient flatness and to increase a gettering effect by a method wherein another semiconductor substrate for support use is bonded, via a specific compound film, to the other main face of a semiconductor single-crystal silicon substrate which has a device formation region on one main face. CONSTITUTION:Before a bonding operation, the bonding face of a polycrystalline silicon film 4 is polished. After that, a hydrophilic treatment is executed respectively to it and to a single crystal silicon substrate 5; a phenyl group is attached; they are overlapped in a clean atmosphere. A heating operation is executed; a dehydration treatment is executed; after that, a heat treatment is executed additionally; their bonding strength is increased. The surface 2 of a single-crystal silicon substrate 1 and the rear 7 of the single-crystal silicon substrate 5 are polished. The single-crystal silicon substrate 1 for device formation use and the single-crystal silicon substrate 5 for support use are pasted via the polycrystalline silicon film 4; a structure is formed. The distance between the surface on which a device is formed of the single-crystal substrate 1 and the polycrystalline silicon film 4 for gettering use can be made short without being restricted by mechanical strength.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体デバイスを形成するための半導体基板
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a semiconductor substrate for forming a semiconductor device.

〔従来の技術〕[Conventional technology]

第12図に従来用いられている単結晶シリコン基板を示
す。同図において、単結晶シリコン基板1の一方の主面
(表面)2はデバイスを形成するためにそのまま露出さ
れているが、他方の主面(裏面)3には、CVD法によ
シ多結晶シリコン膜4が形成されている。
FIG. 12 shows a conventionally used single crystal silicon substrate. In the figure, one main surface (front surface) 2 of a single-crystal silicon substrate 1 is exposed as it is for forming a device, but the other main surface (back surface) 3 is coated with polycrystalline silicon by a CVD method. A silicon film 4 is formed.

この多結晶シリコン膜4は、単結晶シリコン基板1の表
面にデバイスを形成する際、熱処理中に発生する微小熱
誘起欠陥および金属汚染を集めて封じ込めるゲッタリン
グ効果を目的として形成されている。すなわち、実際に
デバイス形成用として必要な部分は単結晶シリコン基板
1の表面2の側であるが、その表面が汚染すると、熱処
理によって汚染物質が基板の内部に拡散していく。その
拡散速度は各元素ごとに固有の値をもち、ある時間が経
過すると基板の裏面3にまで達する。このとき裏面3に
多結晶シリコン4が存在すると、汚染物質は裏面3と多
結晶シリコン膜4との界面に生じた歪でおよび多結晶シ
リコン膜4の内部の粒界にゲッタリングされ封じ込めら
れて、もはや基板の表面2の側に逆拡散していけなくな
る。このようにして単結晶シリコン基板1の表面2を汚
染のない状態に保つことができる。
This polycrystalline silicon film 4 is formed for the purpose of a gettering effect that collects and confines minute heat-induced defects and metal contamination that occur during heat treatment when a device is formed on the surface of the single-crystal silicon substrate 1. That is, the part actually required for device formation is the surface 2 side of the single-crystal silicon substrate 1, but if that surface becomes contaminated, the contaminants will diffuse into the inside of the substrate due to heat treatment. The diffusion rate has a unique value for each element, and reaches the back surface 3 of the substrate after a certain period of time. At this time, if polycrystalline silicon 4 exists on the back surface 3, contaminants are gettered and confined by the strain generated at the interface between the back surface 3 and the polycrystalline silicon film 4 and at the grain boundaries inside the polycrystalline silicon film 4. , it is no longer possible to diffuse back toward the surface 2 of the substrate. In this way, the surface 2 of the single crystal silicon substrate 1 can be kept free from contamination.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

このような従来の単結晶シリコン基板においては、デバ
イス形成領域はその表面に、他方ゲッタリング効果を有
する多結晶シリコン膜は裏面にあって、両者は単結晶シ
リコン基板の厚みだけ隔たっている。このため、拡散係
数の小さい金属(AZ。
In such a conventional single-crystal silicon substrate, a device formation region is located on the front surface, and a polycrystalline silicon film having a gettering effect is located on the back surface, separated by the thickness of the single-crystal silicon substrate. For this reason, metals with a small diffusion coefficient (AZ).

Ti等)などの汚染につbては、特に600℃以下の低
温もしくは短時間の熱処理の場合など、その工程での汚
染をその工程中にゲッタリングし切れない問題があった
。この傾向は、基板の大口径化に伴い、機械的に十分な
強度をもたせるために厚みも増大しつつあることからさ
らに悪化しつつある。
Regarding contamination such as Ti, etc., there is a problem in that the contamination in the process cannot be completely gettered during the process, especially when heat treatment is performed at a low temperature of 600° C. or less or for a short time. This tendency is getting worse as the diameter of the substrate becomes larger and the thickness is also increasing in order to provide sufficient mechanical strength.

また、デバイスの集積度の増加とともに基板の平坦度に
対する要求が厳しくなυつつあるが、高平坦度を得るた
めには両面研磨を行なう必要がある。しかし、上述した
ように多結晶シリコン膜が裏面に露出した構造では、両
面研磨の際に多結晶シリコン膜も研磨され、そのゲッタ
リング効果が薄れるという問題があった。
Further, as the degree of integration of devices increases, requirements for substrate flatness are becoming stricter, and in order to obtain high flatness, it is necessary to perform double-sided polishing. However, in the structure in which the polycrystalline silicon film is exposed on the back surface as described above, there is a problem that the polycrystalline silicon film is also polished during double-sided polishing, and the gettering effect is weakened.

この発明の目的は、十分な平坦度と機械的強度を保持し
つつ、単結晶シリコン基板のデバイス形成用表面とゲッ
タリング領域とを近づけることにある。
An object of the present invention is to bring the device-forming surface of a single-crystal silicon substrate closer to the gettering region while maintaining sufficient flatness and mechanical strength.

〔課題を解決するための手段〕[Means to solve the problem]

この発明は、半導体単結晶シリコン基板の裏面に、ゲッ
タリング用のシリコンもしくはシリコン化合物膜を介し
て別の支持用半導体基板を接合して一つの半導体基板と
したものである。
In the present invention, another support semiconductor substrate is bonded to the back surface of a semiconductor single-crystal silicon substrate via a gettering silicon or silicon compound film to form a single semiconductor substrate.

〔作 用〕[For production]

支持用半導体基板によって十分な機械的強度が得られる
ことから、単結晶シリコン基板は研磨精度が許す限シ、
デバイスの作製に必要な限界まで薄くすることが可能と
なる。これによシ、単結晶シリコン基板のデバイス形成
用表面と裏面のゲッタリング用膜との距離を従来に比較
して著しく小さくすることが可能となシ、拡散係数の小
さい金属の汚染であっても、結晶欠陥や転位になる前に
短時間でゲッタリングされるようになる。
Because the supporting semiconductor substrate provides sufficient mechanical strength, single-crystal silicon substrates can be polished to the extent that polishing precision allows.
It becomes possible to reduce the thickness to the limit required for device fabrication. This makes it possible to significantly reduce the distance between the device-forming surface of the single-crystal silicon substrate and the gettering film on the back surface, and to prevent contamination of metals with small diffusion coefficients. Also, gettering occurs in a short time before it becomes a crystal defect or dislocation.

また、ゲッタリング用の膜は単結晶シリコン基板と支持
用半導体基板とに挾まれて外に露出しない構造であるこ
とから、両面研磨、熱激化、洗浄、エツチング等の作用
から守られ、デバイス工程の初期から最終工程に至るま
でそのゲッタリング効果を持続させることが容易である
In addition, because the gettering film is sandwiched between a single crystal silicon substrate and a supporting semiconductor substrate and is not exposed to the outside, it is protected from the effects of double-sided polishing, thermal intensification, cleaning, etching, etc. It is easy to maintain the gettering effect from the initial stage to the final process.

〔実施例〕〔Example〕

以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図はこの発明の一実施例を示す半導体基板の断面図
である。同図において1は単結晶シリコン基板でアシ、
表面2に各種デバイスを作製するため、所定の酸素濃度
、抵抗率、方位、ドーパント種等をもったものを用いる
。その表面2および裏面3は研磨され鏡面化されておシ
、裏面3にはゲッタリング用の多結晶シリコン膜4がC
VD法により反応温度300〜800℃で堆積させであ
る。
FIG. 1 is a sectional view of a semiconductor substrate showing an embodiment of the present invention. In the same figure, 1 is a single-crystal silicon substrate;
In order to fabricate various devices on the surface 2, a material having a predetermined oxygen concentration, resistivity, orientation, dopant species, etc. is used. Its front surface 2 and back surface 3 are polished to a mirror surface, and the back surface 3 is coated with a polycrystalline silicon film 4 for gettering.
It is deposited by the VD method at a reaction temperature of 300 to 800°C.

多結晶シリコン膜4の膜厚は0.05〜5μm程度あれ
ば十分で、それより厚くしてもコストが増大する割に効
果に変わりはない。この多結晶シリコン膜4を介して、
さらに別の単結晶シリコン基板5が接合面6で接合しで
ある。
It is sufficient that the thickness of the polycrystalline silicon film 4 is about 0.05 to 5 μm, and even if it is made thicker than that, the effect remains the same even though the cost increases. Through this polycrystalline silicon film 4,
Furthermore, another single crystal silicon substrate 5 is bonded at a bonding surface 6.

単結晶シリコン基板5は、機械的強度をもたせるための
支持用であるが、多結晶シリコン膜4に強固に接合して
いなければならない。このため、接合する前に、多結晶
シリコン膜4の接合面を0.01〜0.50μm程度研
磨することが望ましい。
The single crystal silicon substrate 5 is used for support to provide mechanical strength, but must be firmly bonded to the polycrystalline silicon film 4. Therefore, before bonding, it is desirable to polish the bonding surface of the polycrystalline silicon film 4 by about 0.01 to 0.50 μm.

その後、多結晶シリコン基板5とにそれぞれ親水性処理
を施してフェノール基を付け、清浄な雰囲気で重ね合せ
る。そして200〜800℃で2時間加熱して脱水処理
を行なった後、さらに800〜1200℃で熱処理を行
なうことによシ接着強度が高められる。この時、接合面
6をピークとして酸素の濃度分布が形成される。その層
の厚みは0.1μm以下で、接合強度を高めるために働
いているが、5102 にはなっていない。
Thereafter, each of the polycrystalline silicon substrates 5 is subjected to a hydrophilic treatment to have a phenol group attached thereto, and then superimposed on each other in a clean atmosphere. Then, after dehydration treatment is performed by heating at 200 to 800°C for 2 hours, the adhesive strength is increased by further performing heat treatment at 800 to 1200°C. At this time, an oxygen concentration distribution is formed with the peak at the bonding surface 6. The thickness of this layer is 0.1 μm or less and works to increase the bonding strength, but it is not 5102 mm thick.

その後、単結晶シリコン基板1の表面2と単結晶シリコ
ン基板5の裏面7を研磨する。このとき、単結晶シリコ
ン基板1の厚みを30〜50μm程度とし、単結晶シリ
コン基板5の厚みは、この半導体基板全体の厚みが規格
の厚みになるように調節する。研磨は研削でも、エツチ
ングによってもよい。
Thereafter, the front surface 2 of the single crystal silicon substrate 1 and the back surface 7 of the single crystal silicon substrate 5 are polished. At this time, the thickness of the single-crystal silicon substrate 1 is approximately 30 to 50 μm, and the thickness of the single-crystal silicon substrate 5 is adjusted so that the thickness of the entire semiconductor substrate becomes a standard thickness. Polishing may be done by grinding or etching.

このように多結晶シリコン膜4を介してデバイス形成用
の単結晶シリコン基板1と支持用の単結晶シリコン基板
5とを貼り合せて、構造としたことにより、単結晶シリ
コン基板1のデバイスが形成される表面とゲッタリング
を目的とした多結晶シリコン膜4との間の距離を、機械
的強度に制約されることなしに短くとることができる。
By bonding the single-crystal silicon substrate 1 for device formation and the single-crystal silicon substrate 5 for support through the polycrystalline silicon film 4 to form a structure, a device of the single-crystal silicon substrate 1 is formed. The distance between the surface to be treated and the polycrystalline silicon film 4 for gettering can be shortened without being restricted by mechanical strength.

例えばこれを50μmとすれば、通常第12図に示した
ような従来の基板においては500μm以上ある単結晶
シリコン基板1の厚みが10分の1以下になシ、金属不
純物や微小欠陥をゲッタリングするに要する時間が10
分の1以下になる。
For example, if this is 50 μm, the thickness of the single-crystal silicon substrate 1, which is normally 500 μm or more in the conventional substrate shown in FIG. The time required to do this is 10
It will be less than one-fold.

また多結晶シリコン膜4が2枚の単結晶シリコン基板で
挾まれ外部に露出していない構造のため、デバイス工程
においての研磨、熱処理、洗浄、エツチング等による多
結晶シリコン膜4の消耗をなくすことができる。これに
より、デバイス工程初期から最終工程に至るまで、高い
ゲッタリング能力を完全に維持することができる。
Furthermore, since the polycrystalline silicon film 4 is sandwiched between two single-crystalline silicon substrates and is not exposed to the outside, consumption of the polycrystalline silicon film 4 due to polishing, heat treatment, cleaning, etching, etc. in the device process can be eliminated. I can do it. As a result, high gettering ability can be completely maintained from the initial stage of the device process to the final process.

さらK、基板の反りを小さくすることができる。Furthermore, the warpage of the substrate can be reduced.

従来、単結晶シリコン基板1の裏面3に膨張係数の異な
る多結晶シリコン膜4を付与しただけの構造では反りが
生じる問題があったが、多結晶シリコン膜4を2枚の単
結晶シリコン基板で挾む構造にしたことにより、多結晶
シリコン膜4を境にして2枚の単結晶シリコン基板1,
5が反対向きに反り合うことから、半導体基板全体とし
ての反りは小さくなる。
Conventionally, a structure in which polycrystalline silicon films 4 having different expansion coefficients were simply applied to the back surface 3 of a single-crystalline silicon substrate 1 had a problem of warping, but the polycrystalline silicon film 4 was formed by forming two single-crystalline silicon substrates. By adopting the sandwiching structure, two single crystal silicon substrates 1,
Since the semiconductor substrates 5 are warped in opposite directions, the warpage of the semiconductor substrate as a whole is reduced.

また、従来単結晶シリコン基板1の裏面に多結晶シリコ
ン膜4が露出した構造では多結晶シリコン膜4を損わな
いためには単結晶シリコン基板1の表面2のみ研磨する
片面研磨しかできず、平坦化が難しかったが、多結晶シ
リコン膜4を単結晶シリコン基板1,5で挾み込んだこ
とによシ、単結晶シリコン基板1の表面2と単結晶シリ
コン基板5の裏面7とを研磨する両面研磨が可能となシ
、高い平坦度が実現できる。
In addition, in the conventional structure in which the polycrystalline silicon film 4 is exposed on the back surface of the single-crystal silicon substrate 1, only one-sided polishing, which is polishing only the front surface 2 of the single-crystal silicon substrate 1, can be performed in order not to damage the polycrystalline silicon film 4. Although planarization was difficult, by sandwiching the polycrystalline silicon film 4 between the single-crystal silicon substrates 1 and 5, the front surface 2 of the single-crystal silicon substrate 1 and the back surface 7 of the single-crystal silicon substrate 5 were polished. It is possible to polish both sides and achieve high flatness.

なお、上述した実施例では多結晶シリコン膜4は単結晶
シリコン基板1の表面2から50μm程度の深さに設け
たが、本発明はこれに限定されるものではなく、0,0
5μm程度以上であればよい。
In the above embodiment, the polycrystalline silicon film 4 was provided at a depth of about 50 μm from the surface 2 of the single crystal silicon substrate 1, but the present invention is not limited to this.
It is sufficient if the thickness is about 5 μm or more.

特に、第2図に示すように多結晶シリコン膜4を挾む単
結晶シリコン膜1,5の厚みが等しくなるようにすれば
、基板の反りを最小にすることができる。
In particular, as shown in FIG. 2, if the thicknesses of the single crystal silicon films 1 and 5 sandwiching the polycrystalline silicon film 4 are made equal, the warpage of the substrate can be minimized.

また逆に、第3図に示すように多結晶シリコン膜4を表
面2よシも裏面Tに近づけて配置することも可能であシ
、単結晶シリコン基板1にIG(Intrinsic 
Gettering)効果をもたせてもよい。図中8は
IG源を模式的に示したものである。
Conversely, as shown in FIG.
(Gettering) effect may also be provided. 8 in the figure schematically shows an IG source.

支持用の基板として、単結晶シリコン基板5の代シに、
第4図に示すように多結晶シリコン基板9を貼り合せて
用いてもよい。10はその裏面を示す。
As a support substrate, instead of the single crystal silicon substrate 5,
As shown in FIG. 4, a polycrystalline silicon substrate 9 may be bonded and used. 10 indicates the back side thereof.

また、ゲッタリングの必要のない支持用基板側までゲッ
タリングすることでデバイス形成側の単結晶シリコン基
板1のゲッタリング効果を減殺することがないよう、第
5図に示すように多結晶シリコン膜4に加えて酸化膜1
1あるいは第6図に示すように窒化膜12を付与しても
よい。
In addition, in order to avoid reducing the gettering effect of the single crystal silicon substrate 1 on the device formation side by gettering up to the support substrate side where no gettering is necessary, a polycrystalline silicon film is added as shown in FIG. 4 plus oxide film 1
1 or 6, a nitride film 12 may be provided.

さらに第7図に示すように単結晶シリコン基板1人の表
面2人の上にドーパントの種類または濃度の異なるエビ
層1Bを積んで、単結晶シリコン基板1としてもよい。
Furthermore, as shown in FIG. 7, layers 1B having different types or concentrations of dopants may be stacked on two surfaces of one single crystal silicon substrate to form the single crystal silicon substrate 1.

2Bはエビ層1Bの表面を示す。また、第8図に示すよ
うに支持用基板と貼シ合せる側の裏面3に埋め込み拡散
領域13を予め形成しておいてもよい。
2B shows the surface of the shrimp layer 1B. Further, as shown in FIG. 8, an embedded diffusion region 13 may be formed in advance on the back surface 3 on the side to be bonded to the supporting substrate.

あるいはまた、第9図に示すように単結晶シリコン基板
1の裏面3にサンドブラスト、レーザ照射またはイオン
注入によシダメージを与えて機械的歪層14を形成した
上に多結晶シリコン膜4を形成してもよい。
Alternatively, as shown in FIG. 9, the polycrystalline silicon film 4 is formed on the mechanically strained layer 14 by damaging the back surface 3 of the single crystal silicon substrate 1 by sandblasting, laser irradiation, or ion implantation. You can.

さらに第10図に示すように支持用の単結晶シリコン基
板5の裏面にエツチングを施し、サンドブラストで荒ら
したシ多結晶シリコン膜を付与するなどのゲッタリング
処理をしてもよい。同図には、エツチング面15に多結
晶シリコン膜16を付与した例を示しである。
Further, as shown in FIG. 10, the back surface of the support single crystal silicon substrate 5 may be etched and a gettering process may be performed, such as applying a polycrystalline silicon film roughened by sandblasting. This figure shows an example in which a polycrystalline silicon film 16 is provided on the etched surface 15.

また、第11図に示したようにデバイス形成側または支
持側のいずれかの基板の周辺部を5mm以下程度の範囲
で削除した上で貼シ合せてもよい。
Alternatively, as shown in FIG. 11, the peripheral portion of either the device forming side or supporting side substrate may be removed within a range of about 5 mm or less and then bonded together.

同図の例では多結晶シリコン基板4を付与した単結晶シ
リコン基板1を面取シしている。このようにすることに
より、面取り部からの剥離を少なくすることができ、ま
た半導体基板の表裏も一見してわかシやすくなる。
In the example shown in the figure, a single crystal silicon substrate 1 provided with a polycrystalline silicon substrate 4 is chamfered. By doing this, peeling from the chamfered portion can be reduced, and the front and back sides of the semiconductor substrate can be easily washed at a glance.

なお、ゲッタリング用の膜としては、多結晶シリコン膜
の代シにアモルファスシリコン膜、窒化シリコン膜ある
いは不純物を高濃度にドープした酸化膜などでもよい。
Note that the gettering film may be an amorphous silicon film, a silicon nitride film, or an oxide film heavily doped with impurities instead of the polycrystalline silicon film.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、デバイス形成用の単結
晶シリコン基板にゲッタリング用膜を介して専用の支持
基板を貼シ合せた構造とすることにより、機械的強度を
低下させることなく単結晶シリコン基板のデバイス形成
用表面とゲッタリング用膜との間の距離を小さくシ、マ
たゲッタリング用膜を損うことなく両面研磨することが
可能となる。このため、十分な機械的強度および平坦度
をもち、かつゲッタリング効果の高い半導体基板が得ら
れる効果がある。
As described above, according to the present invention, by creating a structure in which a dedicated support substrate is bonded to a single crystal silicon substrate for device formation via a gettering film, a single crystal silicon substrate for device formation can be easily bonded without reducing mechanical strength. By reducing the distance between the device forming surface of the crystalline silicon substrate and the gettering film, it becomes possible to polish both sides without damaging the gettering film. Therefore, a semiconductor substrate having sufficient mechanical strength and flatness and a high gettering effect can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示す断面図、第2図ない
し第11図はそれぞれ他の実施例を示す断面図、第臆図
は従来例を示す断面図である。 1−・・拳単結晶シリコン基板、2・・・・表面、3・
・・・裏面、4・・・・ゲッタリング用多結晶シリコン
膜、5・・・・支持用単結晶シリコン基板、10・・・
・支持用多結晶シリコン基板。
FIG. 1 is a sectional view showing one embodiment of the present invention, FIGS. 2 to 11 are sectional views showing other embodiments, and FIG. 1 is a sectional view showing a conventional example. 1-...Fist single crystal silicon substrate, 2...Surface, 3...
...Back surface, 4... Polycrystalline silicon film for gettering, 5... Single crystal silicon substrate for support, 10...
- Polycrystalline silicon substrate for support.

Claims (1)

【特許請求の範囲】[Claims]  一方の主面にデバイス形成領域を有する半導体単結晶
シリコン基板の他方の主面に、ゲツタリング用のシリコ
ンもしくはシリコン化合物膜を介して別の支持用半導体
基板を接合してなる半導体基板。
A semiconductor substrate formed by bonding a semiconductor single-crystal silicon substrate having a device formation region on one main surface to another supporting semiconductor substrate via a gettering silicon or silicon compound film.
JP29044090A 1990-10-25 1990-10-25 Semiconductor substrate Pending JPH04162630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29044090A JPH04162630A (en) 1990-10-25 1990-10-25 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29044090A JPH04162630A (en) 1990-10-25 1990-10-25 Semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH04162630A true JPH04162630A (en) 1992-06-08

Family

ID=17756062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29044090A Pending JPH04162630A (en) 1990-10-25 1990-10-25 Semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH04162630A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5346848A (en) * 1993-06-01 1994-09-13 Motorola, Inc. Method of bonding silicon and III-V semiconductor materials
US5413952A (en) * 1994-02-02 1995-05-09 Motorola, Inc. Direct wafer bonded structure method of making
JPH10303089A (en) * 1997-02-27 1998-11-13 Mitsubishi Materials Shilicon Corp Manufacture of laminated substrate
JP2007208288A (en) * 1995-04-06 2007-08-16 Sumco Techxiv株式会社 Method for manufacturing laminate semiconductor wafer
WO2010140510A1 (en) * 2009-06-02 2010-12-09 信越化学工業株式会社 Method of improving crystal quality of paste-together substrate having sandblast processing implemented
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6329937A (en) * 1986-07-23 1988-02-08 Sony Corp Semiconductor substrate
JPS63221633A (en) * 1987-03-10 1988-09-14 Fujitsu Ltd Manufacture of semiconductor element
JPH02199839A (en) * 1989-01-30 1990-08-08 Kawasaki Steel Corp Manufacture of semiconductor wafer
JPH02260428A (en) * 1989-03-31 1990-10-23 Hitachi Ltd Semiconductor substrate and device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6329937A (en) * 1986-07-23 1988-02-08 Sony Corp Semiconductor substrate
JPS63221633A (en) * 1987-03-10 1988-09-14 Fujitsu Ltd Manufacture of semiconductor element
JPH02199839A (en) * 1989-01-30 1990-08-08 Kawasaki Steel Corp Manufacture of semiconductor wafer
JPH02260428A (en) * 1989-03-31 1990-10-23 Hitachi Ltd Semiconductor substrate and device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5346848A (en) * 1993-06-01 1994-09-13 Motorola, Inc. Method of bonding silicon and III-V semiconductor materials
US5413952A (en) * 1994-02-02 1995-05-09 Motorola, Inc. Direct wafer bonded structure method of making
JP2007208288A (en) * 1995-04-06 2007-08-16 Sumco Techxiv株式会社 Method for manufacturing laminate semiconductor wafer
JP4750065B2 (en) * 1995-04-06 2011-08-17 Sumco Techxiv株式会社 Manufacturing method of bonded semiconductor wafer
JPH10303089A (en) * 1997-02-27 1998-11-13 Mitsubishi Materials Shilicon Corp Manufacture of laminated substrate
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US8389385B2 (en) 2009-02-04 2013-03-05 Micron Technology, Inc. Semiconductor material manufacture
WO2010140510A1 (en) * 2009-06-02 2010-12-09 信越化学工業株式会社 Method of improving crystal quality of paste-together substrate having sandblast processing implemented
JP2010283033A (en) * 2009-06-02 2010-12-16 Shin-Etsu Chemical Co Ltd Method for improving quality of crystal of laminated substrate treated with sandblasting

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