JPH02199839A - Manufacture of semiconductor wafer - Google Patents
Manufacture of semiconductor waferInfo
- Publication number
- JPH02199839A JPH02199839A JP1777089A JP1777089A JPH02199839A JP H02199839 A JPH02199839 A JP H02199839A JP 1777089 A JP1777089 A JP 1777089A JP 1777089 A JP1777089 A JP 1777089A JP H02199839 A JPH02199839 A JP H02199839A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- polycrystalline silicon
- layer
- strain
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000013078 crystal Substances 0.000 claims abstract description 11
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 239000012808 vapor phase Substances 0.000 claims description 4
- 238000005247 gettering Methods 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 43
- 238000010438 heat treatment Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005422 blasting Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000006061 abrasive grain Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 238000007447 staining method Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体ウェーハの製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing semiconductor wafers.
シリコン単結晶ウェーハは、シリコン単結晶インゴット
より約７００ａｍの厚さに切断され半導体装置の基板と
して使用されており、表面より数１０μｍ程度までが素
子形成層となっている。A silicon single-crystal wafer is cut from a silicon single-crystal ingot to a thickness of approximately 700 am and is used as a substrate for a semiconductor device, with an element forming layer extending from the surface to about several tens of micrometers.
シリコン単結晶ウェーハはデバイスプロセス中に半導体
装置の性能を低下させる重金属不純物による汚染を受け
る可能性があり、ウェーへの裏面に、シリコン、酸素等
の原子またはイオンのインプランテーシヨンあるいは砥
粒または珪砂粒によるブラストにより歪層を形成させる
か、または多結晶シリコンを気相成長させ、後工程にお
いてゲッタリング効果により素子形成層の重金属不純物
を低減している。Single-crystal silicon wafers can be contaminated by heavy metal impurities that reduce the performance of semiconductor devices during device processing. A strained layer is formed by blasting with silica sand grains, or polycrystalline silicon is grown in a vapor phase, and heavy metal impurities in the element forming layer are reduced by a gettering effect in a subsequent process.
しかしこれらの方法においてはゲッタリングサイトはウ
ェーへの裏面にあり、ゲッタリングはウェーハのほぼ全
厚を通して行われるため効果は不十分である。However, in these methods, the gettering site is located on the back side of the wafer, and gettering is performed through almost the entire thickness of the wafer, so the effects are insufficient.
ウェーハどうじを接合して一体化する方法については特
開昭６２−１７６５６等がある。これらは高抵抗基板と
低抵抗基板を接合したＩＣ用基板の製作や、接合面付近
（接合されたウェーハの内部）にフローセンサ等の機能
を持つ素子領域を形成することを目的としている。Regarding the method of joining and integrating wafers, there is Japanese Patent Application Laid-Open No. 62-17656. The purpose of these is to manufacture an IC substrate by bonding a high resistance substrate and a low resistance substrate, and to form an element region having a function such as a flow sensor near the bonding surface (inside the bonded wafer).
これらの方法では接合に用いられるウェーハは鏡面ウェ
ーハであり、接合面は二つのウェーハとも鏡面であるこ
とが必要である。In these methods, the wafers used for bonding are mirror-finished wafers, and the bonding surfaces of both wafers must be mirror-finished.
従って接合工程の前にウェーハ加工の最終工程までを通
過しなければならない。Therefore, it is necessary to go through the final process of wafer processing before the bonding process.
また、鏡面どうしの接合であるため、接合面付近のゲッ
タリングサイトは接合時の両鏡面でのミスフィツトが主
であり、ゲッタリング能力は小さい。Furthermore, since the mirror surfaces are joined together, the gettering sites near the joint surfaces are mainly caused by misfit between the two mirror surfaces at the time of joining, and the gettering ability is small.
〔発明が解決しようとする課題１
本発明は上記従来技術の問題点を解決し、ゲッタリング
効果の高いウェーハを製造する方法を提供しようとする
ものである。[Problem to be Solved by the Invention 1] The present invention aims to solve the problems of the above-mentioned prior art and provide a method for manufacturing a wafer with a high gettering effect.
〔課題を解決するための手段］
本発明は上記課題を解決するために、単結晶ジノコンウ
ェーハの裏面に結晶歪を持つ歪層を形成した後、該歪層
の下面に多結晶シリコン層を気相成長させ１次に該多結
晶シリコン層の下面に多結晶シリコンウェーハを接合し
一体化することを特徴とする半導体ウェーへの製造方法
を提供するものである。[Means for Solving the Problems] In order to solve the above problems, the present invention forms a strained layer having crystal strain on the back surface of a single crystal Zinocon wafer, and then forms a polycrystalline silicon layer on the bottom surface of the strained layer. The present invention provides a method of manufacturing a semiconductor wafer, which is characterized in that a polycrystalline silicon wafer is first bonded and integrated with the lower surface of the polycrystalline silicon layer by vapor phase growth.
［作用］
第１図は本発明の方法により製造されたウェーハの縦断
面模式図で、１は単結晶シリコンウェー八、２は歪層、
３は多結晶シリコン層、４は多結晶シリコンウェーハで
ある。[Function] FIG. 1 is a schematic vertical cross-sectional view of a wafer manufactured by the method of the present invention, where 1 is a single crystal silicon wafer, 2 is a strained layer,
3 is a polycrystalline silicon layer, and 4 is a polycrystalline silicon wafer.
半導体装置における素子形成層の厚さは表面より数１０
μｍ程度までであるが、本発明においてはインゴットよ
り切断された厚さ約３００ｕｍの単結晶シリコンウェー
八が用いられる。The thickness of the element forming layer in a semiconductor device is several tens of tens of meters thicker than the surface.
In the present invention, a single crystal silicon wafer cut from an ingot and having a thickness of about 300 um is used.
上記ウェーハの裏面に歪層を形成する方法としては、シ
リコン、酸素等の原子またはイオンのインプランテーシ
ョン、あるいは砥粒または珪石粒によるブラストが、通
常の方法により行われる。As a method for forming the strained layer on the back surface of the wafer, implantation of atoms or ions of silicon, oxygen, etc., or blasting with abrasive grains or silica grains is performed by a conventional method.
上記歪層の下面には、多結晶シリコン層が通常用いられ
る方法により気相成長される。A polycrystalline silicon layer is grown in vapor phase on the lower surface of the strained layer by a commonly used method.
この多結晶シリコン層の下面に、多結晶シリコン層に接
合される面を鏡面とした多結晶シリコンウェー八を接合
して一体化する。多結晶シリコンウェーハはドーパント
および酸素の濃度を限定する必要はなく、任意のもので
よい。A polycrystalline silicon wafer whose surface to be bonded to the polycrystalline silicon layer is mirror-finished is bonded and integrated to the lower surface of this polycrystalline silicon layer. The polycrystalline silicon wafer does not need to have a limited concentration of dopant and oxygen, and may be of any concentration.
本発明の方法により製造されたウェーハは２素子形成層
とゲッタリングサイトとの距離が従来の方法に比較して
極めて短いのでゲッタリング効果が向上する。In the wafer manufactured by the method of the present invention, the distance between the two-element forming layer and the gettering site is extremely short compared to the conventional method, so that the gettering effect is improved.
また、単結晶シリコンウェーハの厚さを薄くし、多結晶
シリコン層をバッファとして多結晶シリコンウェー八を
接合しているので、熱膨張による単結晶ウェーハでのス
リップ等の欠陥を低減することができ、更に、多結晶シ
リコンウェーハの表面のみを鏡面仕上すればよいので製
造工程を簡単にすることができる。In addition, since the thickness of the single crystal silicon wafer is reduced and the polycrystalline silicon wafers are bonded using the polycrystalline silicon layer as a buffer, defects such as slips in the single crystal wafer due to thermal expansion can be reduced. Furthermore, since only the surface of the polycrystalline silicon wafer needs to be mirror-finished, the manufacturing process can be simplified.
［実施例］
直径約１５０ｍｍのシリコン単結晶インゴットにより厚
さ約３００μｍのウェーハを切断し、このウェーハの裏
面にシリコン原子のインプランテーションを行い、厚さ
約５μｍの歪層を形成させ、この歪層の下面に厚さ５〜
ｌＯμｍの多結晶シリコン層を気相成長させた。[Example] A wafer with a thickness of about 300 μm was cut from a silicon single crystal ingot with a diameter of about 150 mm, and silicon atoms were implanted on the back side of the wafer to form a strained layer with a thickness of about 5 μm. Thickness 5~ on the bottom surface of
A polycrystalline silicon layer of 10 μm was grown by vapor phase.
次に、直径約１５０ｍｍのシリコン多結晶インゴットよ
り厚さ約３５０μｍのウェーハを切断し、その１面をポ
リッシングすることにより鏡面仕上し、鏡面仕上された
面を多結晶シリコン層に接合して一体化し、本発明方法
によるウェーハを製造した。Next, a wafer with a thickness of approximately 350 μm is cut from a silicon polycrystalline ingot with a diameter of approximately 150 mm, one surface of the wafer is polished to a mirror finish, and the mirror-finished surface is bonded to the polycrystalline silicon layer for integration. , a wafer was manufactured by the method of the present invention.
上記により得られたウェーハ５０枚を試料とし、Ｃｕの
定量汚塗法によって表面にＣｕを付着させ、１１５０℃
Ｘ１ｈｒの熱処理を行った後、さらに１０００℃Ｘ１６
ｈｒの熱処理を行い５発生した酸化積層欠陥（Ｏ３Ｆ）
密度を測定した。Fifty wafers obtained above were used as samples, and Cu was attached to the surface by quantitative Cu staining method and heated to 1150°C.
After heat treatment for X1hr, further heat treatment at 1000℃X16
Oxidized stacking fault (O3F) generated after 5 hours of heat treatment
The density was measured.
また上記ウェーハを、０２雰囲気中で１０００’ＣＸ
５ ｈ ｒの熱処理を行った優、さらにＮ２雰囲気中で
１２００℃Ｘ５ｈｒの熱処理を行い１発生したスリップ
長さ（１枚のウェーハの単結晶面に発生したスリップ長
さの和）を測定した。Further, the above wafer was heated at 100'CX in 02 atmosphere.
After heat treatment was performed for 5 hours, heat treatment was performed at 1200° C. for 5 hours in a N2 atmosphere, and the length of slip that occurred (the sum of the lengths of slip that occurred on the single crystal plane of one wafer) was measured.
比較例として、実施例に用いた単結晶インゴットより厚
さ約７００ｕｍのウェーハを切断し、裏面に実施例と同
様に歪層を形成させ、実施例と同様に酸化積層欠陥密度
およびスリップ長さを測定した。As a comparative example, a wafer with a thickness of approximately 700 um was cut from the single crystal ingot used in the example, a strained layer was formed on the back side in the same manner as in the example, and the oxidized stacking fault density and slip length were measured in the same manner as in the example. It was measured.
実施例および比較例にあける測定結果を第２図および第
１表に示した。The measurement results for Examples and Comparative Examples are shown in FIG. 2 and Table 1.
第
■
表
２・・−歪層
３・・−多結晶シリコン層
４・・−多結晶シリコンウェーハ
本発明により、ゲッタリング効果が高く、かつスリップ
発生の軽減されたウェーハを製造することができた。Table 2 - Strained layer 3 - Polycrystalline silicon layer 4 - Polycrystalline silicon wafer According to the present invention, a wafer with a high gettering effect and reduced occurrence of slip could be manufactured. .
本発明により、
ｌ）ゲッタリング効果の高い、
２）熱歪による欠陥発生の少ない、
ウェーハの製造が可能となり、このウェーハ上に電子回
路を構成する際に歩留改善が可能となる。The present invention makes it possible to manufacture wafers that: 1) have a high gettering effect; and 2) have few defects caused by thermal strain, and it is possible to improve the yield when configuring electronic circuits on these wafers.
第１図は本発明方法による半導体ウェーハの縦断面図模
式図、第２図は実施例および比較例における半導体ウェ
ーへの表面Ｃｕｆｉ度と熱処理後の酸化積層欠陥密度と
の関係を示す図である。
ｌ・・・単結晶シリコンウェーハ
川崎製鉄株式会社FIG. 1 is a schematic vertical cross-sectional view of a semiconductor wafer according to the method of the present invention, and FIG. 2 is a diagram showing the relationship between the surface Cufi degree of the semiconductor wafer and the oxidized stacking fault density after heat treatment in Examples and Comparative Examples. . l...Single crystal silicon wafer Kawasaki Steel Corporation
Claims (1)
形成した後、 該歪層の下面に多結晶シリコン層を気相成 長させ、 次に該多結晶シリコン層の下面に多結晶シ リコンウェーハを接合し一体化することを特徴とする半
導体ウェーハの製造方法。[Claims] 1. After forming a strained layer with crystal strain on the back surface of a single-crystal silicon wafer, a polycrystalline silicon layer is grown in vapor phase on the lower surface of the strained layer, and then a polycrystalline silicon layer is grown on the lower surface of the polycrystalline silicon layer. A method for manufacturing a semiconductor wafer, which comprises bonding and integrating a polycrystalline silicon wafer to a semiconductor wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1777089A JPH02199839A (en) | 1989-01-30 | 1989-01-30 | Manufacture of semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1777089A JPH02199839A (en) | 1989-01-30 | 1989-01-30 | Manufacture of semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02199839A true JPH02199839A (en) | 1990-08-08 |
Family
ID=11952951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1777089A Pending JPH02199839A (en) | 1989-01-30 | 1989-01-30 | Manufacture of semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02199839A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04162630A (en) * | 1990-10-25 | 1992-06-08 | Mitsubishi Materials Shilicon Corp | Semiconductor substrate |
-
1989
- 1989-01-30 JP JP1777089A patent/JPH02199839A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04162630A (en) * | 1990-10-25 | 1992-06-08 | Mitsubishi Materials Shilicon Corp | Semiconductor substrate |
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