JP2002075905A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor deviceInfo
- Publication number
- JP2002075905A JP2002075905A JP2000259226A JP2000259226A JP2002075905A JP 2002075905 A JP2002075905 A JP 2002075905A JP 2000259226 A JP2000259226 A JP 2000259226A JP 2000259226 A JP2000259226 A JP 2000259226A JP 2002075905 A JP2002075905 A JP 2002075905A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- cobalt
- film
- semiconductor device
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 54
- 239000010941 cobalt Substances 0.000 claims abstract description 54
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 54
- 238000005530 etching Methods 0.000 claims abstract description 51
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 28
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 28
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims abstract description 18
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 16
- 239000000243 solution Substances 0.000 claims description 13
- 239000007864 aqueous solution Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 239000007788 liquid Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005245 sintering Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- DJNHLZWTYLEQCN-UHFFFAOYSA-N [Si].[Co].[Co] Chemical compound [Si].[Co].[Co] DJNHLZWTYLEQCN-UHFFFAOYSA-N 0.000 description 4
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 102220491117 Putative postmeiotic segregation increased 2-like protein 1_C23F_mutation Human genes 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910000428 cobalt oxide Inorganic materials 0.000 description 1
- IVMYJDGYRUAWML-UHFFFAOYSA-N cobalt(ii) oxide Chemical compound [Co]=O IVMYJDGYRUAWML-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
- C23F1/14—Aqueous compositions
- C23F1/16—Acidic compositions
- C23F1/28—Acidic compositions for etching iron group metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- ing And Chemical Polishing (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体装置の製造
方法に係わり、特に、低抵抗なシリサイド層の形成に好
適な半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for forming a low-resistance silicide layer.
【0002】[0002]
【従来の技術】浅接合の高速ロジックデバイス及びDR
AM/ロジック混載デバイスの実現には、サリサイドプ
ロセスによるゲート及びソース、ドレイン電極の低抵抗
化が必須であり、細線効果、耐熱性の観点よりコバルト
サリサイド技術を採用している。半導体素子の拡散層電
極もしくはゲート電極、もしくは拡散層電極、ゲート電
極双方が形成されたシリコン基板にシリサイド反応を抑
制する不純物が注入されていると、局所的に低抵抗かつ
均一なコバルトシリサイド膜が形成されない領域が生じ
る。2. Description of the Related Art Shallow junction high-speed logic device and DR
In order to realize an AM / logic hybrid device, it is necessary to reduce the resistance of the gate, source, and drain electrodes by a salicide process, and the cobalt salicide technology is used from the viewpoint of the fine wire effect and heat resistance. When impurities for suppressing the silicide reaction are implanted into a silicon substrate on which a diffusion layer electrode or a gate electrode, or both a diffusion layer electrode and a gate electrode of a semiconductor element are formed, a locally low-resistance and uniform cobalt silicide film is formed. Some areas are not formed.
【0003】[0003]
【発明が解決しようとする課題】この局所的にコバルト
シリサイドが形成し難い状況(形成不良)を改善する
為、コバルトサリサイドプロセスのどの工程が形成不良
に大きく影響を与えているか調査した。その結果、第1
シンター後の未反応コバルト及び一部酸化されたコバル
ト膜を除去する工程において、エッチング液温度を高温
にし、又は、エッチング時間を長時間行うことによっ
て、シリサイド層の形成不良が発生することを見いだし
た。In order to improve the situation in which cobalt silicide is hardly formed locally (defective formation), it was investigated which step of the cobalt salicide process greatly affects the formation failure. As a result, the first
In the process of removing the unreacted cobalt and the partially oxidized cobalt film after sintering, it was found that the formation of a silicide layer was poorly performed by increasing the temperature of the etchant or performing the etching for a long time. .
【0004】本発明の目的は、上記した従来技術の欠点
を改良し、特に、低抵抗なシリサイド層の形成に好適な
新規な半導体装置の製造方法を提供することにある。An object of the present invention is to improve the above-mentioned drawbacks of the prior art and to provide a novel method of manufacturing a semiconductor device which is particularly suitable for forming a low-resistance silicide layer.
【0005】[0005]
【課題を解決するための手段】本発明は上記した目的を
達成するため、基本的には、以下に記載されたような技
術構成を採用するものである。SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object.
【0006】即ち、本発明に係わる半導体装置の製造方
法の第1態様は、半導体基板上に選択的に形成された絶
縁膜から露出した部分に形成されたソース・ドレイン領
域、ゲート電極上に、自己整合的に金属シリサイド層を
形成する半導体装置の製造方法において、前記半導体基
板上にコバルトを堆積せしめ、熱処理を施すことで、前
記金属シリサイド層を形成し、その後、未反応のコバル
トをエッチングして除去する際、塩酸、過酸化水素、水
の混合水溶液からなるエッチング液のそれぞれの濃度比
を1:1:5〜3:1:5とし、液温を25〜45℃と
し、エッチング時間を1〜20分とした条件下でエッチ
ングすることを特徴とするものである。That is, a first aspect of the method of manufacturing a semiconductor device according to the present invention is that a source / drain region formed in a portion exposed from an insulating film selectively formed on a semiconductor substrate and a gate electrode are formed on a gate electrode. In a method of manufacturing a semiconductor device in which a metal silicide layer is formed in a self-aligned manner, cobalt is deposited on the semiconductor substrate, and heat treatment is performed to form the metal silicide layer, and thereafter, unreacted cobalt is etched. When removing by etching, the respective concentration ratios of the etching solution composed of a mixed aqueous solution of hydrochloric acid, hydrogen peroxide and water are set to 1: 1: 5 to 3: 1: 5, the liquid temperature is set to 25 to 45 ° C., and the etching time is set to The etching is performed under the conditions of 1 to 20 minutes.
【0007】[0007]
【発明の実施の形態】本発明に係わる半導体装置の製造
方法は、半導体基板上に選択的に形成された絶縁膜から
露出した部分に形成されたソース・ドレイン領域、ゲー
ト電極上に、自己整合的に金属シリサイド層を形成する
半導体装置の製造方法において、前記半導体基板上にコ
バルトを堆積せしめ、熱処理を施すことで、前記金属シ
リサイド層を形成し、その後、未反応のコバルトをエッ
チングして除去する際、塩酸、過酸化水素、水の混合水
溶液からなるエッチング液のそれぞれの濃度比を1:
1:5〜3:1:5とし、液温を25〜45℃とし、エ
ッチング時間を1〜20分とした条件下でエッチングす
ることを特徴とするものである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device in which a source / drain region formed in a portion exposed from an insulating film selectively formed on a semiconductor substrate and a gate electrode are self-aligned. In a method of manufacturing a semiconductor device, wherein a metal silicide layer is formed on a semiconductor substrate, cobalt is deposited on the semiconductor substrate and heat treatment is performed to form the metal silicide layer, and thereafter, unreacted cobalt is removed by etching. In this case, the respective concentration ratios of the etching solutions composed of a mixed aqueous solution of hydrochloric acid, hydrogen peroxide and water are set to 1:
Etching is performed under conditions of 1: 5 to 3: 1: 5, liquid temperature of 25 to 45 ° C., and etching time of 1 to 20 minutes.
【0008】[0008]
【実施例】以下に、本発明に係わる半導体装置の製造方
法の具体例を図面を参照しながら詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings.
【0009】(第1の具体例)図1、図2は、第1の具
体例を説明するための工程図である。(First Specific Example) FIGS. 1 and 2 are process diagrams for explaining a first specific example.
【0010】本発明では、まず、図1(a)に示すよう
に、素子を形成した半導体基板1上の全面に、図1
(b)に示すように、コバルト6を成膜する。この時の
成膜温度は、200〜500℃、成膜方法はマグネトロ
ンスパッタ法で成膜する。次に、これを500℃以上の
不活性ガス雰囲気中、例えば、窒素雰囲気中で30秒間
熱処理し、ダイコバルトシリサイド膜(Co2Si)、
コバルトモノシリサイド膜(CoSi)、コバルトダイ
シリサイド膜(CoSi2)を形成する(第1シンタ
ー)。この時コバルトシリサイド層は、図1(c)に示
すように、ゲート電極5上及び拡散層3、4上のみに自
己整合的に形成される。そして、塩酸、過酸化水素、水
の混合水溶液(HPM)にシリコン基板1を液浸するこ
とにより、選択的にウェットエッチングし、フィールド
酸化膜2及びサイドウォール膜上の未反応もしくは一部
酸化されたコバルト膜のみをエッチングして除去する
(図1(d))。この余剰コバルトエッチングプロセス
の際、過剰なエッチングによるゲート電極5の表面およ
びソース・ドレイン領域3、4のシリサイド膜のエッチ
ングを避ける為、エッチング条件を最適化ずる必要があ
り、塩酸、過酸化水素、水の濃度比を1:1:5〜3:
1:5、HPM液の温度を25〜45℃、エッチング時
間を1〜20分とする。次いで、第1シンター時以上の
温度、例えば、800℃、10秒間熱処理を行う(図1
(e))。この結果、低抵抗かつ均一なコバルトダイシ
リサイド(CoSi2)が形成される(第2シンタ
ー)。In the present invention, first, as shown in FIG. 1A, the entire surface of a semiconductor substrate 1 on which elements are formed is
As shown in (b), a film of cobalt 6 is formed. The film forming temperature at this time is 200 to 500 ° C., and the film is formed by magnetron sputtering. Next, this is heat-treated for 30 seconds in an inert gas atmosphere of 500 ° C. or more, for example, in a nitrogen atmosphere, to obtain a dicobalt silicide film (Co 2 Si),
A cobalt monosilicide film (CoSi) and a cobalt disilicide film (CoSi 2 ) are formed (first sinter). At this time, the cobalt silicide layer is formed in a self-aligned manner only on the gate electrode 5 and the diffusion layers 3 and 4, as shown in FIG. Then, the silicon substrate 1 is immersed in a mixed aqueous solution (HPM) of hydrochloric acid, hydrogen peroxide, and water to selectively wet-etch and unreact or partially oxidize the field oxide film 2 and the sidewall film. Only the removed cobalt film is removed by etching (FIG. 1D). In this surplus cobalt etching process, it is necessary to optimize the etching conditions in order to avoid the etching of the surface of the gate electrode 5 and the silicide films of the source / drain regions 3 and 4 due to excessive etching. Water concentration ratio of 1: 1: 5 to 3:
1: 5, the temperature of the HPM solution is 25 to 45 ° C., and the etching time is 1 to 20 minutes. Next, a heat treatment is performed for 10 seconds at a temperature higher than that of the first sintering, for example, 800 ° C. (FIG. 1).
(E)). As a result, low resistance and uniform cobalt disilicide (CoSi 2 ) is formed (second sinter).
【0011】次に、上記した余剰コバルトエッチングプ
ロセスに関して、図2を用いて更に説明する。Next, the surplus cobalt etching process will be further described with reference to FIG.
【0012】第1シンター後はその温度によってダイコ
バルトシリサイド膜、コバルトモノシリサイド膜、コバ
ルトダイシリサイド膜のどれか、もしくはそれらの混合
膜が形成されている。その状態でフィールド酸化膜上及
びサイドウォール上の未反応コバルトもしくはコバルト
の酸化物を除去する目的で、選択的ウェットエッチン
グ、即ち、余剰コバルトエッチングを行うが、その際、
過剰なエッチングを行うと、具体的には、長時間のエッ
チングによりエッチング液がコバルトシリサイド結晶の
結晶粒界から液が入り込んでいき、下地の影響、例えば
不純物注入等の影響を受けてできた不安定なコバルトシ
リサイド膜、コバルトシリサイド膜とシリコン基板の界
面に存在する不純物、基板中の不純物等をエッチングし
て局所的にシリサイド膜がエッチングされた状態ができ
る(図2(b))。この状態でその後、第2シンターを
行っても、低抵抗かつ均一なコバルトシリサイド膜をは
形成する事が出来ない。After the first sintering, any one of a dicobalt silicide film, a cobalt monosilicide film, a cobalt disilicide film, or a mixed film thereof is formed depending on the temperature. In that state, in order to remove unreacted cobalt or oxides of cobalt on the field oxide film and the sidewalls, selective wet etching, that is, excess cobalt etching is performed.
When excessive etching is performed, specifically, the etching liquid enters through the crystal grain boundaries of the cobalt silicide crystal due to long-time etching, and the etching liquid is not affected by the influence of the base, for example, the impurity implantation. By etching a stable cobalt silicide film, impurities present at the interface between the cobalt silicide film and the silicon substrate, impurities in the substrate, and the like, a state where the silicide film is locally etched is obtained (FIG. 2B). In this state, even if the second sintering is performed thereafter, a low-resistance and uniform cobalt silicide film cannot be formed.
【0013】このような不具合をなくす為、未反応コバ
ルトもしくはコバルトの酸化物を除去する工程におい
て、シリサイド膜には影響を与えず、未反応コバルトお
よび一部酸化されたコバルト膜のみをエッチング除去す
る為にエッチングレートを下げる、又は、過剰な時間エ
ッチング液に浸水させないようにする必要がある。本発
明者の実験によると、エッチング液は塩酸、過酸化水素
水、水の混合水溶液とし、その濃度比を1:1:5〜
3:1:5とし、液温度を25〜45℃とし、エッチン
グ時間を1〜20分としてエッチングするのが最適であ
った。例えば、エッチング液温度を35℃、エッチング
時間を3分とすると、未反応コバルト及びコバルトの酸
化物のみをエッチングして、シリサイド層は全くエッチ
ングされない(図2(c))。その後、第2シンターを
行うことにより、低抵抗で且つ均一なコバルトシリサイ
ド膜(CoSi2)11が形成された。不良の発生は、
エッチング液の濃度、液温、エッチング時間に大きく依
存していた。In order to eliminate such a problem, in the step of removing unreacted cobalt or cobalt oxide, only the unreacted cobalt and the partially oxidized cobalt film are removed by etching without affecting the silicide film. Therefore, it is necessary to lower the etching rate or to prevent the etching liquid from being immersed in the etching solution for an excessive time. According to the experiments of the present inventors, the etching solution was a mixed aqueous solution of hydrochloric acid, hydrogen peroxide solution and water, and the concentration ratio was 1: 1: 5 to 5: 1.
It was optimal to perform the etching at a ratio of 3: 1: 5, a liquid temperature of 25 to 45 ° C., and an etching time of 1 to 20 minutes. For example, when the temperature of the etching solution is 35 ° C. and the etching time is 3 minutes, only the unreacted cobalt and the oxide of cobalt are etched, and the silicide layer is not etched at all (FIG. 2C). Thereafter, the second sintering was performed to form a low-resistance and uniform cobalt silicide film (CoSi 2 ) 11. The occurrence of defects is
It greatly depended on the concentration of the etching solution, the solution temperature, and the etching time.
【0014】エッチング液の濃度、液温、エッチング時
間を上記範囲以下に設定した場合、未反応コバルト及び
コバルトの酸化物を完全に除去出来ず、また、エッチン
グ液の濃度、液温、エッチング時間を上記範囲以上に設
定した場合、シリサイド層をエッチングしてしまう。従
って、上記範囲が最適なエッチング条件であると結論づ
けた。When the concentration, the liquid temperature and the etching time of the etching solution are set below the above ranges, unreacted cobalt and oxides of cobalt cannot be completely removed. If it is set to a value higher than the above range, the silicide layer will be etched. Therefore, it was concluded that the above range was the optimum etching condition.
【0015】(第2の具体例)図3及び図4は、本発明
の第2の具体例を説明するための工程図である。(Second Embodiment) FIGS. 3 and 4 are process diagrams for explaining a second embodiment of the present invention.
【0016】まず、図3(a)に示すように、素子を形
成した半導体基板1上の全面に、図3(b)に示すよう
に、コバルト6を成膜する。ここで、コバルト6を成膜
した後、コバルト6の酸化防止の為にチタン(Ti)又
は窒化チタン(TiN)7を成膜し、コバルト6を覆う
(図3(c))。成膜方法としては、マグネトロンスパ
ッタ法もしくは蒸着で成膜する。この状態で、500℃
以上の不活性ガス雰囲気中で10〜60秒間熱処理し、
ダイコバルトシリサイド膜、コバルトモノシリサイド
膜、コバルトダイシリサイド膜を形成する(第1シンタ
ー)。この時、コバルトシリサイド層10は、ゲート電
極5上及び拡散層3、4上のみに自己整合的に形成され
る(図4(a))。次に、コバルト6成膜時に、酸化防
止の為にキャップ膜として形成したチタンもしくは窒化
チタン膜7を除去する為に、アンモニア、過酸化水素
水、水の混合水溶液(APM)にシリコン基板1を液浸
する(図4(b))。その後、塩酸、過酸化水素、水の
混合水溶液(HPM)にシリコン基板1を液浸すること
により、選択的にウェットエッチングし、フィールド酸
化膜及びサイドウォール膜上の未反応もしくは一部酸化
されたコバルト膜のみを除去する(図4(c))。この
際、過剰なエッチングによるゲート電極5の表面および
ソース・ドレイン領域3、4のシリサイド膜のエッチン
グを避ける為、エッチング条件を最適化ずる必要があ
り、その条件として、塩酸、過酸化水素、水の濃度比を
1:1:5〜3:1:5に、HPM液の温度を25〜4
5℃に、エッチング時間を1〜20分の条件でエッチン
グした。次いで、第1シンター時以上の温度で10〜6
0秒間熱処理を行う(図4(d))。この結果、低抵抗
且つ均一なコバルトダイシリサイド11が形成された。First, as shown in FIG. 3A, a cobalt 6 film is formed on the entire surface of the semiconductor substrate 1 on which the elements are formed, as shown in FIG. 3B. Here, after forming the cobalt 6, a film of titanium (Ti) or titanium nitride (TiN) 7 is formed to prevent oxidation of the cobalt 6, and covers the cobalt 6 (FIG. 3C). As a film forming method, a film is formed by a magnetron sputtering method or vapor deposition. In this state, 500 ° C
Heat treatment for 10 to 60 seconds in the above inert gas atmosphere,
A dicobalt silicide film, a cobalt monosilicide film, and a cobalt disilicide film are formed (first sinter). At this time, the cobalt silicide layer 10 is formed only on the gate electrode 5 and the diffusion layers 3 and 4 in a self-aligned manner (FIG. 4A). Next, in order to remove the titanium or titanium nitride film 7 formed as a cap film for preventing oxidation during the formation of the cobalt 6, the silicon substrate 1 is placed in a mixed aqueous solution (APM) of ammonia, hydrogen peroxide and water. Immersion (FIG. 4B). Thereafter, the silicon substrate 1 was immersed in a mixed aqueous solution (HPM) of hydrochloric acid, hydrogen peroxide, and water to selectively wet-etch and unreacted or partially oxidized the field oxide film and the sidewall film. Only the cobalt film is removed (FIG. 4C). At this time, it is necessary to optimize the etching conditions to avoid etching of the surface of the gate electrode 5 and the silicide films of the source / drain regions 3 and 4 due to excessive etching. The conditions include hydrochloric acid, hydrogen peroxide, and water. To 1: 1: 5 to 3: 1: 5, and the temperature of the HPM solution to 25 to 4
Etching was performed at 5 ° C. for 1 to 20 minutes. Then, at a temperature equal to or higher than the time of the first sinter, 10 to 6
Heat treatment is performed for 0 seconds (FIG. 4D). As a result, a low resistance and uniform cobalt disilicide 11 was formed.
【0017】[0017]
【発明の効果】本発明に係わる半導体装置の製造方法
は、未反応もしくは一部酸化されたコバルト膜の除去工
程において、塩酸、過酸化水素水、水の混合水溶液から
なるエッチング液の濃度比を1:1:5〜3:1:5と
し、液温度を25〜45℃とし、エッチング時間を1〜
20分としてエッチングすることにより、ゲート電極上
もしくは拡散層電極上にアンバランスにダイコバルトシ
リサイド膜、コバルトモノシリサイド膜、コバルトダイ
シリサイド膜が存在した場合においても、シリサイドし
たコバルト膜はエッチングされず、未反応のコバルトも
しくは一部酸化されたコバルトのみをエッチング除去す
ることが出来た。従って、次工程の高温熱処理を行うこ
とで、均一で低抵抗なコバルトダイシリサイド膜を形成
でき、その結果、製品の歩留まり及び長期信頼性を向上
させることができるという優れた効果を奏する。According to the method of manufacturing a semiconductor device of the present invention, in the step of removing the unreacted or partially oxidized cobalt film, the concentration ratio of the etching solution consisting of a mixed aqueous solution of hydrochloric acid, hydrogen peroxide and water is adjusted. 1: 1: 5 to 3: 1: 5, the liquid temperature is 25 to 45 ° C., and the etching time is 1 to 5.
Even if the dicobalt silicide film, the cobalt monosilicide film, and the cobalt disilicide film are unbalanced on the gate electrode or the diffusion layer electrode by etching for 20 minutes, the silicided cobalt film is not etched, Only unreacted cobalt or partially oxidized cobalt could be removed by etching. Therefore, by performing a high-temperature heat treatment in the next step, a uniform and low-resistance cobalt disilicide film can be formed, and as a result, an excellent effect of improving product yield and long-term reliability can be obtained.
【図1】本発明に係わる半導体装置の製造方法の第1の
具体例の工程を示す断面図である。FIG. 1 is a sectional view showing steps of a first specific example of a method for manufacturing a semiconductor device according to the present invention.
【図2】本発明と従来例との差異を説明する図である。FIG. 2 is a diagram illustrating a difference between the present invention and a conventional example.
【図3】本発明に係わる半導体装置の製造方法の第2の
具体例の工程を示す断面図である。FIG. 3 is a cross-sectional view showing a process of a second specific example of the method for manufacturing a semiconductor device according to the present invention.
【図4】図3の続きの工程を示す図である。FIG. 4 is a view showing a step that follows the step shown in FIG. 3;
1 シリコン基板 2 LOCOS酸化膜 3 ドレイン領域 4 ソース領域 5 ゲート電極 6 コバルト(Co)膜 7 チタン(Ti)又は窒化チタン(TiN)膜 10 CO2Si、COSi、COSi2 11 COSi2膜 REFERENCE SIGNS LIST 1 silicon substrate 2 LOCOS oxide film 3 drain region 4 source region 5 gate electrode 6 cobalt (Co) film 7 titanium (Ti) or titanium nitride (TiN) film 10 CO2Si, COSi, COSi2 11 COSi2film
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 21/336 H01L 29/78 301P // C23F 1/28 Fターム(参考) 4K057 WA01 WA10 WB01 WB03 WE08 WE25 WG01 WG02 WG03 WN01 4M104 AA01 BB20 CC01 CC05 DD02 DD64 DD78 DD84 GG09 GG14 HH16 5F033 HH04 HH25 MM07 QQ08 QQ20 QQ70 QQ73 WW03 WW04 XX10 5F040 DA10 DC01 EC01 EC07 EC13 EH02 EK01 FA03 FC19 FC22 5F043 AA26 BB15 DD07 GG04 GG10──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 21/336 H01L 29/78 301P // C23F 1/28 F term (Reference) 4K057 WA01 WA10 WB01 WB03 WE08 WE25 WG02
Claims (1)
膜から露出した部分に形成されたソース・ドレイン領
域、ゲート電極上に、自己整合的に金属シリサイド層を
形成する半導体装置の製造方法において、 前記半導体基板上にコバルトを堆積せしめ、熱処理を施
すことで、前記金属シリサイド層を形成し、その後、未
反応のコバルトをエッチングして除去する際、塩酸、過
酸化水素、水の混合水溶液からなるエッチング液のそれ
ぞれの濃度比を1:1:5〜3:1:5とし、液温を2
5〜45℃とし、エッチング時間を1〜20分とした条
件下でエッチングすることを特徴とする半導体装置の製
造方法。1. A method of manufacturing a semiconductor device in which a metal silicide layer is formed in a self-aligned manner on a source / drain region and a gate electrode formed in a portion exposed from an insulating film selectively formed on a semiconductor substrate. Forming a metal silicide layer by depositing cobalt on the semiconductor substrate and performing heat treatment, and then removing unreacted cobalt by etching, a mixed aqueous solution of hydrochloric acid, hydrogen peroxide, and water; The concentration ratio of each of the etching solutions consisting of 1: 1: 5 to 3: 1: 5, and the solution temperature being 2: 1
A method for manufacturing a semiconductor device, characterized in that etching is performed under conditions of 5 to 45 ° C. and an etching time of 1 to 20 minutes.
Priority Applications (3)
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JP2000259226A JP2002075905A (en) | 2000-08-29 | 2000-08-29 | Method of manufacturing semiconductor device |
US09/940,247 US6809039B2 (en) | 2000-08-29 | 2001-08-27 | Method for forming a silicide layer |
KR10-2001-0052004A KR100407362B1 (en) | 2000-08-29 | 2001-08-28 | Method for forming a silicide layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000259226A JP2002075905A (en) | 2000-08-29 | 2000-08-29 | Method of manufacturing semiconductor device |
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JP2002075905A true JP2002075905A (en) | 2002-03-15 |
Family
ID=18747425
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JP2000259226A Pending JP2002075905A (en) | 2000-08-29 | 2000-08-29 | Method of manufacturing semiconductor device |
Country Status (3)
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---|---|
US (1) | US6809039B2 (en) |
JP (1) | JP2002075905A (en) |
KR (1) | KR100407362B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7863191B2 (en) | 2006-09-28 | 2011-01-04 | Elpida Memory, Inc. | Manufacturing method of semiconductor device |
Families Citing this family (7)
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JP4653949B2 (en) * | 2003-12-10 | 2011-03-16 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
US7129169B2 (en) * | 2004-05-12 | 2006-10-31 | International Business Machines Corporation | Method for controlling voiding and bridging in silicide formation |
KR100602121B1 (en) * | 2004-12-03 | 2006-07-19 | 동부일렉트로닉스 주식회사 | Method of manufacturing semiconductor device |
WO2006130439A1 (en) * | 2005-05-27 | 2006-12-07 | Fsi International, Inc. | Process for removal of metals and alloys from a substrate |
CN100452288C (en) * | 2005-12-01 | 2009-01-14 | 上海华虹Nec电子有限公司 | Method for removing cobalt contaminant on back side of silicon piece by wet method |
US20070295357A1 (en) * | 2006-06-27 | 2007-12-27 | Lovejoy Michael L | Removing metal using an oxidizing chemistry |
US7390754B2 (en) * | 2006-07-20 | 2008-06-24 | United Microelectronics Corp. | Method of forming a silicide |
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US4663191A (en) | 1985-10-25 | 1987-05-05 | International Business Machines Corporation | Salicide process for forming low sheet resistance doped silicon junctions |
US4713358A (en) * | 1986-05-02 | 1987-12-15 | Gte Laboratories Incorporated | Method of fabricating recessed gate static induction transistors |
KR960006698B1 (en) | 1993-01-19 | 1996-05-22 | 금성일렉트론주식회사 | Silicide forming method |
JPH07283168A (en) | 1994-04-15 | 1995-10-27 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
KR0172260B1 (en) * | 1995-12-20 | 1999-03-30 | 김주용 | Method of forming cobalt silicide of semiconductor device |
JP4142753B2 (en) * | 1996-12-26 | 2008-09-03 | 株式会社東芝 | Sputtering target, sputtering apparatus, semiconductor device and manufacturing method thereof |
US6074960A (en) * | 1997-08-20 | 2000-06-13 | Micron Technology, Inc. | Method and composition for selectively etching against cobalt silicide |
EP0921560A2 (en) | 1997-12-05 | 1999-06-09 | Texas Instruments Inc. | Self-aligned contact |
KR19990060822A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Manufacturing Method of Semiconductor Device |
US6368960B1 (en) | 1998-07-10 | 2002-04-09 | Sharp Laboratories Of America, Inc. | Double sidewall raised silicided source/drain CMOS transistor |
KR100273314B1 (en) * | 1998-10-22 | 2001-01-15 | 김영환 | Semiconductor device manufacturing method |
US6251777B1 (en) * | 1999-03-05 | 2001-06-26 | Taiwan Semiconductor Manufacturing Company | Thermal annealing method for forming metal silicide layer |
-
2000
- 2000-08-29 JP JP2000259226A patent/JP2002075905A/en active Pending
-
2001
- 2001-08-27 US US09/940,247 patent/US6809039B2/en not_active Expired - Lifetime
- 2001-08-28 KR KR10-2001-0052004A patent/KR100407362B1/en not_active IP Right Cessation
Cited By (1)
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US7863191B2 (en) | 2006-09-28 | 2011-01-04 | Elpida Memory, Inc. | Manufacturing method of semiconductor device |
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US6809039B2 (en) | 2004-10-26 |
KR20020018052A (en) | 2002-03-07 |
US20020031915A1 (en) | 2002-03-14 |
KR100407362B1 (en) | 2003-11-28 |
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