JP2002043433A5 - - Google Patents

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Publication number
JP2002043433A5
JP2002043433A5 JP2001181366A JP2001181366A JP2002043433A5 JP 2002043433 A5 JP2002043433 A5 JP 2002043433A5 JP 2001181366 A JP2001181366 A JP 2001181366A JP 2001181366 A JP2001181366 A JP 2001181366A JP 2002043433 A5 JP2002043433 A5 JP 2002043433A5
Authority
JP
Japan
Prior art keywords
layer
forming
openings
electrode
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001181366A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002043433A (ja
Filing date
Publication date
Priority claimed from US09/596,382 external-priority patent/US6762087B1/en
Application filed filed Critical
Publication of JP2002043433A publication Critical patent/JP2002043433A/ja
Publication of JP2002043433A5 publication Critical patent/JP2002043433A5/ja
Pending legal-status Critical Current

Links

JP2001181366A 2000-06-16 2001-06-15 二重ダマシーン構造およびコンデンサを有する集積回路を製造するためのプロセス Pending JP2002043433A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/596,382 US6762087B1 (en) 2000-06-16 2000-06-16 Process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor
US09/596382 2000-06-16

Publications (2)

Publication Number Publication Date
JP2002043433A JP2002043433A (ja) 2002-02-08
JP2002043433A5 true JP2002043433A5 (https=) 2004-07-15

Family

ID=24387077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001181366A Pending JP2002043433A (ja) 2000-06-16 2001-06-15 二重ダマシーン構造およびコンデンサを有する集積回路を製造するためのプロセス

Country Status (5)

Country Link
US (1) US6762087B1 (https=)
JP (1) JP2002043433A (https=)
KR (1) KR100727794B1 (https=)
GB (1) GB2368722B (https=)
TW (1) TWI256683B (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120223413A1 (en) 2011-03-04 2012-09-06 Nick Lindert Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layer
JP2013026599A (ja) * 2011-07-26 2013-02-04 Elpida Memory Inc 半導体装置の製造方法
WO2016182782A1 (en) 2015-05-08 2016-11-17 Cirrus Logic International Semiconductor Ltd. High denstiy capacitors formed from thin vertical semiconductor structures such as finfets

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633781A (en) 1995-12-22 1997-05-27 International Business Machines Corporation Isolated sidewall capacitor having a compound plate electrode
US6025226A (en) * 1998-01-15 2000-02-15 International Business Machines Corporation Method of forming a capacitor and a capacitor formed using the method
US6251740B1 (en) * 1998-12-23 2001-06-26 Lsi Logic Corporation Method of forming and electrically connecting a vertical interdigitated metal-insulator-metal capacitor extending between interconnect layers in an integrated circuit
US6156640A (en) 1998-07-14 2000-12-05 United Microelectronics Corp. Damascene process with anti-reflection coating
TW374948B (en) 1998-07-28 1999-11-21 United Microelectronics Corp Method of prevention of poisoning trenches in dual damascene process structures and dielectric layer windows
US6174803B1 (en) 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
US6037216A (en) 1998-11-02 2000-03-14 Vanguard International Semiconductor Corporation Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process
TW389993B (en) 1998-11-18 2000-05-11 United Microelectronics Corp Method for producing thin film resistance of dual damascene interconnect
JP2000159698A (ja) * 1998-11-30 2000-06-13 Matsushita Electric Ind Co Ltd 芳香族メチリデン化合物、それを製造するための芳香族アルデヒド化合物、及びそれらの製造方法
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US6320244B1 (en) 1999-01-12 2001-11-20 Agere Systems Guardian Corp. Integrated circuit device having dual damascene capacitor
US6346454B1 (en) * 1999-01-12 2002-02-12 Agere Systems Guardian Corp. Method of making dual damascene interconnect structure and metal electrode capacitor
US6365327B1 (en) 1999-08-30 2002-04-02 Agere Systems Guardian Corp. Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuit
US6313025B1 (en) 1999-08-30 2001-11-06 Agere Systems Guardian Corp. Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit
US6281134B1 (en) 1999-10-22 2001-08-28 United Microelectronics Corp. Method for combining logic circuit and capacitor
US6228711B1 (en) * 1999-11-30 2001-05-08 United Microelectronics Corp. Method of fabricating dynamic random access memory
US6383858B1 (en) * 2000-02-16 2002-05-07 Agere Systems Guardian Corp. Interdigitated capacitor structure for use in an integrated circuit
US6664185B1 (en) * 2002-04-25 2003-12-16 Advanced Micro Devices, Inc. Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect

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