JP2001525996A - 電子装置パッケージング用の基板、ピン治具 - Google Patents
電子装置パッケージング用の基板、ピン治具Info
- Publication number
- JP2001525996A JP2001525996A JP55020098A JP55020098A JP2001525996A JP 2001525996 A JP2001525996 A JP 2001525996A JP 55020098 A JP55020098 A JP 55020098A JP 55020098 A JP55020098 A JP 55020098A JP 2001525996 A JP2001525996 A JP 2001525996A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- pin
- thickness
- porous
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 77
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 59
- 239000007787 solid Substances 0.000 claims abstract description 22
- 230000000873 masking effect Effects 0.000 claims abstract description 16
- 238000002048 anodisation reaction Methods 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000007743 anodising Methods 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 230000035515 penetration Effects 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims 3
- 239000004020 conductor Substances 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 47
- 229910052782 aluminium Inorganic materials 0.000 description 46
- 239000000463 material Substances 0.000 description 12
- 229910044991 metal oxide Inorganic materials 0.000 description 9
- 150000004706 metal oxides Chemical class 0.000 description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 239000007769 metal material Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 210000000078 claw Anatomy 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000003416 augmentation Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- PLHJDBGFXBMTGZ-WEVVVXLNSA-N furazolidone Chemical compound O1C([N+](=O)[O-])=CC=C1\C=N\N1C(=O)OCC1 PLHJDBGFXBMTGZ-WEVVVXLNSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 230000000930 thermomechanical effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
- H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
- C25D11/02—Anodisation
- C25D11/022—Anodisation on selected surface areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
- C25D11/02—Anodisation
- C25D11/04—Anodisation of aluminium or alloys based thereon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0315—Oxidising metal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0323—Working metal substrate or core, e.g. by etching, deforming
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1142—Conversion of conductive material into insulating material or into dissolvable compound
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S428/00—Stock material or miscellaneous articles
- Y10S428/901—Printed circuit
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.1対の両側の主面を有する離散型の略準角柱状で最初は導電性であるバル ブ金属の中実ボデーを備えた電子装置パッケージング用の基板であって、前記中 実ボデーは前記主面と実質的に直角方向の1個又は複数個のオリジナルのバルブ 金属の充填バイアを有し、前記充填バイアは互いに間隔を空けられかつ各がその まわりの多孔質酸化ボデー部分により個々に電気絶縁される前記基板。 2.充填バイアがこれに沿って広がっていく断面、及び約25μmから約15 0μmの間の厚さを有する請求項1による基板。 3.充填バイアがこれに沿った樽状の断面、及び約300pm以下の間の厚さを 有する請求項1による基板。 4.前記中実ボデーが、充填バイアの厚さと実質的に等しい実質的に一様な厚 さを有する請求項1ないし3のいずかによる基板。 5.前記中実ボデーが充填バイアの厚さに相当する厚さの凹所部分を有する請 求項1ないし3のいずれかによる基板。 6.前記中実ボデーの凹所のない部分が約200μmから約10mmの間の厚さ を有する請求項5による基板。 7.前記凹所部分が実質的に円錐台状の形である請求項5による基板。 8.電子装置パッケージング用の離散型基板の製造方法であって、 (a)1対の両側の主面を有し離散型で略準角柱状で最初は導電性であるバルブ 金属ブランクを準備し、このブランクは、各が両側の端面の対の間を伸びている 複数の間隔を空けられた略円筒状の貫通部分であって、両側の端面が1対の両側 の主面と実質的に平行である前記貫通部分を有し、 (b)1個又は複数個の貫通部分の両方の端面を選択的にマスキングし、そして (c)多孔質の酸化部分が貫通部分のまわりに形成されその両方の端面がマスク されたとき基板を多孔質陽極酸化し、これにより貫通部分をオリジナル金属バル ブの充填バイアとして保持する 諸段階を含む方法。 9.基板が、約150μmの貫通部分の厚さまでに限定された片面の多孔質陽 極酸化を受ける請求項8による方法。 10.基板が、約300μmの貫通部分の厚さまでに限定された両面の多孔質 陽極酸化を受ける請求項8による方法。 11.金属面を機械的にマスクするためのピン治具であって、各ピンが金属面 のある部分に対して密に並置しこれにより前記部分をマスクするための先端の面 を有するピンの陽極酸化抵抗床を備えるピン治具。 12.前記ピンの床の先端の面が実質的に同一面上にある請求項11によるピ ン治具。 13.前記ピンが異なった長さのものであり、その先端の面が異なった平行面 にある請求項11による治具。 14.電源に接続するようにされかつ前記先端の面が金属面に電気エネルギー を伝えるための電気導体である請求項11ないし13のいずれかによる治具。 15.少なくも前記ピンがバルブ金属より作られかつ周囲の酸化物メッキ面を 有する請求項14による治具。 16.選択的にマスクされたバルブ金属面を調製する方法であって、 (a)各が先端の面を有するピンの陽極酸化抵抗床を有するピン治具を 準備し、 (b)先端の面をバルブ金属面の部分をマスクするためにこの金属面に対して密 に並置し、 (c)マスクされた金属面を陽極酸化する 諸段階を含んだ方法。 17.段階(c)が導電ピンを通して電流を通過させることを含む請求項16 による方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IL12086697A IL120866A0 (en) | 1997-05-20 | 1997-05-20 | Process for producing an aluminum substrate |
IL120866 | 1997-05-20 | ||
PCT/IL1998/000230 WO1998053499A1 (en) | 1997-05-20 | 1998-05-20 | Substrate for electronic packaging, pin jig fixture |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001525996A true JP2001525996A (ja) | 2001-12-11 |
JP4484251B2 JP4484251B2 (ja) | 2010-06-16 |
Family
ID=11070149
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55020098A Expired - Fee Related JP4484251B2 (ja) | 1997-05-20 | 1998-05-20 | 基板、基板の製造方法、ピン治具、調整方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6448510B1 (ja) |
EP (1) | EP1012880A1 (ja) |
JP (1) | JP4484251B2 (ja) |
AU (1) | AU7447498A (ja) |
CA (1) | CA2290819A1 (ja) |
IL (1) | IL120866A0 (ja) |
WO (1) | WO1998053499A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006093712A (ja) * | 2004-01-26 | 2006-04-06 | Marvell World Trade Ltd | アルミニウム・コアを有する相互接続構造 |
JP2010534950A (ja) * | 2007-07-31 | 2010-11-11 | ウエイブニクス インク. | 金属ベースパッケージ基板とこれを利用した3次元多層パッケージモジュールおよびその製造方法 |
JP2011014611A (ja) * | 2009-06-30 | 2011-01-20 | Ibiden Co Ltd | 配線基板の製造方法 |
JP2012508051A (ja) * | 2008-11-11 | 2012-04-05 | ユニバーシティ オブ バス | 生体適合電極 |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
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IL120866A0 (en) | 1997-05-20 | 1997-09-30 | Micro Components Systems Ltd | Process for producing an aluminum substrate |
IL127256A (en) * | 1998-11-25 | 2002-09-12 | Micro Components Ltd | A device for packaging electronic components, a process for its manufacture and a pin device used in the process |
US6930256B1 (en) | 2002-05-01 | 2005-08-16 | Amkor Technology, Inc. | Integrated circuit substrate having laser-embedded conductive patterns and method therefor |
US6770822B2 (en) * | 2002-02-22 | 2004-08-03 | Bridgewave Communications, Inc. | High frequency device packages and methods |
US7548430B1 (en) | 2002-05-01 | 2009-06-16 | Amkor Technology, Inc. | Buildup dielectric and metallization process and semiconductor package |
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US7633765B1 (en) | 2004-03-23 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
US7960833B2 (en) | 2003-10-22 | 2011-06-14 | Marvell World Trade Ltd. | Integrated circuits and interconnect structure for integrated circuits |
US7851872B2 (en) | 2003-10-22 | 2010-12-14 | Marvell World Trade Ltd. | Efficient transistor structure |
US11081370B2 (en) | 2004-03-23 | 2021-08-03 | Amkor Technology Singapore Holding Pte. Ltd. | Methods of manufacturing an encapsulated semiconductor device |
US10811277B2 (en) | 2004-03-23 | 2020-10-20 | Amkor Technology, Inc. | Encapsulated semiconductor package |
US7262368B2 (en) * | 2004-08-13 | 2007-08-28 | Tessera, Inc. | Connection structures for microelectronic devices and methods for forming such structures |
US20070080360A1 (en) * | 2005-10-06 | 2007-04-12 | Url Mirsky | Microelectronic interconnect substrate and packaging techniques |
US7425910B1 (en) | 2006-02-27 | 2008-09-16 | Marvell International Ltd. | Transmitter digital-to-analog converter with noise shaping |
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- 1998-05-20 CA CA002290819A patent/CA2290819A1/en not_active Abandoned
- 1998-05-20 AU AU74474/98A patent/AU7447498A/en not_active Abandoned
- 1998-05-20 EP EP98921706A patent/EP1012880A1/en not_active Withdrawn
- 1998-05-20 JP JP55020098A patent/JP4484251B2/ja not_active Expired - Fee Related
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1999
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JP2006093712A (ja) * | 2004-01-26 | 2006-04-06 | Marvell World Trade Ltd | アルミニウム・コアを有する相互接続構造 |
JP2010534950A (ja) * | 2007-07-31 | 2010-11-11 | ウエイブニクス インク. | 金属ベースパッケージ基板とこれを利用した3次元多層パッケージモジュールおよびその製造方法 |
JP2012508051A (ja) * | 2008-11-11 | 2012-04-05 | ユニバーシティ オブ バス | 生体適合電極 |
JP2011014611A (ja) * | 2009-06-30 | 2011-01-20 | Ibiden Co Ltd | 配線基板の製造方法 |
Also Published As
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US6448510B1 (en) | 2002-09-10 |
WO1998053499A1 (en) | 1998-11-26 |
EP1012880A1 (en) | 2000-06-28 |
CA2290819A1 (en) | 1998-11-26 |
AU7447498A (en) | 1998-12-11 |
JP4484251B2 (ja) | 2010-06-16 |
IL120866A0 (en) | 1997-09-30 |
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