JP2001358350A - Photovoltaic element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photovoltaic element which has excellent photoelectric characteristics at low cost and at a film forming speed applicable to a process time at an industrially practical level. SOLUTION: The photovoltaic element comprises a substrate having on a base body at least a first laminated transparent conductive layer, a silicon- based semiconductor layer having at least one of pin junctions which is laminated on the substrate, and a second transparent conductive layer 103 laminated on the silicon-based semiconductor layer. In the pin junction of the silicon-based semiconductor layer, there are laminated in succession a foundational layer, an i-type semiconductor layer 102-2 containing a crystal phase, and a second conduction type non-single-crystal semiconductor layer 102-3. Further, in the foundational layer, there are laminated in succession a first conductivity type amorphous semiconductor layer 102-1A and a first conductivity type semiconductor layer 102-1B containing a crystal phase. Moreover, the grain size of the first conductivity type semiconductor layer 102-1B containing a crystal phase is increased toward the i-type semiconductor layer 102-2 containing a crystal phase.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a photovoltaic element such as a solar cell or a sensor formed by depositing at least one or more pin-type semiconductor layers including a mold layer.

[0002]

2. Description of the Related Art Conventionally, as a method of forming a crystalline silicon thin film, a method of growing from a liquid phase such as a casting method has been used. However, high temperature treatment is required, and mass production and cost reduction are required. There was a task toward.

As a method of forming a silicon thin film having crystallinity other than the casting method, a method of forming a polycrystalline silicon film by solid-phase growth of an amorphous silicon film described in Japanese Patent Application Laid-Open No. Hei 5-109638, No. 136062 discloses a method for forming a polycrystalline silicon film by performing a hydrogen plasma treatment after forming amorphous silicon and repeating this process.

[0004]

However, in the above-described method of forming a silicon thin film having crystallinity as described above, in the former method, a semiconductor layer having a thickness of several μm or more is formed by a solid phase reaction. A long heat treatment is required for crystallization, and the latter method has a problem that the process time is increased by repeating the hydrogen plasma treatment and the formation of the silicon layer.

Therefore, the present invention solves the above-mentioned problems,
It is an object of the present invention to provide a photovoltaic device which is inexpensive and has excellent photoelectric characteristics at a film forming rate which can be achieved in a process time which is practically industrially practical.

[0006]

Means for Solving the Problems At least one set of a silicon-based semiconductor layer having a pin junction and a second transparent conductive layer are laminated on a substrate having at least a first transparent conductive layer laminated on a substrate. In the photovoltaic device, the silicon-based semiconductor layer is formed by sequentially laminating an amorphous semiconductor layer having a first conductivity type and a semiconductor layer having a first conductivity type and including a crystal phase. Pi in which an i-type semiconductor layer containing
A photovoltaic device comprising an n-junction and having a crystal grain size of a semiconductor layer containing a crystal phase having the first conductivity type increasing toward an i-type semiconductor layer containing the crystal phase. I will provide a.

The present invention is characterized in that the photovoltaic element is formed by sequentially depositing an amorphous layer doped with the base layer and a non-doped amorphous layer and partially crystallizing the amorphous layer using crystallization means. I will provide a.

Further, the present invention provides a photovoltaic device, wherein the Raman scattering intensity caused by the amorphous component of the underlayer is less than the Raman scattering intensity caused by the crystalline component.

Further, the present invention provides a photovoltaic device, wherein the dopant concentration of the underlayer decreases toward the i-type semiconductor layer containing the crystal phase.

The present invention also provides a photovoltaic device, wherein the semiconductor layer is formed by a plasma CVD method using a high frequency.

It is preferable that the crystallization means is laser irradiation. Preferably, the crystallization means is a heat treatment. The frequency of the high frequency is 10 MHz or more and 10 GH
It is preferably at most z. Preferably, the substrate is a conductive substrate.

The film thickness of the semiconductor layer having the first conductivity type and including the crystal phase is d, and the length of the portion having the longest crystal grain size contained in the semiconductor layer having the first conductivity type and including the crystal phase. To r
2. The photovoltaic device according to claim 1, wherein the value of r / d is 100 or less.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As a result of intensive studies to solve the above-mentioned problems, the present inventor has found that a method of forming a photovoltaic element containing a crystal phase by a plasma CVD method using a high frequency has a first effect. An amorphous semiconductor layer having the first conductivity type and a semiconductor layer having the first conductivity type and including the crystal phase, an i-type semiconductor layer including the crystal phase, and a non-single crystal having the second conductivity type A pin in which semiconductor layers are sequentially stacked
The photovoltaic device, comprising a junction and having a structure in which the crystal grain size of a semiconductor layer containing a crystal phase having the first conductivity type increases toward the i-type semiconductor layer containing the crystal phase, A semiconductor layer containing a good crystalline phase can be formed without causing significant damage to the layer, an increase in the crystal grain size of the i-type semiconductor layer containing the crystalline phase, a decrease in defect density, and an interface with the underlayer. It has been found that by improving the above, good photoelectric conversion characteristics and environmental resistance are exhibited, and that the adhesion between the substrate and the semiconductor layer is good.

With the above configuration, the following operations are provided.

A method of forming a silicon-based semiconductor layer containing a crystal phase by a plasma CVD method using a high frequency has a shorter process time and a lower process temperature as compared with a solid-phase reaction, so that the cost can be reduced. Is advantageous. In particular, in a photovoltaic element having a pin junction, by applying the present invention to an i-type semiconductor layer having a large film thickness, this effect is greatly exerted.

When the i-type semiconductor layer substantially functioning as a light absorption layer is an i-type semiconductor layer containing a crystalline phase, light degradation due to the Stäbler-Wronski effect, which is a problem in the case of amorphous, is considered. There is an advantage that the phenomenon can be suppressed. Here, as a problem in the i-type semiconductor layer including the crystal phase, it is known that the crystal grain boundaries affect both the majority carrier and the minority carrier to deteriorate the performance. In order to suppress the influence of the crystal grain boundaries, it is considered that one of the effective means is to increase the crystal grain size in the i-type semiconductor layer to lower the crystal grain boundary density. From the beginning of the i-type semiconductor layer formation,
The formation of a high-quality crystal phase having a low grain boundary density is particularly important.

Here, when the underlying layer is only an amorphous semiconductor layer having the first conductivity type and a crystal phase is directly formed thereon, there is a problem that an amorphous layer of poor quality is likely to be formed as an initial film. There is a point. In this phenomenon, the arrangement of silicon atoms in the initial stage of film formation largely depends on the arrangement of dangling bonds existing on the surface of the amorphous semiconductor layer having the first conductivity type. It is thought to be due to dragging.
The amorphous layer thus formed as an initial film becomes a low-quality film having a high defect density due to reasons such as optimization of hydrogen content and structural relaxation, and the like. Due to its existence, the characteristics as the i-type semiconductor layer are greatly impaired. By using an underlayer in which the semiconductor layer having the first conductivity type of the present invention and having a crystal phase is introduced in a region in contact with the i-type semiconductor layer including the crystal phase, the crystal phase can be maintained without dragging the amorphous structure. Can be started. As a result of intensive studies by the present inventors, the underlayer has a Raman scattering intensity (typically around 480 cm ^-1 ) due to amorphous and a Raman scattering intensity (typical 520 cm as typical example) due to the crystalline component. ^-1 )
It has been found that the above effects are more remarkably exhibited in the underlayer formed as described below.

On the other hand, when the semiconductor layer is formed by a plasma CVD method using a high frequency, the film forming conditions of the amorphous semiconductor layer and the semiconductor layer containing the crystal phase are compared. Under the film forming conditions, the hydrogen dilution rate is relatively high, and the input power is large.
Film formation is performed in an atmosphere having a higher reducing property.
Therefore, when a semiconductor layer having the first conductivity type and including a crystal phase is directly deposited on the first transparent conductive layer, oxygen is eliminated when the first transparent conductive layer includes an oxide. As a result, the transmittance of the first transparent conductive layer is reduced, and there is a concern that the back surface reflection function may be reduced. Therefore, by forming an amorphous semiconductor layer having the first conductivity type in a region in contact with the first transparent conductive layer, it is possible to suppress a decrease in transmittance of the first transparent conductive layer. Further, when the first transparent conductive layer contains a crystalline phase, the mechanical strength characteristics are more isotropic between the first transparent conductive layer and the semiconductor layer having the first conductivity type and containing the crystalline phase. By interposing the target amorphous semiconductor layer having the first conductivity type, the adhesion between the first transparent conductive layer and the base layer is improved. Further, in a photovoltaic device having a plurality of pin junctions, even when the pin junction not adjacent to the substrate includes the i-type semiconductor layer containing the crystal phase, the lower pin
By forming an amorphous semiconductor layer exhibiting the first conductivity type in a region in contact with the junction, a p-type junction with the lower pin junction is formed.
The above arrangement is likewise preferred for reasons such as suppression of dopant diffusion at the n-junction.

As described above, the i-type semiconductor layer containing the crystal phase of the present invention is formed by sequentially stacking an amorphous semiconductor layer having the first conductivity type and a semiconductor layer having the first conductivity type and containing the crystal phase. The configuration formed on the formation layer prevents the transmittance of the first transparent conductive layer from lowering,
It is possible to suppress the diffusion of the dopant at the pn junction with the in junction and to form an i-type semiconductor layer containing a crystal phase without forming an initial film having poor film quality.

As described above, it is known that in an i-type semiconductor layer containing a crystal phase, crystal grain boundaries affect both majority carriers and minority carriers to deteriorate the performance. In order to suppress the influence of the crystal grain boundary, it is one of effective means to reduce the crystal grain boundary density by increasing the crystal grain size in the i-type semiconductor layer particularly from the initial stage of the formation of the i-type semiconductor layer. it is conceivable that. For this purpose, in the region where the semiconductor layer having the first conductivity type and including the crystal phase is in contact with the i-type semiconductor layer including the crystal phase, the crystal grain size becomes larger, so that the subsequently formed i-type semiconductor is formed. It is considered that the layer is particularly preferable because it can form a crystal phase having a good quality and a low grain boundary density from the initial stage of formation.

On the other hand, in the region in contact with the amorphous semiconductor layer having the first conductivity type, in order to improve the adhesion and suppress the defect density due to the discontinuity of the structure,
It is considered preferable to have a structure having a high affinity with the amorphous structure.

According to the present invention, the semiconductor layer containing the crystal phase having the first conductivity type has a structure in which the crystal grain size increases toward the i-type semiconductor layer containing the crystal phase. Is effectively expressed.

The silicon-based semiconductor layer may be an underlayer formed by sequentially stacking an amorphous semiconductor layer having a first conductivity type and a semiconductor layer having a first conductivity type and containing a crystalline phase.
An i-type semiconductor layer including a crystal phase, including a pin junction in which a non-single-crystal semiconductor layer indicating a second conductivity type is sequentially stacked, and a crystal grain size of the semiconductor layer including a crystal phase indicating the first conductivity type is By employing a structure that increases toward the i-type semiconductor layer containing the crystal phase, it is possible to suppress generation of dangling bonds at crystal grain boundaries and to suppress generation of distortion at crystal grain boundaries and in crystal grains. And the potential barrier inside and outside the crystal grains is reduced, so that the series resistance component can be reduced.
Since the underlayer contains an amorphous layer, a shunt current flowing along the crystal grain boundary can be suppressed, and a decrease in the parallel resistance component can be suppressed.

[0024] As a method of forming an underlayer in which an amorphous semiconductor layer having the first conductivity type and a semiconductor layer having the first conductivity type and having a crystal phase are sequentially laminated, the underlayer is doped with an amorphous layer. After the deposition, by performing a method of forming by crystallizing a part using a crystallization means, the crystal grain size of the semiconductor layer containing a crystal phase having the first conductivity type of the present invention, I with crystal phase
A configuration that increases toward the type semiconductor layer can be formed. Specifically, as the crystallization means, laser irradiation, a heat treatment, etc., which is a means of undergoing a crystal growth process in a liquid phase, may be mentioned, and by adjusting the irradiation intensity of the laser or the heating temperature, By making the surface on the reflection side of the substrate higher than that of the substrate, the distribution of the crystal grain size can be formed.

As the crystallization means, irradiation with an ultraviolet pulse laser typified by an excimer laser, heat treatment with a halogen lamp heater, a resistance heater or the like is preferable. Excimer lasers include ArF laser (oscillation wavelength 193 nm), KrF laser (oscillation wavelength 248 nm), and XeCl laser (oscillation wavelength 308 n).
m), a XeF laser (oscillation wavelength 351 nm) and the like are preferable, and the pulse energy is 100 to 50 OmJ / cm.
² is preferred.

Further, of the two processes of crystal nucleation and crystal growth in the crystal growth, in the region where the doping concentration is high, the function of crystal nucleus generation becomes dominant because the dopant contributes to the factor for generating crystal nuclei. On the other hand, it is considered that the function of crystal growth becomes dominant in a region where the dopant concentration is small. Therefore, by using the crystallization means after the doping concentration of the underlayer is reduced toward the i-type semiconductor layer containing the crystal phase, the crystal grain size changes in the film pressure direction. More easily. Here, a region having a low dopant concentration may be used as a non-doped layer.

When the doping concentration of the underlayer is reduced toward the i-type semiconductor layer containing the crystal phase, the entire crystallized region has a change in crystal grain size in the thickness direction. At the same time as being more continuous, the crystallization rate can be increased. Here, the crystal grain size and the crystallization ratio are different factors, and the definition of one does not uniquely determine the other. A method of increasing the dopant concentration that contributes as a crystal nucleus generation factor in the region where the crystal grain size is desired to be smaller and smaller in the region where the crystal grain size is desired to be increased is based on the crystallization rate. One of the ways to increase it. Not only by changing the crystal grain size in the film thickness direction, but also by increasing the crystallization rate of the crystallized region, in other words, by making the amorphous region smaller, the subsequently deposited i-type semiconductor layer can be formed in the initial stage. This is considered to be more preferable because good crystallinity can be obtained from the film.

In the case where the underlayer is formed by the above method, if the entire region of the underlayer is crystallized, the effect of the crystallization means directly affects the first transparent conductive layer. Therefore, when the first transparent conductive layer contains an oxide, oxygen is desorbed, whereby the transmittance of the first transparent conductive layer is reduced, and there is a concern that the back surface reflection function may be reduced. Therefore, by adjusting the condition of the crystallization means so as to crystallize a part of the amorphous semiconductor layer (a region on the side opposite to the first transparent conductive layer), the above-described effect is obtained. Is expressed.

As another method of forming an underlayer, in which an amorphous semiconductor layer having the first conductivity type and a semiconductor layer having the first conductivity type and having a crystal phase are sequentially laminated, the underlayer is formed using a high frequency. After the formation of the doped amorphous layer by the plasma CVD method, a method of forming a semiconductor layer containing a crystal phase by a plasma CVD method using high frequency can be given. Here, when a semiconductor layer containing a crystal phase is formed, the amount of a dopant, a hydrogen dilution ratio, a pressure, a high-frequency power, and the like are changed in a film formation process to control a crystal grain size, thereby controlling the crystal grain size according to the present invention. An underlayer can be formed.

Further, the silicon-based semiconductor of the present invention is characterized in that it is formed by a CVD method using a high frequency of 10 MHz to 10 GHz. In the CVD method, a silicon-based semiconductor can be formed at a lower temperature than a method in which the silicon-based semiconductor is formed from a liquid phase, and the silicon-based semiconductor can be formed at low cost.

In the photovoltaic device of the present invention, the thickness of the semiconductor layer having the first conductivity type and including the crystal phase is included in d and the thickness of the semiconductor layer having the first conductivity type and including the crystal phase is included. Where r is the length of the longest part of the crystal grain size to be obtained, r / d
Is 100 or less. r / d
ha10 or less is more preferable.

Further, as a result of intensive studies by the present inventors,
When r / d is more than 100, film peeling is induced between the first transparent conductive layer and the first transparent conductive layer due to stress generated in the surface direction on the semiconductor layer having the first conductivity type and including the crystal phase. It is easy to be. The control of r / d is performed by continuously controlling the concentration profile of the dopant in the semiconductor layer having the first conductivity type and including the crystal phase, and using crystallization means that undergoes a crystal growth process in a liquid phase. In such a case, the temperature may be changed promptly to control the temperature.

Next, the components of the photovoltaic element of the present invention will be described.

FIG. 1 is a schematic sectional view showing an example of the photovoltaic device of the present invention. In the figure, 101 is a substrate, 102 is a semiconductor layer, 103 is a second transparent conductive layer, and 104 is a current collecting electrode. 101-1 is a base, 101-2 is a metal layer, and 101-3 is a first transparent conductive layer. These are components of the substrate 101.

(Base) As the base 101-1, a metal,
A plate-like member or a sheet-like member made of resin, glass, ceramics, semiconductor bulk, or the like is preferably used. The surface may have fine irregularities. A structure in which light is incident from the substrate side using a transparent substrate may be employed. Further, by forming the base into a long shape, continuous film formation using a roll-to-roll method can be performed. In particular, flexible materials such as stainless steel and polyimide are used for the substrate 101-.
It is suitable as the material of (1).

(Metal Layer) The metal layer 101-2 has a role as an electrode and a role as a reflection layer that reflects light reaching the base 101-1 and reuses it in the semiconductor layer 102. The materials include Al, Cu, Ag, Au,
CuMg, AlSi, or the like can be suitably used. As the forming method, methods such as vapor deposition, sputtering, electrodeposition, and printing are suitable. The metal layer 101-2 preferably has irregularities on its surface. Accordingly, the optical path length of the reflected light in the semiconductor layer 102 can be extended, and the short-circuit current can be increased. When the base 101-1 has conductivity, the metal layer 101-2 need not be formed.

(First Transparent Conductive Layer) First Transparent Conductive Layer 1
01-3 has a role of increasing the irregular reflection of incident light and reflected light and extending the optical path length in the semiconductor layer 102. Also,
It has a role of preventing the element of the metal layer 101-2 from diffusing or migrating into the semiconductor layer 102 and preventing the photovoltaic element from shunting. Furthermore, by having an appropriate resistance, it has a role of preventing a short circuit due to a defect such as a pinhole in the semiconductor layer. Further, it is desirable that the first transparent conductive layer 101-3 has an unevenness on the surface thereof, similarly to the metal layer 101-2. The first transparent conductive layer 101-3 is preferably made of a conductive oxide such as Zn0 or IT0, and is preferably formed using a method such as evaporation, sputtering, CVD, or electrodeposition. A substance that changes the conductivity may be added to these conductive oxides.

(Substrate) The substrate 101-
A substrate 101 is formed by laminating a metal layer 101-2 and a first transparent conductive layer 101-3 on the substrate 1 as needed. Further, an insulating layer may be provided on the substrate 101 as an intermediate layer in order to facilitate integration of elements.

(Semiconductor Layer) As a main material of the silicon-based thin film and the semiconductor layer 102 of the present invention, an amorphous phase or a crystalline phase, or a mixed phase Si thereof is used. Instead of Si, an alloy of Si and C or Ge may be used. The semiconductor layer 102 contains hydrogen and / or halogen atoms at the same time. The preferred content is 0.1 to 40 atomic%. Further, the semiconductor layer 102
May contain oxygen, nitrogen, and the like. The semiconductor layer contains a Group III element to be a p-type semiconductor layer, and contains a Group V element to be an n-type semiconductor layer. As the electrical characteristics of the p-type layer and the n-type layer, those having an activation energy of 0.2 eV or less are preferable, and those having an activation energy of 0.1 eV or less are optimal. The specific resistance is preferably 100 Ωcm or less, and 1 Ωcm
The following are optimal. In the case of a stack cell (a photovoltaic element having a plurality of pin junctions), it is preferable that the band gap of the i-type semiconductor layer of the pin junction near the light incident side is wide, and the band gap becomes narrower as the pin junction becomes farther. . Further, it is preferable that the band gap has a minimum value closer to the p layer than the center in the thickness direction in the i layer. As the doped layer (p-type layer or n-type layer) on the light incident side, a crystalline semiconductor with little light absorption or a semiconductor with a wide band gap is suitable. As an example of a stack cell in which two sets of pin junctions are stacked, a combination of an i-type silicon-based semiconductor layer, from the light incident side (amorphous semiconductor layer, semiconductor layer containing crystal phase), (semiconductor layer containing crystal phase, crystal Phase-containing semiconductor layer). Also, p
An example of a photovoltaic element in which three sets of in junctions are stacked is i
From the light incident side (amorphous semiconductor layer, amorphous semiconductor layer, semiconductor layer containing crystalline phase), (amorphous semiconductor layer containing crystalline phase, semiconductor layer containing crystalline phase), (crystal (A semiconductor layer containing a phase, a semiconductor layer containing a crystal phase, and a semiconductor layer containing a crystal phase). The i-type semiconductor layer has an absorption coefficient (α) of light (630 nm) of 5000 cm ⁻¹ or more and a solar simulator (AM 1.5, 100 mW).
/ Cm ² ) photoconductivity (σp) of simulated sunlight irradiation
There 10 × 10- ⁵ S / cm or more, dark conductivity (.sigma.d) is 1
0 × 10- ⁶ S / cm or less, the Urbach energy by the constant photocurrent method (CPM) is 55
It is preferably at most meV. A slightly p-type or n-type semiconductor layer can be used as the i-type semiconductor layer.

The semiconductor layer 102 as a component of the present invention will be further described. FIG. 3 shows an example of a semiconductor layer 102 having a set of pin junctions as an example of the semiconductor layer of the present invention.
FIG. In the figure, 102-1A is an amorphous semiconductor layer showing a first conductivity type, 102-1B is a semiconductor layer showing a first conductivity type and including a crystal phase, and a base layer 102-1 is formed by laminating them. Then, an i-type semiconductor layer 102-2 containing a crystal phase and a non-single-crystal semiconductor layer 102-3 having a second conductivity type are stacked. p
In a semiconductor layer having a plurality of in junctions, at least one of the semiconductor layers preferably has the above-described structure. Amorphous semiconductor layer 102-showing the first conductivity type
The film thickness of 1A is 2.0 nm to 100 nm, and the thickness of the semiconductor layer 102-1B showing the first conductivity type and including a crystal phase is 2.0 nm.
When the thickness of the semiconductor layer having the first conductivity type and including a crystal phase is d, and the length of the longest portion of the crystal grain is r, the crystal grain size is r / d. Preferably, the value is 100 or less.

(Method for Forming Semiconductor Layer) In order to form the silicon-based thin film of the present invention and the above-mentioned semiconductor layer 102, a high-frequency plasma CVD method is suitable. Hereinafter, a preferred example of a procedure for forming the semiconductor layer 102 by a high-frequency plasma CVD method will be described. (1) The inside of the deposition chamber (vacuum chamber) which can be reduced in pressure is reduced to a predetermined deposition pressure. (2) A material gas such as a source gas or a dilution gas is introduced into the deposition chamber, and the deposition chamber is set to a predetermined deposition pressure while exhausting the deposition chamber by a vacuum pump. (3) The substrate 101 is set to a predetermined temperature by a heater. (4) The high frequency oscillated by the high frequency power supply is introduced into the deposition chamber. The method of introducing into the deposition chamber is as follows: a high frequency is guided by a waveguide and introduced into the deposition chamber through a dielectric window such as alumina ceramics, or a high frequency is guided by a coaxial cable and introduced into the deposition chamber through a metal electrode. There are ways to do that. (5) Plasma is generated in the deposition chamber to decompose the source gas, and a deposited film is formed on the substrate 101 disposed in the deposition chamber. This procedure is repeated a plurality of times as needed to form the semiconductor layer 102.

The conditions for forming the silicon-based thin film of the present invention and the semiconductor layer 102 are as follows: the substrate temperature in the deposition chamber is 100 to 450 ° C., and the pressure is 0.5 mTorr to 100 T.
Orr and high frequency power are preferably 0.001 to 2 W / cm ³ .

The source gas suitable for forming the silicon-based thin film of the present invention and the semiconductor layer 102 is Si
Examples include gasizable compounds containing silicon atoms, such as H ₄ , Si ₂ H ₆ , and SiF ₄ . In the case of using an alloy, it is desirable to further add a gasizable compound containing Ge or C, such as GeH ₄ or CH ₄ , to the source gas. It is desirable that the source gas be diluted with a dilution gas and introduced into the deposition chamber. Examples of the dilution gas include H ₂ and He. Further, a gasifiable compound containing nitrogen, oxygen or the like may be added as a source gas or a diluent gas. B ₂ H ₆ , BF ₃ or the like is used as a dopant gas for turning the semiconductor layer into a p-type layer. Further, as a dopant gas for converting the semiconductor layer into an n-type layer, P
H ₃ , PF ₃ or the like is used. When depositing a thin film of a crystalline phase or a layer having a small light absorption or a wide band gap such as SiC, increase the ratio of the diluent gas to the source gas,
It is preferable to introduce a relatively high power high frequency.

(Means for Forming Underlayer)
As a method of forming the first method, plasma CVD using high frequency
Amorphous semiconductor layer 1 showing first conductivity type by method
02-1A, a method of sequentially laminating semiconductor layers 102-1B having the first conductivity type and including a crystal phase, and sequentially depositing a doped amorphous layer and a non-doped amorphous layer by a plasma CVD method using high frequency,
There are a method of partially crystallizing using a crystallization means, a method of depositing an amorphous layer while changing the concentration of a dopant, and then partially crystallizing using a crystallization means.

(Second transparent conductive layer) Second transparent conductive layer 1
Reference numeral 03 denotes an electrode on the light incident side, and can also serve as an anti-reflection film by appropriately setting its film thickness. The second transparent conductive layer 103 is a semiconductor layer 102
Is required to have a high transmittance in a wavelength region that can absorb light and to have a low resistivity. Preferably 550
The transmittance in nm is 80% or more, more preferably 85%.
% Is desirable. The resistivity is 5 × 10 ^-3 Ωc
m, more preferably 1 × 10 ⁻³ Ωcm or less. As a material of the second transparent conductive layer 103, IT0, ZnO, In ₂ O ₃ or the like can be preferably used. As the formation method, methods such as vapor deposition, CVD, spray, spin-on, and immersion are suitable. A substance that changes conductivity may be added to these materials.

(Current Collecting Electrode) The current collecting electrode 104 is provided on the transparent electrode 103 to improve current collecting efficiency. As the forming method, a method of forming a metal of an electrode pattern by sputtering using a mask, a method of printing a conductive paste or a solder paste, a method of fixing a metal wire with a conductive paste, and the like are preferable.

Incidentally, if necessary, protective layers may be formed on both surfaces of the photovoltaic element. At the same time, an auxiliary material such as a steel plate may be used in combination on the back surface (light incident side and reflection side) of the photovoltaic element.

[0048]

EXAMPLES In the following examples, the present invention will be specifically described by taking a solar cell as an example of a photovoltaic element, but these examples do not limit the content of the present invention at all.

Example 1 A silicon-based thin film was formed by the following procedure using the deposited film forming apparatus 201 shown in FIG.

FIG. 2 is a schematic sectional view showing an example of a deposited film forming apparatus for producing a silicon-based thin film and a photovoltaic element according to the present invention. The deposited film forming apparatus 201 shown in FIG.
Substrate sending container 202, semiconductor forming vacuum container 211
218 and the substrate take-up container 203 are connected via a gas gate. A strip-shaped conductive substrate 204 is set in the deposition film forming apparatus 201 through each container and each gas gate. The strip-shaped conductive substrate 204 is unwound from a bobbin provided in the substrate unloading container 202, and is wound on another bobbin by the substrate unwinding container 203.

The semiconductor forming vacuum vessels 211 to 218
Each has a deposition chamber, and discharge electrodes 2 in the discharge chamber.
Glow discharge is generated by applying high frequency power from 41 to 248 to the high frequency power supply 251 to 258, thereby decomposing the source gas and depositing a semiconductor layer on the conductive substrate 204. Also, each semiconductor forming vacuum vessel 21
3, 214, 217, and 218 have gas introduction pipes 233, 234, and 23 for introducing a source gas and a dilution gas.
7, 238 are connected. In addition, semiconductor vacuum vessel 2
11, 212, 215 and 216, gas introduction pipes 231a and 231 are provided on both the upstream side and the downstream side in the substrate transport direction.
b, 232a, 232b, 235a, 235b, 236
a, 236b.

Between the semiconductor forming vacuum vessel 212 and the semiconductor forming vacuum vessel 213 and the semiconductor forming vacuum vessel 21
Crystallizing containers 221 and 222 for crystallization means and excimer laser devices 223 and 224 are provided between the semiconductor device 6 and the semiconductor forming vacuum container 217, respectively.

The deposited film forming apparatus 201 shown in FIG. 2 has eight semiconductor forming vacuum apparatuses. In the following embodiment, it is necessary to generate a glow discharge in all the semiconductor forming vacuum vessels. However, the presence or absence of glow discharge in each container can be selected according to the layer configuration of the photovoltaic element to be manufactured. Further, each semiconductor forming apparatus is provided with a film formation region adjustment plate (not shown) for adjusting a contact area between the conductive substrate 204 and the discharge space in each deposition chamber. Thus, the thickness of each semiconductor film formed in each container can be adjusted.

First, a strip-shaped substrate (40 cm wide, 200 m long, 0.125 mm thick) made of stainless steel (SUS430BA) was sufficiently degreased and washed, and was mounted on a continuous sputtering device (not shown), and the Al electrode was targeted. An Al thin film having a thickness of 100 nm was sputter deposited. Further, using a ZnO target, a thickness of 1.2 μm
The ZnO thin film was sputter-deposited on the Al thin film to form a strip-shaped conductive substrate 204.

Next, a bobbin around which the conductive substrate 204 is wound is mounted on the substrate delivery container 202, and the conductive substrate 204 is loaded with the gas gate on the loading side, and the semiconductor forming vacuum containers 211 and 2.
12, 213, 214, 215, 216, 217, 21
8. The substrate take-up container 20 is passed through the gas gate on the carry-out side.
3, the tension was adjusted so that the belt-shaped conductive substrate 204 did not sag. Then, the substrate delivery container 20
2. Vacuum container 211, 212, 213, 2 for semiconductor formation
14, 215, 216, 217, 218, crystallization vessel 2
21, 222 and the substrate take-up container 203 were sufficiently evacuated to 5 × 10 ⁻⁶ Torr or less by an evacuation system including a vacuum pump.

Next, while operating the vacuum evacuation system, the gas introduction pipe 2 was introduced into the vacuum chambers 211, 212, and 213 for semiconductor formation.
31-a, 231-b, 232-a, 232-b, 23
From 3 raw material gas and dilution gas were supplied.

Further, the semiconductor forming vacuum vessels 211 and 21
200 sccm H ₂ gas was supplied from a gas introduction pipe to the semiconductor forming vacuum vessels other than ₂ , 213, and simultaneously 500 sccm H ₂ gas as a gate gas was supplied to each gas gate from each gate gas supply pipe (not shown). In this state, the evacuation capacity of the evacuation system was adjusted to adjust the pressure in the semiconductor formation vacuum vessels 211, 212, and 213 to a desired pressure. The forming conditions are as shown in Table 1.

[0058]

[Table 1]

Vacuum containers 211, 212, and 2 for forming semiconductors
When the pressure in the substrate 13 is stabilized, the substrate
The movement of the conductive substrate 204 in the direction from 02 to the substrate take-up container 203 was started. While moving the conductive substrate 204, the infrared lamp heater in the crystallization container 221 was heated so that the conductive substrate 204 reached 650 ° C.

Next, the semiconductor forming vacuum vessels 211 and 21
The high frequency power supplies 251, 2
A high frequency is introduced from 52 and 253 to generate a glow discharge in the deposition chamber in the semiconductor forming vacuum vessels 211, 212 and 213, and an amorphous n-type semiconductor layer (thickness 30 nm) and an amorphous i-type on the conductive substrate 204. After a semiconductor layer (thickness: 30 nm) is formed, a heat treatment is performed by a lamp heater to form a base layer in which a part of the amorphous n-type semiconductor layer and the amorphous i-type semiconductor layer is crystallized. Phase-containing i-type semiconductor layer (1.5 μm thick)
m) and a silicon-based thin film was formed (Example 1-).
1). Here, a high frequency power of 13.56 MHZ and a power of 5 mW / cm ³ is applied to the vacuum vessel 211 for semiconductor formation, and a frequency of 13.56 is applied to the vacuum vessel 212 for semiconductor formation.
MHZ, high-frequency power of power 5 mW / cm ³ , and high-frequency power of frequency 100 MHZ, power 20 mW / cm ³ were introduced into the vacuum chamber 213 for semiconductor formation.

Next, as shown in Table 1, the gas introduced into the semiconductor vacuum vessel 211 was supplied to the upstream and downstream sides of the transfer.
_A silicon-based thin film was formed in the same manner as in Example 1-1 except that the flow rates of the _three gases were different (Example 1-2).

Next, a silicon-based thin film was formed in the same manner as in Example 1-1, except that heat treatment for crystallization by a lamp heater was not performed (Comparative Example 1).

Next, as a result of evaluating the crystallinity of the silicon-based thin films prepared in Example 1-1 and Comparative Example 1 by the X-ray diffraction method, the silicon-based thin film of Example 1-1 has a higher diffraction intensity. Diffraction lines were sharp. The Scherrer radius was determined from the half width of the diffraction peak of (220) reflection, and the Scherrer radius of the silicon-based thin film formed in Example 1-1 was determined.
The err radius was 2.5 times as large as the Scherrer radius of the silicon-based thin film prepared in Comparative Example 1.
Further, the silicon-based thin film prepared in Example 1-1 was
The cross section was observed by using As shown in the schematic diagram of the cross-sectional observation by TEM in FIG. 7, an amorphous semiconductor layer and a semiconductor layer containing a crystal phase were sequentially formed on ZnO.
The crystal grain size of the semiconductor layer including the crystal phase gradually increases toward the top, and it is observed that the i-type semiconductor layer including the crystal phase continuously grows from the underlayer. No amorphous layer was observed. In the cross-sectional observation of the silicon-based thin film of Comparative Example 1, an amorphous layer was observed in the initial film of the i-type semiconductor layer including the crystal phase. The silicon-based thin film of Example 1-2 has a Scherrer radius of 1.15 compared to the silicon-based thin film of Example 1-1.
It was twice. SIMS analysis revealed that in the underlayer of Example 1-2, a distribution was observed in which the concentration of P atoms decreased from the conductive substrate side toward the i-type semiconductor layer. Was not recognized.

As described above, the silicon-based thin film of the present invention has excellent characteristics that it has excellent crystallinity, has a large crystal grain size, and can continuously generate a crystal phase from the underlayer. You can see it has. Further, it can be seen that the configuration in which the dopant concentration of the underlayer decreases toward the crystal phase has more excellent characteristics.

Example 2 The pin type photovoltaic element shown in FIG. 4 was formed by the following procedure using the deposited film forming apparatus 201 shown in FIG. FIG. 4 is a schematic cross-sectional view schematically illustrating an example of a photovoltaic device having a silicon-based thin film of the present invention. In the figure, the same members as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The semiconductor layers of this photovoltaic element include an amorphous n-type semiconductor layer 102-1A, an n-type semiconductor layer 102-1B containing a crystalline phase, and a microcrystalline i-type semiconductor layer 102-2.
And a microcrystalline p-type semiconductor layer 102-3. That is, this photovoltaic element is a so-called pin type single cell photovoltaic element.

As in the first embodiment, the belt-shaped conductive substrate 20
4 is mounted on the deposition film forming apparatus 201, and the substrate sending container 202, the semiconductor forming vacuum containers 211 and 21 are prepared.
2, 213, 214, 215, 216, 217, 21
8. The substrate take-up container 203 was sufficiently evacuated to 5 × 10 ⁻⁶ Torr or less by a vacuum evacuation system including a vacuum pump (not shown).

Next, while operating the vacuum evacuation system, the gas introduction pipe 231-
a, 231-b, 232-a, 232-b, 233, 2
The raw material gas and the dilution gas were supplied from 34.

Further, vacuum containers 211 to 21 for forming semiconductors
For the semiconductor formation vacuum vessels other than 4
0 sccm of H ₂ gas is supplied, and at the same time, 5 g of gate gas is supplied from each gate gas supply pipe (not shown) to each gas gate.
00 sccm of H ₂ gas was supplied. In this state, the evacuation capacity of the evacuation system is adjusted so that the semiconductor forming vacuum vessel 21 is formed.
The pressure within 1-214 was adjusted to the desired pressure. The forming conditions are as shown in Table 2.

[0069]

[Table 2]

Semiconductor forming vacuum chambers 211, 212, 2
When the pressure in the substrate 13 is stabilized, the substrate
The movement of the conductive substrate 204 in the direction from 02 to the substrate take-up container 203 was started. While moving the conductive substrate 204, the infrared lamp heater in the crystallization container 221 was heated so that the conductive substrate 204 reached 650 ° C.

Next, semiconductor forming vacuum vessels 211 to 21
4, high-frequency power supplies 251-2
A high frequency is introduced from 54 and the semiconductor forming vacuum vessel 211
Glow discharge is generated in the deposition chambers 214 to 214 to form an amorphous n-type semiconductor layer (thickness 30 nm) and an amorphous i-type semiconductor layer (thickness 30 nm) on the conductive substrate 204. After that, a heating process using a lamp heater is performed to form an underlayer in which a part of the amorphous n-type semiconductor layer and the amorphous i-type semiconductor layer is crystallized. 1.5 μm) and a microcrystalline p-type semiconductor layer (thickness: 10 nm) were formed to form a photovoltaic element. At the time of forming the microcrystalline p-type semiconductor layer, the semiconductor forming vacuum vessel 214 has a frequency of 13.5.
6 MHz and a power of 30 mW / cm ³ were introduced, and the other layers were the same as in Example 1. Next, the formed band-shaped photovoltaic element was processed into a solar cell module of 36 cm × 22 cm using a continuous modularization device (not shown) (Example 2).

Next, a solar cell module was formed in the same manner as in Example 1 except that heat treatment for crystallization by a lamp heater was not performed (Comparative Example 2).

The photoelectric conversion efficiencies of the solar cell modules prepared in Example 2 and Comparative Example 2 were measured using a solar simulator (AM 1.5, 100 mW / cm ² ). The photoelectric conversion efficiency of the solar cell module of Example 2 was 1
The value of the photoelectric conversion efficiency of the solar cell module prepared in Comparative Example 2 when normalized to 0.85 was 0.85. From the above, it is understood that the solar cell module including the photovoltaic element of the present invention has excellent features.

Example 3 The pin type photovoltaic element shown in FIG. 4 was formed by the following procedure using the deposited film forming apparatus 201 shown in FIG.

As in the first embodiment, the strip-shaped conductive substrate 20
4 is mounted on the deposition film forming apparatus 201, and the substrate sending container 202, the semiconductor forming vacuum containers 211 and 21 are prepared.
2, 213, 214, 215, 216, 217, 21
8. The substrate take-up container 203 was sufficiently evacuated to 5 × 10 ⁻⁶ Torr or less by a vacuum evacuation system including a vacuum pump (not shown).

Next, while operating the vacuum evacuation system, the gas introduction pipe 231-
a, 231-b, 232-a, 232-b, 233, 2
34, the raw material gas and the dilution gas were supplied.

Further, vacuum containers 211 to 21 for forming semiconductors
For the semiconductor formation vacuum vessels other than 4
0 sccm of H ₂ gas is supplied, and at the same time, 5 g of gate gas is supplied from each gate gas supply pipe (not shown) to each gas gate.
00 sccm of H ₂ gas was supplied. In this state, the evacuation capacity of the evacuation system is adjusted so that the semiconductor forming vacuum vessel 21 is formed.
The pressure within 1-214 was adjusted to the desired pressure. The forming conditions are as shown in Table 3.

[0078]

[Table 3]

Semiconductor-forming vacuum vessels 211, 212, and 2
When the pressure in the substrate 13 is stabilized, the substrate
The movement of the conductive substrate 204 in the direction from 02 to the substrate take-up container 203 was started.

In the same manner as in the first embodiment, high-frequency power is applied to the discharge electrodes 241 to 244 in the vacuum chambers 211 to 214 for forming semiconductors from the high-frequency power sources 251 to 254, and the discharge chambers in the vacuum chambers 211 to 214 for forming semiconductors are introduced. A glow discharge occurs, on the conductive substrate 204, an amorphous n-type semiconductor layer (thickness 30 nm), a microcrystalline n-type semiconductor layer (thickness 30 nm), and an i-type semiconductor layer including a crystalline phase on the conductive substrate 204. (Thickness: 1.5 μm), microcrystalline p-type semiconductor layer (thickness: 10 n)
m) to form a photovoltaic element. Next, the formed band-shaped photovoltaic element was processed into a solar cell module of 36 cm × 22 cm using a continuous modularization device (not shown) (Example 3).

Next, Example 3 was repeated except that the amorphous n-type semiconductor layer was not deposited in the vacuum chamber 211 for forming a semiconductor.
A solar cell module was formed in the same manner as described above (Comparative Example 3).

The photoelectric conversion efficiencies of the solar cell modules prepared in Example 3 and Comparative Example 3 were measured using a solar simulator (AM 1.5, 100 mW / cm ² ). The photoelectric conversion efficiency of the solar cell module of Example 3 was 1
The value of the photoelectric conversion efficiency of the solar cell module prepared in Comparative Example 3 when standardized to was 0.9. Example 3
When the short-circuit current of the solar cell module was normalized to 1, the value of the short-circuit current of the solar cell module created in Comparative Example 3 was 0.9.
It seems that it mainly depended on the short-circuit current.

In addition, the cross-cut tape method (interval space 1 between cuts)
mm, the number of squares of 100) was used to examine the adhesion between the conductive substrate and the semiconductor layer. In addition, the solar cell module whose initial photoelectric conversion efficiency was measured in advance
Installed in a dark place at 5 ° C and 85% humidity and kept for 30 minutes, then 7
Reduce the temperature to -20 ° C over 0 minutes, hold for 30 minutes, and return to 70
This cycle of returning the temperature to 85 ° C. and the humidity of 85% over a period of 100 minutes was repeated 100 times, and then the photoelectric conversion efficiency was measured again to examine the change in the photoelectric conversion efficiency by the temperature and humidity test.

Further, while the solar cell module whose initial photoelectric conversion efficiency was measured in advance was held at 50 ° C., it was irradiated with AM1.5, 100 mW / cm ² simulated sunlight for 500 hours, and then again subjected to photoelectric conversion. Measure efficiency,
The change of the photoelectric conversion efficiency by the light deterioration test was examined. Table 4 shows the results.

[0085]

[Table 4]

As shown in Table 4, the solar cell module of Example 3 including the photovoltaic element of the present invention was different from the solar cell module of Comparative Example 3 in terms of initial conversion efficiency, adhesion,
Excellent durability against temperature and humidity tests and light deterioration tests.
From the above, it can be seen that the solar cell module including the photovoltaic element of the present invention has excellent features.

(Embodiment 4) The discharge electrodes 241 in the vacuum chambers 211 and 212 for forming a semiconductor under the same conditions as those of the embodiment 2
High-frequency power is supplied from a high-frequency power source 251 or 252 to the deposition chamber 242 to generate a glow discharge in a deposition chamber in the vacuum chamber 211 or 212 for forming a semiconductor, and an amorphous n-type semiconductor layer is formed on the conductive substrate 204 or on the conductive substrate 204. (Thickness 30n
m), after forming an amorphous i-type semiconductor layer (thickness: 30 nm), heat treatment was performed by changing the heating temperature of the substrate by a lamp heater so as to change the crystallization rate of the underlayer (Example). 4-1 to 4-3, Comparative Example 4-
1). After forming the underlayer under the same conditions as those underlayers, as in Example 2, an i-type semiconductor layer containing a crystalline phase (thickness: 1.5 μm), a microcrystalline p-type semiconductor layer (thickness: 10
nm) to form a photovoltaic element. Next, the formed strip-shaped photovoltaic element was processed into a solar cell module of 36 cm × 22 cm by using a continuous modularization device (not shown) (Examples 4-4 to 4-6, Comparative Example 4-2).

The photoelectric conversion efficiencies of the solar cell modules prepared in Examples 4-4 to 4-6 and Comparative Example 4-2 were measured using a solar simulator (AM 1.5, 100 mW / cm ² ). Table 5 shows the value of the photoelectric conversion efficiency of each solar cell module when the photoelectric conversion efficiency of the solar cell module of Example 4-4 was normalized to 1. As shown in Table 5, the solar cell module in which the Raman scattering intensity due to the amorphous component of the underlayer is equal to or less than the Raman scattering intensity due to the crystalline component exhibits excellent photoelectric conversion efficiency. It can be seen that the solar cell module including the electromotive element has excellent features.

[0089]

[Table 5]

Example 5 The photovoltaic element shown in FIG. 6 was formed by the following procedure using the deposited film forming apparatus 201 shown in FIG. FIG. 6 is a schematic cross-sectional view schematically illustrating an example of a photovoltaic device having a silicon-based thin film of the present invention. In the figure,
The same members as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The semiconductor layer of this photovoltaic element includes an amorphous n-type semiconductor layer 102-1A and an n-type semiconductor layer 1 including a crystalline phase.
02-1B, microcrystalline i-type semiconductor layer 102-2, microcrystalline p-type semiconductor layer 102-3, amorphous n-type semiconductor layer 1
02-4A and an n-type semiconductor layer 102-4B containing a crystal phase
And a microcrystalline i-type semiconductor layer 102-5 and a microcrystalline p-type semiconductor layer 102-6. That is, this photovoltaic element is a so-called pinpin type double cell photovoltaic element.

As in the first embodiment, the strip-shaped conductive substrate 20
4 is mounted on the deposition film forming apparatus 201, and the substrate sending container 202, the semiconductor forming vacuum containers 211 and 21 are prepared.
2, 213, 214, 215, 216, 217, 21
8. The substrate take-up container 203 was sufficiently evacuated to 5 × 10 ⁻⁶ Torr or less by a vacuum evacuation system including a vacuum pump (not shown).

Next, while operating the vacuum evacuation system, the gas introduction pipe 231-
a, 231-b, 232-a, 232-b, 233, 2
34, 235-a, 235-b, 236-a, 236-
b, 237 and 238 supplied the raw gas and the diluent gas.

Further, from each gate gas supply pipe (not shown),
500 sccm of H _{2 is used} as a gate gas for each gas gate.
Gas was supplied. In this state, the evacuation capacity of the evacuation system was adjusted to adjust the pressure in the semiconductor formation vacuum vessels 211 to 218 to a desired pressure. The conditions for forming the bottom cell and the top cell are the n-layer and the p-layer as shown in Table 2, and the i-type layer is SiF ₄ = 50 sccm, H ₂ = 300 sccm,
The test was performed at 400 ° C. and 100 mTorr.

When the pressure in the semiconductor forming vacuum containers 211 to 218 was stabilized, the movement of the conductive substrate 204 in the direction from the substrate sending container 202 to the substrate take-up container 203 was started.

Next, vacuum containers 211 to 21 for forming semiconductors
8, high-frequency power supplies 251-2
A high frequency is introduced from 58 and the semiconductor forming vacuum vessel 211
A glow discharge is generated in the deposition chambers of 218 to 218 to form an amorphous n-type semiconductor layer (thickness 30 nm) and an amorphous i-type semiconductor layer (thickness 30 nm) on the conductive substrate 204. After that, crystallization treatment with a XeCl excimer laser (pulse energy 150 m
J / cm ² ) to form an underlayer in which the amorphous n-type semiconductor layer and part of the amorphous i-type semiconductor layer are crystallized, and then form an i-type semiconductor layer containing a crystalline phase (film thickness 2.0 μm). ), Forming a microcrystalline p-type semiconductor layer (thickness 10 nm) to form a bottom cell, and further forming an amorphous n-type semiconductor layer (thickness 30 nm) and an amorphous i-type semiconductor layer (thickness 30 nm). Crystallization by XeCl oximer laser (pulse energy 150m
J / cm ² ) to form an underlayer in which the amorphous n-type semiconductor layer and a part of the amorphous i-type semiconductor layer are crystallized, and then form an i-type semiconductor layer containing a crystalline phase (film thickness 1.2 μm). ), A microcrystalline p-type semiconductor layer (thickness: 10 nm) was formed to form a top cell, thereby forming a double-cell photovoltaic element.

Here, the semiconductor forming vacuum vessel 211 has
13.56 MHz frequency, 5 mW / cm power^ThreeHigh lap of
Wave power is applied to the semiconductor forming vacuum vessel 212 at a frequency of 1
3.56MHZ, power 5mW / cm^ThreeHigh frequency power
And a microwave application in the vacuum vessel 213 for semiconductor formation.
Frequency 2.45 GHZ, power via cater 261
50mW / cm^ThreeHigh-frequency power to vacuum
Device 214 has a frequency of 13.56 MHz and a power of 30 mW
/ Cm^ThreeOf the high-frequency power of the semiconductor container 215
Has a frequency of 13.56 MHZ and a power of 5 mW / cm^Threeof
The high-frequency power is supplied to the vacuum chamber 216 for forming a semiconductor.
13.56 MHZ, power 5 mW / cm^ThreeHigh frequency power
And the microwave application in the vacuum chamber 217 for semiconductor formation.
Frequency 2.45 GHZ, power via cater 262
50mW / cm^ThreeHigh-frequency power to vacuum
218 has a frequency of 13.56 MHz and a power of 30 mW
/ Cm ^ThreeOf high frequency power was introduced.

Next, using a continuous modularization device (not shown), the formed band-shaped photovoltaic element was
(Example 5).

The solar cell module of Example 5 exhibited 1.2 times the photoelectric conversion efficiency as compared with the solar cell module of Example 2, and the solar cell module of Example 5 exhibited the adhesion, temperature and humidity tests. Thus, the solar cell module including the photovoltaic element of the present invention has excellent features.

[0099]

As described above, the present invention relates to a method for forming a photovoltaic element containing a crystal phase by a plasma CVD method using a high frequency, comprising: an amorphous semiconductor layer having a first conductivity type; An underlayer formed by sequentially laminating semiconductor layers containing a crystal phase showing a conductivity type, an i-type semiconductor layer containing a crystal phase, and a pin junction formed by sequentially laminating a non-single-crystal semiconductor layer showing a second conductivity type, By employing a configuration in which the crystal grain size of the semiconductor layer including the crystal phase having the first conductivity type is increased toward the i-type semiconductor layer including the crystal phase, the lower layer is not significantly damaged. A semiconductor layer containing a high-quality crystal phase can be formed, an increase in the crystal grain size of the i-type semiconductor layer including the crystal phase, a reduction in defect density, and an improvement in the interface with the underlayer can be achieved. , Good photoelectric conversion characteristics Photovoltaic devices having environmental resistance were obtained.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing one example of a photovoltaic device of the present invention.

FIG. 2 is a schematic cross-sectional view showing one example of a deposited film forming apparatus for producing a silicon-based thin film and a photovoltaic element of the present invention.

FIG. 3 is a schematic cross-sectional view showing an example of a photovoltaic device including a silicon-based thin film of the present invention.

FIG. 4 is a schematic cross-sectional view showing an example of a photovoltaic device including a silicon-based thin film of the present invention.

FIG. 5 is a schematic sectional view showing an example of a deposited film forming apparatus for producing a silicon-based thin film and a photovoltaic element of the present invention.

FIG. 6 is a schematic cross-sectional view showing an example of a photovoltaic device including a silicon-based thin film of the present invention.

FIG. 7 is a schematic diagram of a cross-sectional observation of a silicon-type thin film of the present invention by TEM.

[Explanation of symbols]

101: Substrate 101-1: Base 101-2: Metal layer 101-3: Transparent conductive layer 102: Semiconductor layer 102-1: Underlayer 102-1A: Amorphous semiconductor layer showing first conductivity type 102-1B: First layer Semiconductor layer showing one conductivity type and containing a crystal phase 102-2: i-type semiconductor layer containing a crystal phase 102-3: Non-single-crystal semiconductor layer showing a second conductivity type 102-4A: First conductivity type Amorphous semiconductor layer 102-4B: semiconductor layer showing a first conductivity type and containing a crystal phase 102-5: i-type semiconductor layer containing a crystal phase 102-6: non-single-crystal semiconductor layer 103 showing a second conductivity type : Transparent electrode 104: Current collecting electrode 201: Deposited film forming device 202: Substrate sending container 203: Substrate winding container 204: Conductive substrate 211-218: Vacuum container for semiconductor formation 221, 222: Crystallization Vessels 223 and 224: an excimer laser device 231-a, 231-b, 232-a, 232-b, 2
33, 234, 235-a, 235-b, 236-a,
236-b, 237, 238: gas introduction tubes 241-248: discharge electrodes 251-258: high frequency power supply 261-262: microwave applicator

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Makoto Higashikawa 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Takaichi Matsuda 3-30-2 Shimomaruko, Ota-ku, Tokyo Kyano 5F051 AA04 AA05 BA14 CA03 CA16 CA22 CB04 CB24 CB25 DA04 DA17 GA02

Claims (10)

[Claims] 1. A photovoltaic device comprising: a silicon-based semiconductor layer having at least one set of pin junctions; and a second transparent conductive layer on a substrate having at least a first transparent conductive layer laminated on a substrate. In a power device, the silicon-based semiconductor layer is an underlayer formed by sequentially stacking an amorphous semiconductor layer having a first conductivity type and a semiconductor layer having a first conductivity type and including a crystal phase, and an i-type including a crystal phase. The semiconductor layer includes a pin junction in which a non-single-crystal semiconductor layer having the second conductivity type is sequentially stacked, and the crystal grain size of the semiconductor layer including the crystal phase having the first conductivity type includes the crystal phase. A photovoltaic device characterized by increasing toward an i-type semiconductor layer. 2. The method according to claim 1, wherein the underlayer is formed by sequentially depositing a doped amorphous layer and a non-doped amorphous layer and then partially crystallizing the layer using crystallization means. The photovoltaic device according to any one of the preceding claims. 3. The photovoltaic device according to claim 2, wherein said crystallization means is laser irradiation. 4. The photovoltaic device according to claim 2, wherein said crystallization means is performed by a heat treatment. 5. The photovoltaic device according to claim 1, wherein the Raman scattering intensity caused by the amorphous component of the underlayer is equal to or less than the Raman scattering intensity caused by the crystalline component. 6. The photovoltaic device according to claim 1, wherein the dopant concentration of the underlayer decreases toward the i-type semiconductor layer containing the crystal phase. 7. The semiconductor device according to claim 1, wherein the semiconductor layer is formed by a plasma CVD method using a high frequency.
3. The photovoltaic element according to claim 1. 8. The high frequency is 10 MHz or more and 10 GHz.
The photovoltaic device according to claim 7, wherein: 9. The photovoltaic device according to claim 1, wherein the substrate is a conductive substrate. 10. The semiconductor layer having the first conductivity type and including a crystal phase has a thickness of d, and the semiconductor layer having the first conductivity type and having a crystal phase has the longest crystal grain size. 2. The photovoltaic device according to claim 1, wherein the value of r / d is 100 or less, where r is the length.