JP2001358171A - Structure for semiconductor element mounting - Google Patents

Structure for semiconductor element mounting

Info

Publication number
JP2001358171A
JP2001358171A JP2000175594A JP2000175594A JP2001358171A JP 2001358171 A JP2001358171 A JP 2001358171A JP 2000175594 A JP2000175594 A JP 2000175594A JP 2000175594 A JP2000175594 A JP 2000175594A JP 2001358171 A JP2001358171 A JP 2001358171A
Authority
JP
Japan
Prior art keywords
semiconductor element
wall
connection
mounting
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000175594A
Other languages
Japanese (ja)
Inventor
Hiroyuki Sasaki
裕之 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2000175594A priority Critical patent/JP2001358171A/en
Publication of JP2001358171A publication Critical patent/JP2001358171A/en
Pending legal-status Critical Current

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  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a structure for semiconductor element mounting, capable of mounting at a high density, without short-circuiting connecting metal bumps in mounting semiconductor elements by a flip-chip type facedown mounting system. SOLUTION: In the structure for semiconductor element mounting, comprising a metal layer 8 on connecting terminals 9 of a semiconductor element 7 and metal bumps 2 on the metal layer 8 with respect to wirings 3 and connecting terminals 4, formed on a wiring board 5 and an anisotropically conductive adhesive 6 or anisotropically conductive film for bonding one side of the wiring board 5, having the wirings 3 and the connecting terminals 4 to one side of the semiconductor element 7 which has the metal bumps 2 with electrical connections made between the connecting terminals in the facedown mounting system, and insulative material-made walls 1 are provided between the adjacent connecting terminals.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子をフリ
ップチップ方式のフェイスダウン実装方式で実装した半
導体素子実装構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting structure in which a semiconductor element is mounted by a flip-chip type face-down mounting method.

【0002】[0002]

【従来の技術】ビデオカメラ、デジタルカメラ、プリン
タ等の情報処理装置では、小型化、薄型化、低消費電力
化、高精細化およびカラー化が進み、また表示パネルで
は前記事柄に加えて大画面化が図られている。これに伴
い実装される半導体素子も高集積化、大型化、高速化、
低消費電力化が図られ、入出力点数が増加する傾向にあ
る。
2. Description of the Related Art In information processing apparatuses such as video cameras, digital cameras, and printers, miniaturization, thinning, low power consumption, high definition, and colorization are progressing. The screen is planned. The semiconductor elements to be mounted along with this are also highly integrated, larger, faster,
Power consumption is reduced, and the number of input / output points tends to increase.

【0003】従って、半導体素子と配線基板の実装形態
も高密度化が求められるようになった。従来は、半導体
素子をリードフレーム上に接着し半導体素子の端子とリ
ードフレームの端子をワイヤーボンディングにより接続
し半導体素子の周囲を樹脂等により封止する実装技術が
多用されていた。しかし、高密度実装を実現するため
に、半導体素子に複数の接続用金属突起を設け、その面
と配線基板の接続用端子を設けた面とを向かい合わせて
加熱圧着してフリップチップ方式で接続する、いわゆる
フェイスダウン実装方式が用いられるようになった。
[0003] Accordingly, it has been required to increase the mounting density of the semiconductor element and the wiring board. Conventionally, a mounting technique of bonding a semiconductor element on a lead frame, connecting terminals of the semiconductor element and terminals of the lead frame by wire bonding, and sealing the periphery of the semiconductor element with a resin or the like has been frequently used. However, in order to realize high-density mounting, multiple connection metal projections are provided on the semiconductor element, and the surface is connected to the surface on which the connection terminals of the wiring board are provided with the connection terminals by heat and pressure to connect them in a flip-chip manner In other words, a so-called face-down mounting method has been used.

【0004】フリップチップ方式によるフェイスダウン
実装方式においては、半導体素子と配線基板の接続に
は、ワイヤーボンディングに変わりフィルムや接着剤の
異方性導電樹脂や半田バンプ、導電性ペースト、金−金
接続等が用いられている。その結果、フェイスダウン実
装における接続用端子間ピッチは100μm〜60μ
m、バンプ(接続用金属突起)サイズは60×60μm
〜40×50μm、また接続用端子間スペースは40〜
20μmといったファインピッチ化が進み、接続用端子
数が数百に達するものもある。
[0004] In the face-down mounting method using the flip chip method, instead of wire bonding, the semiconductor element and the wiring board are connected by anisotropic conductive resin such as a film or an adhesive, solder bumps, conductive paste, or gold-gold connection. Etc. are used. As a result, the pitch between connection terminals in face-down mounting is 100 μm to 60 μm.
m, bump (metal projection for connection) size is 60 × 60 μm
~ 40 × 50μm, space between connecting terminals is 40 ~
Fine pitches such as 20 μm have progressed, and some of them have several hundred connection terminals.

【0005】加熱圧着による接続するフェイスダウン実
装方式において、加圧力と配線基板−半導体素子の接続
抵抗の関係は、図3に示すように加圧力が大きくなる程
接続抵抗が低く且つ抵抗のバラツキが小さくなる。しか
し接続時の加圧により接続用金属突起がつぶれ横方向に
広がる。そのため加圧力が大きくなる程、前記金属突起
(バンプ)のつぶれ量が大きくなり横への広がりも大き
くなる。
[0005] In the face-down mounting method of connection by heat compression, the relationship between the pressing force and the connection resistance between the wiring board and the semiconductor element is such that as the pressing force increases, the connection resistance decreases and the resistance varies. Become smaller. However, the metal projection for connection collapses and expands in the lateral direction due to the pressure during connection. Therefore, as the pressing force increases, the amount of crushing of the metal protrusion (bump) increases, and the lateral spread also increases.

【0006】[0006]

【発明が解決しようとする課題】高密度実装化の傾向は
今後、益々進む傾向にある。高密度実装の一例として、
接続端子間ピッチ40μm、バンプサイズ25μm×8
0μm、接続間スペース15μm、接続用端子としてA
lとITO(Indium Tin Oxide)膜を施した硝子基板に
接続用突起として高さ14μmの金メッキバンプを形成
した半導体素子を異方性導電接着剤を用い、低抵抗接続
を目的に加熱温度200℃、30kg/mm2でフェイ
スダウン実装を行なった時の実装構造の模式図を、図2
(A),(B)に示す。
The tendency for high-density mounting will tend to increase further in the future. As an example of high-density mounting,
Connection terminal pitch 40μm, bump size 25μm × 8
0 μm, connection space 15 μm, A for connection terminal
1 and a glass substrate on which an ITO (Indium Tin Oxide) film has been formed, a semiconductor element having a 14 μm-high gold-plated bump formed as a connection projection using an anisotropic conductive adhesive, and a heating temperature of 200 ° C. for the purpose of low resistance connection FIG. 2 is a schematic diagram of a mounting structure when face-down mounting is performed at 30 kg / mm 2 .
(A) and (B) show.

【0007】図2(A)は、従来のフェイスダウン方式
による実装断面図であり、図2(B)は図2(A)の実
装状態を硝子基板上面から透過した図である。
FIG. 2A is a cross-sectional view of a conventional face-down mounting method, and FIG. 2B is a view of the mounting state of FIG.

【0008】5は硝子配線基板であり、Al配線3と接
続端子4が設けられている。一方、半導体素子7には接
続端子9上にメタル層8と金属突起として金メッキバン
プ2が形成されている。Al配線3と接続端子4が設け
られた硝子基板5面と金メッキバンプ2が形成された半
導体素子7の面を対向し、異方性導電接着剤6を用い
て、加圧接着することにより電気的接続を図るようにな
っている。、図2(A)の接続断面図および図2(B)
の硝子基板上面から硝子を透して見た図から分かるよう
に、加圧力により金メッキバンプ2がつぶれ隣接する金
メッキバンプ同士がショートを起こし、半導体素子と配
線基板の電気的接続が不良となる。このバンプのつぶれ
によるショート現象は、ファインピッチ化が進み、接続
用端子間が短くなるほど、発生しやすくなる。
Reference numeral 5 denotes a glass wiring board on which Al wiring 3 and connection terminals 4 are provided. On the other hand, the semiconductor element 7 has a metal layer 8 and a gold-plated bump 2 as a metal projection on a connection terminal 9. The surface of the glass substrate 5 on which the Al wirings 3 and the connection terminals 4 are provided and the surface of the semiconductor element 7 on which the gold-plated bumps 2 are formed face each other, and are electrically bonded by pressure using an anisotropic conductive adhesive 6. The connection is intended to be established. 2 (A) and FIG. 2 (B).
As can be seen from the view of the glass substrate seen through the glass substrate from above, the gold plating bumps 2 are crushed by the pressing force and adjacent gold plating bumps are short-circuited, and the electrical connection between the semiconductor element and the wiring board becomes poor. The short-circuit phenomenon due to the crushing of the bump is more likely to occur as the fine pitch progresses and the distance between the connection terminals becomes shorter.

【0009】本発明が解決しようとする課題は、フリッ
プチップ方式のフェイスダウン実装により半導体素子が
実装される半導体素子実装構造において、接続用金属突
起間がショートすることがなく高密度実装が可能な半導
体素子実装構造を提供することである。
The problem to be solved by the present invention is that in a semiconductor element mounting structure in which a semiconductor element is mounted by face-down mounting of a flip chip type, high-density mounting is possible without short-circuiting between connection metal projections. It is to provide a semiconductor element mounting structure.

【0010】[0010]

【課題を解決するための手段】本発明の半導体素子実装
構造は、配線基板上に形成された配線および接続用端子
に対し、半導体素子側の接続用端子上にメタル層と前記
メタル層上に金属突起を設け、異方性導電接着剤あるい
は異方性導電接着フィルムで、前記配線基板の配線およ
び接続用端子を設けた面と前記半導体素子の金属突起を
設けた面とを接着し、同時に接続用端子間の電気的接続
をとるフェイスダウン実装方式で接続された半導体素子
実装構造において、前記隣接する接続用端子の間に絶縁
性物質からなる壁を設けたことを特徴とするものであ
る。
According to the semiconductor device mounting structure of the present invention, a metal layer and a metal layer are formed on a connection terminal on a semiconductor device side with respect to a wiring and a connection terminal formed on a wiring board. A metal projection is provided, and an anisotropic conductive adhesive or an anisotropic conductive adhesive film is used to bond the surface of the wiring substrate on which the wiring and connection terminals are provided and the surface of the semiconductor element on which the metal protrusion is provided, and simultaneously In a semiconductor element mounting structure connected by a face-down mounting method for making electrical connection between connection terminals, a wall made of an insulating material is provided between the adjacent connection terminals. .

【0011】上記本発明の実施の形態において、絶縁性
の壁を設けるのは配線基板側の接続用端子間でもよく、
半導体素子側の接続用端子間であってもよい。
In the above embodiment of the present invention, the insulating wall may be provided between the connection terminals on the wiring board side.
It may be between the connection terminals on the semiconductor element side.

【0012】また、上記本発明の実施の形態において、
絶縁性の壁は、ドライフィルムまたはレジスト等の有機
材料またはSi酸化膜、NSG(Non-doped Silicate G
lass)膜、シリコン窒化膜等の不導体膜が好ましい。
In the above embodiment of the present invention,
The insulating wall is made of an organic material such as a dry film or a resist, or a silicon oxide film, NSG (Non-doped Silicate G).
a non-conductive film such as a glass film or a silicon nitride film.

【0013】本発明の上記構成によれば、半導体素子ま
たは配線基板の接続用端子の間に絶縁性の壁を設けるこ
とにより加熱圧着時のバンプつぶれによる隣接ショート
を防止し、加熱圧着方式でのフェイスダウン実装におけ
る高密度実装を可能にする。
According to the above configuration of the present invention, by providing an insulating wall between the connection terminals of the semiconductor element or the wiring board, it is possible to prevent an adjacent short circuit due to a crushed bump at the time of thermocompression bonding. Enables high-density mounting in face-down mounting.

【0014】[0014]

【発明の実施の形態】以下、本発明の実施形態について
図1を参照して説明する。
An embodiment of the present invention will be described below with reference to FIG.

【0015】図1(A)は、隣接ショート防止用の壁を
設けた配線基板に半導体素子をフリップチップ方式のフ
ェイスダウンで実装した40μmピッチの接続断面図で
ある。
FIG. 1A is a connection sectional view at a pitch of 40 μm in which a semiconductor element is mounted face-down by a flip chip method on a wiring board provided with a wall for preventing adjacent short circuit.

【0016】図1(B)は、図1(A)のフェイスダウ
ンで実装された半導体素子の接続状態を硝子基板上面か
ら硝子を透して見た接続状態図である。
FIG. 1B is a connection state diagram of the semiconductor element mounted face-down in FIG. 1A viewed from above the glass substrate through the glass.

【0017】図1(A)、(B)において、1は隣接シ
ョート防止用の絶縁性物質で形成された壁、2は金メッ
キバンプ、3はAl配線、4は接続用端子(基板側)、
5は硝子配線基板、6は異方性導電接着剤、7は半導体
素子、8はメタル層、9は接続用端子(半導体素子側)
である。
1 (A) and 1 (B), reference numeral 1 denotes a wall formed of an insulating material for preventing adjacent short-circuit, 2 denotes a gold-plated bump, 3 denotes an Al wiring, 4 denotes a connection terminal (substrate side),
5 is a glass wiring board, 6 is an anisotropic conductive adhesive, 7 is a semiconductor element, 8 is a metal layer, 9 is a connection terminal (semiconductor element side).
It is.

【0018】図1(A)、(B)に示した本発明の半導
体素子実装構造とするには、まず硝子配線基板5の接続
用端子4間に絶縁性の壁1を形成する。次いで、半導体
素子7を硝子配線基板5に実装するには、通常のフェイ
スダウン実装方式に従って実装すればよい。すなわち、
接続用端子4を形成した硝子配線基板5の面と、金メッ
キバンプ2を形成した半導体素子7の面を対向して、硝
子配線基板5の所定の接続端子4と半導体素子7の所定
の金メッキバンプ2が接着するように、異方性導電接着
剤6を用いて加熱圧着すればよい。
In order to obtain the semiconductor element mounting structure of the present invention shown in FIGS. 1A and 1B, first, an insulating wall 1 is formed between connection terminals 4 of a glass wiring board 5. Next, in order to mount the semiconductor element 7 on the glass wiring board 5, the semiconductor element 7 may be mounted according to a normal face-down mounting method. That is,
The surface of the glass wiring board 5 on which the connection terminals 4 are formed and the surface of the semiconductor element 7 on which the gold-plated bumps 2 are formed face each other, and the predetermined connection terminals 4 of the glass wiring board 5 and the predetermined gold-plated bumps of the semiconductor element 7 are formed. What is necessary is just to heat-press using the anisotropic conductive adhesive 6 so that 2 may adhere | attach.

【0019】図1(A)、(B)に示すように、加熱圧
着によりつぶされた金メッキバンプ2は、ショート防止
用の絶縁性の壁により隣接する金メッキバンプと接触す
ることがないため、ショートを引き起こさずに、対向す
る配線基板の接続用端子との接続が可能となる。
As shown in FIGS. 1 (A) and 1 (B), the gold-plated bump 2 crushed by heat compression does not come into contact with the adjacent gold-plated bump due to the insulating wall for short-circuit prevention. The connection with the connection terminal of the opposing wiring board can be performed without causing the problem.

【0020】上記実施形態では、配線基板側にショート
防止用の壁を設けた例を示したが、ショート防止用の壁
を、半導体素子側に設けてもよい。また、上記実施形態
では、異方性導電接着剤を用いた例を示したが、異方性
導電接着フィルムを用いてもよい。
In the above embodiment, the example in which the wall for preventing short circuit is provided on the wiring board side is shown, but the wall for preventing short circuit may be provided on the semiconductor element side. Further, in the above embodiment, an example using an anisotropic conductive adhesive is shown, but an anisotropic conductive adhesive film may be used.

【0021】本発明における、ショート防止用の壁の材
質は、絶縁性の物質であれば特に限定されないが、例え
ばドライフィルムまたはレジスト等の有機材料や、Si
酸化膜、NSG膜、シリコン窒化膜等の不導体膜を挙げ
ることができる。
In the present invention, the material of the wall for preventing short circuit is not particularly limited as long as it is an insulating material. For example, an organic material such as a dry film or a resist,
Non-conductive films such as an oxide film, an NSG film, and a silicon nitride film can be given.

【0022】次に配線基板または半導体素子への隣接シ
ョート防止用の壁の形成方法の一実施形態を説明する。
半導体素子または配線基板へのショート防止用壁の形成
方法は同じである。すなわち、配線基板にショート防止
用壁を形成する場合は、配線層を形成し保護膜を形成し
た後に、半導体素子にショート防止用壁を形成する場合
は、プロセス工程が完了した後に、以下の(1)または
(2)の方法により行なえばよい。
Next, an embodiment of a method for forming a wall for preventing a short circuit adjacent to a wiring board or a semiconductor element will be described.
The method of forming the short prevention wall on the semiconductor element or the wiring board is the same. That is, when a short-circuit preventing wall is formed on a wiring board, a wiring layer is formed and a protective film is formed, and when a short-circuit preventing wall is formed on a semiconductor element, after the process step is completed, the following ( It may be performed by the method of 1) or 2).

【0023】(1)配線基板または半導体素子にショー
ト防止用の不導体膜をスパッタまたはCVDにより形成
し、レジスト塗布後パターンニングを行いエッチングを
行うことによりショート防止用の壁を作成する。
(1) A non-conductive film for preventing short circuit is formed on a wiring board or a semiconductor element by sputtering or CVD, followed by patterning after resist coating and etching to form a wall for preventing short circuit.

【0024】(2)ドライフィルムを配線基板または半
導体素子に熱圧着後パターンニングを行う。次に現像を
行った後に加温することにより作成完了となる。なお、
半導体素子の場合はショート防止用壁を作成した後バン
プを形成する。
(2) After the dry film is thermocompression-bonded to a wiring board or a semiconductor element, patterning is performed. Next, development is performed and then heating is performed to complete the preparation. In addition,
In the case of a semiconductor device, a bump is formed after a short prevention wall is formed.

【0025】[0025]

【発明の効果】以上説明したように、接続端子間に接続
端子ショート防止用の絶縁性の壁を設けることにより接
続ピッチの縮小が可能となり高密度で低抵抗の接続が可
能になる。
As described above, by providing insulating walls between the connection terminals for preventing the connection terminals from being short-circuited, the connection pitch can be reduced, and high-density and low-resistance connection can be achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(A)は隣接ショート防止用の壁を設けた40
μmピッチでのフェイスダウン実装方式での実装断面
図、(B)は隣接ショート防止用の壁を設けた40μm
ピッチでのフェイスダウン実装方式での実装状態を硝子
上面から透過した図。
FIG. 1 (A) shows a case where a wall for preventing adjacent short circuit is provided.
Sectional view of mounting in a face-down mounting method at a pitch of μm, (B): 40 μm provided with a wall for preventing adjacent short circuit
FIG. 3 is a view showing a mounting state in a face-down mounting method at a pitch, which is transmitted from the upper surface of the glass.

【図2】(A)は従来のフェイスダウン方式で実装した
40μmピッチでの実装断面図、(B)は従来のフェイ
スダウン方式で実装した40μmピッチでの実装状態を
硝子基板上面から透過した図。
FIG. 2A is a cross-sectional view of mounting at a pitch of 40 μm mounted by a conventional face-down method, and FIG. 2B is a view of the mounting state at a pitch of 40 μm mounted by a conventional face-down method, which is transmitted through the upper surface of a glass substrate. .

【図3】フェイスダウン方式における、接続抵抗と加圧
圧力の関係を示したグラフ。
FIG. 3 is a graph showing a relationship between connection resistance and pressurized pressure in a face-down system.

【符号の説明】[Explanation of symbols]

1 隣接ショート防止用の壁 2 金めっきバンプ 3 Al配線 4 配線基板側接続用端子 5 硝子配線基板 6 異方性導電接着剤 7 半導体素子 8 メタル層 9 半導体素子側接続用端子 DESCRIPTION OF SYMBOLS 1 Wall for prevention of adjacent short-circuit 2 Gold-plated bump 3 Al wiring 4 Wiring board side connection terminal 5 Glass wiring board 6 Anisotropic conductive adhesive 7 Semiconductor element 8 Metal layer 9 Semiconductor element side connection terminal

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 配線基板上に形成された配線および接続
用端子に対し、半導体素子側の接続用端子上にメタル層
と前記メタル層上に金属突起を設け、異方性導電接着剤
あるいは異方性導電接着フィルムで、前記配線基板の配
線および接続用端子を設けた面と前記半導体素子の金属
突起を設けた面とを接着し、同時に接続用端子間の電気
的接続をとるフェイスダウン実装方式で接続された半導
体素子実装構造において、前記隣接する接続用端子の間
に絶縁性物質からなる壁を設けたことを特徴とする半導
体素子実装構造。
1. A semiconductor device comprising a metal layer on a connection terminal on a semiconductor element side and a metal projection on the metal layer. Face-down mounting, in which an isotropic conductive adhesive film is used to bond the surface of the wiring substrate on which the wiring and connection terminals are provided and the surface of the semiconductor element on which the metal projections are provided, and simultaneously establish electrical connection between the connection terminals. In a semiconductor device mounting structure connected in a system, a wall made of an insulating material is provided between the adjacent connection terminals.
【請求項2】 前記壁を配線基板上の接続端子の間に設
けることを特徴とする請求項1に記載の半導体素子実装
構造。
2. The semiconductor element mounting structure according to claim 1, wherein said wall is provided between connection terminals on a wiring board.
【請求項3】 前記壁を半導体素子上の接続端子の間に
設けることを特徴とする請求項1に記載の半導体素子実
装構造。
3. The semiconductor element mounting structure according to claim 1, wherein the wall is provided between connection terminals on the semiconductor element.
【請求項4】 前記壁の材質がドライフィルムまたはレ
ジスト等の有機材料であることを特徴とする請求項1な
いし3のいずれか1項に記載の半導体素子実装構造。
4. The semiconductor device mounting structure according to claim 1, wherein the material of the wall is an organic material such as a dry film or a resist.
【請求項5】 前記壁がSi酸化膜、NSG膜、シリコ
ン窒化膜等の不導体膜であることを特徴とする請求項1
ないし3のいずれか1項に記載の半導体素子実装構造。
5. The device according to claim 1, wherein the wall is a non-conductive film such as a Si oxide film, an NSG film, and a silicon nitride film.
4. The semiconductor element mounting structure according to any one of items 3 to 3.
JP2000175594A 2000-06-12 2000-06-12 Structure for semiconductor element mounting Pending JP2001358171A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000175594A JP2001358171A (en) 2000-06-12 2000-06-12 Structure for semiconductor element mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000175594A JP2001358171A (en) 2000-06-12 2000-06-12 Structure for semiconductor element mounting

Publications (1)

Publication Number Publication Date
JP2001358171A true JP2001358171A (en) 2001-12-26

Family

ID=18677449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000175594A Pending JP2001358171A (en) 2000-06-12 2000-06-12 Structure for semiconductor element mounting

Country Status (1)

Country Link
JP (1) JP2001358171A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059916A (en) * 2005-08-24 2007-03-08 Samsung Electronics Co Ltd Semiconductor chip, its manufacturing method, display panel on which the semiconductor chip is mounted, and its manufacturing method
JP2008277438A (en) * 2007-04-26 2008-11-13 Ricoh Microelectronics Co Ltd Electronic component, substrate, and method of manufacturing electronic component and substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059916A (en) * 2005-08-24 2007-03-08 Samsung Electronics Co Ltd Semiconductor chip, its manufacturing method, display panel on which the semiconductor chip is mounted, and its manufacturing method
JP2008277438A (en) * 2007-04-26 2008-11-13 Ricoh Microelectronics Co Ltd Electronic component, substrate, and method of manufacturing electronic component and substrate

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