JP4201016B2 - Semiconductor module and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent signal delay by directly connecting a laminated semiconductor chip, without using any wire for reducing the conductive path. <P>SOLUTION: The above signal delay can be prevented, and at the same time, packaging area can be reduced by having a substrate for connection, which includes a first projection, on whose top a first electrode for connection is established; and a second projection, which is located outward of installation region of the first projection and, at the same time, formed higher than the first projection and on whose top a second electrode for connection is established, a first semiconductor chip, which is mounted on the first electrode for connection formed on the first projection, and a second semiconductor chip, which is mounted on the second electrode for connection formed on the second projection and makes a laminated form with the first semiconductor chip. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to a semiconductor module and an electronic device, and more particularly, to a semiconductor module and an electronic device that are intended to prevent delay and reduce the size of an electric signal.

  2. Description of the Related Art In recent years, high performance and miniaturization of a semiconductor device have been achieved by arranging a plurality of semiconductor chips in a single package as a multi-chip package in accordance with higher performance and downsizing of electronic devices. . The multi-chip package includes a plurality of semiconductor chips arranged in a plane and a plurality of semiconductor chips stacked in the thickness direction. A multi-chip package in which semiconductor chips are arranged in a plane requires a large mounting area, and therefore contributes little to downsizing of electronic devices. For this reason, development of stacked MCPs in which semiconductor chips are stacked has been actively conducted.

  For example, as described in JP-A-6-37250, a conventional stacked MCP has a terminal portion formed on the periphery of each semiconductor chip when electrically connecting the stacked semiconductor chips to each other. The terminals of the chip are connected by wires. For this reason, the electrical connection between the semiconductor chips becomes complicated, the conduction path becomes longer by the amount of the wire, and there is a possibility that a signal delay occurs.

  The present invention has been made to solve the above-described drawbacks of the prior art, and has an object to directly connect stacked semiconductor chips without using wires and prevent signal delay by shortening a conduction path.

A semiconductor module according to the present invention includes a first protrusion provided with a first connection electrode on the top, and is positioned outside the installation area of the first protrusion and is higher than the first protrusion. A connection substrate based on single crystal silicon having a second protrusion provided with two connection electrodes;
A first semiconductor chip mounted on the first connection electrode formed on the first protrusion, and a second semiconductor mounted on the second connection electrode formed on the second protrusion and stacked with the first semiconductor chip And having a chip. According to the semiconductor module of the seventh aspect, since the second semiconductor chip is mounted so as to cover the first semiconductor chip mounted on the connection substrate, the mounting area can be reduced. In addition, since the first and second semiconductor chips can be mounted on the first and second connection electrodes, it is needless to say that the conduction path is the shortest and signal delay can be minimized.

  The electronic device described in the present invention is characterized by mounting the semiconductor module of the present invention. According to the electronic device of the present invention, since the semiconductor module having the signal transmission path set to the shortest is mounted, the influence of the signal delay can be reduced even in the electronic device. The action can be performed.

As described above, according to the semiconductor module of the present invention, the first protrusion provided with the first connection electrode on the top, the outside of the installation area of the first protrusion, and the first protrusion A connection substrate having a single crystal silicon base material, the second protrusion having a second connection electrode formed on the top of the second protrusion;
A first semiconductor chip mounted on the first connection electrode formed on the first protrusion, and a second semiconductor mounted on the second connection electrode formed on the second protrusion and stacked with the first semiconductor chip In addition to preventing the delay of the signal, the mounting area can be reduced.

  Further, according to the electronic device according to the present invention, since the semiconductor module of the present invention is mounted, the influence of signal delay can be reduced even in the electronic device, and the electronic device can be operated accurately. .

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Preferred embodiments of a semiconductor module and an electronic device according to the invention will be described below in detail with reference to the drawings.

  FIG. 1 is an explanatory view showing the structure of a semiconductor chip according to the present embodiment, and FIG. 1A is a cross-sectional structure view of the semiconductor chip according to the present embodiment. FIG. 2 is an arrow view A in FIG.

  As shown in the figure, the semiconductor chip 10 according to the present embodiment has a single crystal silicon 12 as a base material, and an element such as a MOS transistor, a resistor or a capacitor (not shown) is formed on the surface 14 side. These elements are connected to an electrode 16 formed on the surface 14 via a wiring (not shown). The electrode 16 has a structure in which different kinds of metal materials are laminated as shown in FIG. 1A. In the present embodiment, the lower layer side is tungsten 18 and the upper layer side is aluminum 20. .

  By the way, a vertical hole 24 is formed below the electrode 16 so as to penetrate the single crystal silicon 12 from the back surface 22 side of the single crystal silicon 12, and tungsten 18 forming the electrode 16 is formed at the tip (ceiling) of the vertical hole 24. Is exposed. In such a vertical hole 24, an insulating film 28 is formed on the inclined surface 26 and the back surface 22 of the single crystal silicon 12 that continues to the inclined surface 26, and even if the conductive member contacts the back surface 22, a short circuit occurs between them. Can be prevented from occurring. Further, a metal wiring 30 is routed around the surface of the insulating film 28, and a connection pad (not shown) is formed at the tip of the metal film 30, so that another semiconductor chip 32 can be mounted on the connection pad. Yes.

  That is, in the semiconductor chip 10, the electrode 16 that is electrically connected to the element formed on the surface 14 side and the other semiconductor chip 32 are connected through the metal wiring 30 at the shortest distance. As described above, since the signal path is the shortest, the signal delay can be minimized even when the operation of the semiconductor chip becomes high speed, so that stable operation can be performed.

  Further, by connecting the electrode 16 in the semiconductor chip 10 to another connection substrate (not shown), the signal path between the three of the semiconductor chip 10 and the other semiconductor chip 32 and the connection substrate is shortened. Therefore, stable operation can be secured even in such a semiconductor module.

  2 and 3 are process explanatory views showing the manufacturing process of the semiconductor chip 10 according to the present embodiment. As shown in FIG. 2A, after elements (not shown) are formed on single crystal silicon serving as a base material of the semiconductor chip 10, an electrode 16 that is electrically connected to these elements is formed.

  Note that the electrode 16 has a two-layer structure of tungsten 18 and aluminum 20, and after the tungsten 20 is formed, the aluminum 20 is formed on the upper layer of the tungsten 18.

  For the tungsten 18, first, a Ti film is formed in a thickness of 70 to 200 angstrom by sputtering, and a TiN film is formed thereon in a thickness of 300 to 1000 angstrom by reactive sputtering. Thereafter, plasma CVD using tungsten hexafluoride (WF6) as a main gas is performed, and the surface 14 is covered with tungsten which is a refractory metal. Thereafter, the tungsten is etched back by dry etching using a mixed gas of SF6 and Ar, the excess tungsten is removed, leaving the tungsten only within the range of the electrode 16, and the tungsten 18 which is the lower layer of the electrode 16 is removed. Form. Note that this excess tungsten may be removed by CMP without using etch back.

  After the tungsten 18 is thus formed, the single crystal silicon wafer 12 itself is placed in an argon atmosphere at a pressure of 2 to 5 mTorr and a temperature of 150 to 300 ° C., and Al—Cu, Al—Si—Cu, Al—Si, etc. are targeted. Then, sputtering is performed with an input power of DC 9 to 12 kW, and aluminum 20 having the same composition as these targets may be formed on the upper layer of tungsten 18.

  After the electrode 16 is formed on the surface 14 of the single crystal silicon 12 in this way, as shown in FIG. 2B, anisotropic etching is performed using an etching solution such as a KOH aqueous solution or an ethylenediamine aqueous solution from the back surface 22 side. A vertical hole 24 is formed. The inclined surface 26 of the vertical hole 24 is formed as an inclined surface that forms 54.74 degrees with the back surface 22 (the crystal orientation plane of the back surface 22 is a (100) plane). By setting the opening width on the back surface 22, the vertical holes 24 having a uniform angle can be formed. As the anisotropic etching progresses, the etching solution reaches the electrode 16, but here the electrode 16 has a two-layer structure of tungsten 18 and aluminum 20, and the tungsten 18 is not eroded by the etching solution. Therefore, the vertical hole 24 has a form in which the tungsten 18 constituting the electrode 16 is exposed at the tip (ceiling).

  After the etching is completed, an insulating film (SiO2) 28 may be formed by thermal CVD using tetraethoxysilane (TEOS) from the back side as shown in FIG. Since the insulating film 28 is formed on the back surface 22 of the single crystal silicon 12 in this way, it is possible to prevent a short circuit from occurring even when the conductive member contacts the back surface 22 or the like.

  After that, as shown in FIG. 4 (4), the insulating film 28 on the tungsten 18 may be removed through a photoresist process or the like so that the ceiling in the vertical hole 24, that is, the tungsten 18 is exposed.

  After the formation of the insulating film 28, a metal film 34 may be formed inside the vertical hole 24 as shown in FIG. As a method of forming the metal film 34, the single crystal silicon 12 itself is placed in an argon atmosphere having a pressure of 2 to 5 mTorr and a temperature of 150 to 300 ° C., and Al—Cu, Al—Si—Cu, Al—Si, etc. And a metal film 34 made of aluminum having the same composition as these targets may be formed by sputtering with an input power of DC 9 to 12 kW. After the metal film 34 is formed, as shown in FIG. 2B, the resist 36 is left in a portion corresponding to the metal wiring 30 by a photoresist process, and after the metal wiring 30 is formed, FIG. The resist 36 formed in the upper layer of the metal wiring 30 may be removed as shown in FIG.

  After the metal wiring 30 is thus formed on the back surface 22, another semiconductor chip 32 may be mounted on the connection pad formed at the tip of the metal wiring 30.

  FIG. 4 is an explanatory cross-sectional view showing a first reference embodiment of the semiconductor module according to the present embodiment. As shown in the figure, the semiconductor module 38 includes a connection substrate 40 and semiconductor chips 42 and 44 mounted on the front and back surfaces of the connection substrate 40, respectively. In the semiconductor module 38, the semiconductor chip 42 and the semiconductor chip 44 use the same structure as the semiconductor chip 10 described above, and the semiconductor chip 42 and the semiconductor chip 44 are only different in size. Therefore, the description of the overlapping parts of the structures of the semiconductor chip 42 and the semiconductor chip 44 is omitted.

  Similar to the semiconductor chips 42 and 44, the connection substrate 40 constituting the semiconductor module 38 is based on single crystal silicon 46, and connection electrodes 52 and 54 are formed on the front surface 48 and the back surface 50, Electrical conduction is achieved by the metal wiring 56.

  That is, in the connection substrate 40, as in the semiconductor chips 42 and 44, a vertical hole 58 is formed below the connection electrode 52, and the metal wiring 56 led out from the connection electrode 52 serving as a ceiling portion of the vertical hole 58 is the back surface 50. And is connected to the connection electrode 54.

  For this reason, by mounting the semiconductor chip 42 side on the connection electrode 52 and the semiconductor chip 44 side on the connection electrode 54, the electrical continuity between the semiconductor chip 42 and the semiconductor chip 44 can be reduced. Can be done through. For this reason, the electrical path becomes the shortest, and it is possible to cope with the higher speed of the semiconductor chip by minimizing the delay of signal transmission.

  Even if heat is generated by the operation of the semiconductor chips 42 and 44, the semiconductor chips 42 and 44 and the connection substrate 40 are made of the same material, that is, single crystal silicon, so that the thermal expansion coefficients are equal. For this reason, even if the temperature of the semiconductor module 38 rises, it is possible to prevent stress from being generated between the semiconductor chips 42 and 44 and the connection substrate 40.

  FIG. 5 is a cross-sectional explanatory view showing an assembling procedure of the semiconductor module 38 according to the reference embodiment. As shown in FIG. 1A, after the connection substrate 40 is installed at a predetermined position, the semiconductor chip 42 is lowered from above as shown in FIG. The connection electrode 52 provided on the surface 48 of the connection substrate 40 may be abutted. In this embodiment, an anisotropic conductive adhesive is used for both connections. However, the present invention is not limited to this method, and other methods include thermocompression bonding, solder connection, or ultrasonic connection. You may make it use the method represented by these.

  After mounting the semiconductor chip 42 on the front surface 48 of the connection substrate 40 as shown in FIG. 3C, the semiconductor chip 44 may be mounted on the back surface 50 side of the connection substrate 40. The semiconductor chip 44 may be mounted using a method similar to that for the semiconductor chip 42. In the present embodiment, the mounting procedure has been described so that the semiconductor chip 42 is mounted first, and then the semiconductor chip 44 is mounted. The chip 44 may be mounted on the connection substrate 40 first, or the semiconductor chips 42 and 44 may be mounted on the connection substrate 40 simultaneously.

  FIG. 6 is a main part enlarged view showing a modification of the semiconductor module 38 according to the present embodiment. As shown in FIG. 1A, a bonding wire 64 is used between an electrode 62 provided in advance on another semiconductor chip 60 mounted on the semiconductor chip 42 and a connection electrode 52 provided on the connection substrate 40. If connected, electrical continuity between the other semiconductor chip 60 and the connection substrate 40 can be achieved without the semiconductor chip 42 being interposed. For this reason, in the other semiconductor chip 60, the driving power supply line can be obtained directly from the connection substrate 40, and therefore the degree of freedom of the wiring pattern in the semiconductor chip 42 can be increased. Alternatively, the electrode 62 may be used as a ground (GND) terminal to stabilize the potential, or may be used as an external connection terminal for transmitting and receiving signals.

  As shown in FIG. 2B, when there is no electrode 62 on the upper surface of another semiconductor chip 60, a bonding wire 64 is provided between the surface electrode of the semiconductor chip 42 and the connection electrode 52 of the connection substrate 40. The connection may be made using

  FIG. 7 is an explanatory cross-sectional view showing an assembly procedure of a modified example of the semiconductor module 38 according to the present embodiment. As shown in FIG. 1A, after the connection substrate 40 is installed at a predetermined position, the semiconductor chip 42 is lowered from above as shown in FIG. The connection electrode 52 provided on the surface 48 of the connection substrate 40 is brought into contact with each other. Then, after the connection substrate 40 and the semiconductor chip 42 are connected, the bonding wire 64 may be connected to the electrode 62 and the connection electrode 52 using the bonding tool 66 as shown in FIG. .

  FIG. 8 is a cross-sectional explanatory view showing an embodiment of a semiconductor module of the present invention. As shown in the figure, the semiconductor module 68 has a configuration in which a first semiconductor chip 74 and a second semiconductor chip 76 are stacked on a surface 72 of a connection substrate 70.

  A pair of first protrusions 78 are formed on the surface 72 of the connection substrate 70 based on the single crystal silicon 69, and the height of the pair of first protrusions 78 is higher than the first protrusions 78. A second protrusion 80 having a high height is formed.

  A first connection electrode 82 is formed on the top of the first protrusion 78, and the interval between the first connection electrodes 82 can be matched with the first electrode 84 formed on the first semiconductor chip 74. Is set to

  On the other hand, a second connection electrode 86 is formed on the top of the second protrusion 80, and the distance between the second connection electrodes 86 can be matched with the second electrode 88 formed on the second semiconductor chip 76. It is set so that. The height of the second protrusion is set to a height that exceeds the height when the first semiconductor chip 74 is mounted on the first protrusion 78 (the height including the first semiconductor chip 74). When the second semiconductor chip 76 is mounted on the second protrusion 80, the second semiconductor chip 76 and the first semiconductor chip 74 do not interfere with each other.

  As described above, if the first protrusion 78 and the second protrusion 80 are provided on the surface of the connection substrate 70 and the first semiconductor chip 74 and the second semiconductor chip 76 are mounted on these protrusions, the semiconductor chips can be stacked. Therefore, the mounting area of the connection substrate 70 can be reduced. Needless to say, since the semiconductor chips are stacked, the signal paths of each other are shortened and signal delay can be prevented.

  FIG. 9 and FIG. 10 are process explanatory views showing the manufacturing process of the connection substrate 70 in the semiconductor module 68. As shown in FIG. 9 (1), a resist 90 is applied to a position corresponding to the top range of the second protrusion 80 on the surface 72 of the single crystal silicon 69 having a (100) crystal orientation plane. After the application of the resist 90, anisotropic etching is performed on the surface 72 using an etching solution such as a KOH aqueous solution or an ethylenediamine aqueous solution to form the second protrusions 80. This state is shown in FIG. Then, after forming the second protrusions 80, a resist 92 is again applied to the surface as shown in FIG. 3C, and anisotropic etching is performed using an etching solution such as a KOH aqueous solution or an ethylenediamine aqueous solution. The application range of the resist 92 is the top range of the first protrusion 78 formed between the second protrusion 80 and the pair of second protrusions 80. After the anisotropic etching is completed, that is, the first protrusion 78 is formed. The later state is shown in FIG.

  Then, as shown in FIG. 10A, after removing the resist 92 applied on the surface 72, as shown in FIG. 10B, the first connection electrode 82 and the second connection electrode 86 are formed. . These connection electrodes are composed of single crystal silicon 69 placed in an argon atmosphere having a pressure of 2 to 5 mTorr and a temperature of 150 to 300 ° C., and Al—Cu, Al—Si—Cu, Al—Si, etc. as targets, and DC 9 to Sputtering may be performed with an input power of 12 kW, an aluminum layer having the same composition as these targets may be formed on the surface 72, and then formed using an etching process.

  After forming the first connection electrode 82 and the second connection electrode 86 in this way, the first semiconductor chip 74 is connected to the electrode 84, the first connection electrode 82, and the upper surface 72 as shown in FIG. Implement to match. After the first semiconductor chip 74 is mounted, the second semiconductor chip 76 is mounted so that the electrode 88 and the second connection electrode 86 are abutted. This state is shown in FIG. If the second semiconductor chip 76 is mounted so as to cover the first semiconductor chip 74 in this way, the mounting area on the connection substrate 70 can be reduced.

  Note that in this embodiment mode, the crystal orientation plane on the surface of single crystal silicon has been described as the (100) plane. However, the present invention is not limited to this mode. For example, the crystal orientation plane on the surface of single crystal silicon is (110). ) Surface and the cross section thereof may be rectangular.

  Furthermore, if the semiconductor module described in this embodiment is used for an electronic device, the semiconductor module with the shortest signal path is applied to the electronic device, so that there is less signal delay and operational reliability is improved. Needless to say.

It is explanatory drawing which shows the structure of the semiconductor chip which concerns on this Embodiment. It is process explanatory drawing which shows the manufacturing process of the semiconductor chip 10 which concerns on this Embodiment. It is process explanatory drawing which shows the manufacturing process of the semiconductor chip 10 which concerns on this Embodiment. It is sectional explanatory drawing which shows the 1st reference form of the semiconductor module which concerns on this Embodiment. It is sectional explanatory drawing which showed the assembly procedure of the semiconductor module 38 which concerns on this Embodiment. It is a principal part enlarged view which shows the modification of the semiconductor module 38 which concerns on this Embodiment. It is sectional explanatory drawing which showed the assembly procedure of the modification of the semiconductor module 38 which concerns on this Embodiment. It is a section explanatory view showing an embodiment of a semiconductor module of the present invention. It is process explanatory drawing which shows the manufacture process of the board | substrate 70 for a connection in the semiconductor module 68 of this invention. It is process explanatory drawing which shows the manufacture process of the board | substrate 70 for a connection in the semiconductor module 68 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor chip 12 Single crystal silicon 14 Surface 16 Electrode 18 Tungsten 20 Aluminum 22 Back surface 24 Vertical hole 26 Slope 28 Insulating film 30 Metal wiring 32 Other semiconductor chip 34 Metal film 36 Resist 38 Semiconductor module 40 Connection substrate 42 Semiconductor chip 44 Semiconductor chip 46 single crystal silicon 48 surface 50 back surface 52 connection electrode 54 connection electrode 56 metal wiring 58 vertical hole 60 other semiconductor chip 62 electrode 64 bonding wire 66 bonding tool 68 semiconductor module 69 single crystal silicon 70 connection substrate 72 surface 74 first Semiconductor chip 76 Second semiconductor chip 78 First protrusion 80 Second protrusion 82 First connection electrode 84 First electrode 86 Second connection electrode 88 Second electrode 90 Resist 92 Resist

Claims (2)

A first protrusion provided with a first connection electrode on the top, and located outside the first protrusion installation area and higher than the first protrusion, and a second connection electrode provided on the top. A connection substrate based on single crystal silicon having a second protrusion;
A first semiconductor chip mounted on the first connection electrode formed on the first protrusion, and a second semiconductor mounted on the second connection electrode formed on the second protrusion and stacked with the first semiconductor chip A semiconductor module comprising a chip.   An electronic apparatus comprising the semiconductor module according to claim 1 mounted thereon.

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