JP2002252325A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

Info

Publication number
JP2002252325A
JP2002252325A JP2001047867A JP2001047867A JP2002252325A JP 2002252325 A JP2002252325 A JP 2002252325A JP 2001047867 A JP2001047867 A JP 2001047867A JP 2001047867 A JP2001047867 A JP 2001047867A JP 2002252325 A JP2002252325 A JP 2002252325A
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring board
semiconductor device
wiring
insulating material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001047867A
Other languages
Japanese (ja)
Inventor
Fumito Ito
史人 伊藤
Kenichi Nishiyama
健一 西山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001047867A priority Critical patent/JP2002252325A/en
Publication of JP2002252325A publication Critical patent/JP2002252325A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve the problem of failures, such as burnout due to a metal small-gauge wire for electrically connecting wiring formed on a wiring board to the electrode of a semiconductor device coming into contact with the end section of the semiconductor device, and short-circuiting between the metal small-gauge wires by the flow of the metal small-gauge wires due to the flow of resin in a sealing process occurring in the semiconductor device, where a plurality of semiconductor devices are laminated on a wiring board. SOLUTION: A first insulating material 11 for bonding the wiring board 12 to the first semiconductor device 10 projects to the side section of the first semiconductor device 10, and the metal small-gauge wire 15 for electrically connecting an electrode of the second semiconductor device 13 to wiring of the wiring board 12 is brought into contact with the projection in the first insulating material 11 for fixing, thus preventing the metal small-gauge wire 15 from coming into contact with the end section of the first semiconductor device 10 for disconnection, and preventing the metal small-gauge wires form being mutually short-circuited by the flow of a sealing resin in the sealing process.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、配線基板上に複数
の半導体素子を積層した半導体装置およびその製造方法
に関するものであり、特に、半導体素子の電極と配線基
板の配線とが金属細線によって安定して接続されること
を特徴とする半導体装置およびその製造方法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of semiconductor elements are stacked on a wiring board and a method of manufacturing the same. And a method of manufacturing the same.

【0002】[0002]

【従来の技術】近年、コンピューターや通信機器を中心
とした電子機器の小型化と高機能化に伴って、半導体装
置にも小型化、高密度化および高速化が要求されるよう
になってきた。そのため、複数の半導体素子を配線基板
上に積層した高密度型半導体装置が提案されている。
2. Description of the Related Art In recent years, as electronic devices such as computers and communication devices have become smaller and more sophisticated, semiconductor devices have also been required to be smaller, denser and faster. . Therefore, a high-density semiconductor device in which a plurality of semiconductor elements are stacked on a wiring board has been proposed.

【0003】以下、従来の半導体装置について図面を参
照しながら説明する。
Hereinafter, a conventional semiconductor device will be described with reference to the drawings.

【0004】図6は従来の半導体装置を示した断面図で
ある。
FIG. 6 is a sectional view showing a conventional semiconductor device.

【0005】図6に示すように、第1の半導体素子1の
電極形成面が第1の絶縁性材料2を介して配線基板3と
接着され、第1の半導体素子1の電極に形成されたバン
プと配線基板3の配線とが電気的に接続している。ま
た、第1の半導体素子1の裏面と第2の半導体素子4の
裏面とが第2の絶縁性材料5を介して接着され、第2の
半導体素子4の電極と配線基板3の配線とが金属細線6
によって電気的に接続されている。そして、配線基板3
上で第1の半導体素子1、第2の半導体素子4および金
属細線6が封止樹脂7によって封止されている。なお、
配線基板3の上面に形成された配線と裏面の外部電極と
は配線基板3の内部でスルーホールによって電気的に接
続され、外部電極には半田などを材料とするボール電極
8が形成されている。
As shown in FIG. 6, the electrode forming surface of the first semiconductor element 1 is adhered to the wiring board 3 via the first insulating material 2 and formed on the electrode of the first semiconductor element 1. The bump and the wiring of the wiring board 3 are electrically connected. Further, the back surface of the first semiconductor element 1 and the back surface of the second semiconductor element 4 are bonded via a second insulating material 5 so that the electrode of the second semiconductor element 4 and the wiring of the wiring board 3 are connected. Metal wire 6
Are electrically connected by And the wiring board 3
Above, the first semiconductor element 1, the second semiconductor element 4, and the thin metal wires 6 are sealed with a sealing resin 7. In addition,
The wiring formed on the upper surface of the wiring board 3 and the external electrode on the rear surface are electrically connected through a through hole inside the wiring board 3, and a ball electrode 8 made of a material such as solder is formed on the external electrode. .

【0006】[0006]

【発明が解決しようとする課題】しかしながら従来の半
導体装置では、金属細線の接続に関して以下の課題が発
生する。
However, in the conventional semiconductor device, the following problems occur in connection of the thin metal wires.

【0007】近年の電子機器の多機能化、高機能化にと
もなって半導体素子の大型化が進み、配線基板の面積に
占める半導体素子の面積の割合が拡大し、配線基板上で
配線が形成される領域は配線基板の周囲に限定され、必
然的に、配線基板に接着された第1の半導体素子の端部
の近傍になる。
[0007] With the recent increase in the number of functions and the functions of electronic devices, the size of semiconductor elements has increased, and the ratio of the area of the semiconductor elements to the area of the wiring board has increased, and wiring has been formed on the wiring board. Is limited to the periphery of the wiring board, and is inevitably near the end of the first semiconductor element bonded to the wiring board.

【0008】また、配線基板に接着される第1の半導体
素子の面積が第2の半導体素子の面積よりも大きい形態
の半導体装置が多く見られる。
There are many semiconductor devices in which the area of the first semiconductor element bonded to the wiring substrate is larger than the area of the second semiconductor element.

【0009】このように、配線基板上の配線が形成され
る領域が第1の半導体素子の端部付近となり、かつ、配
線基板に接着された第1の半導体素子の上面に接着され
る第2の半導体素子に対して、第1の半導体素子が大き
い場合、金属細線のループ形状を、第2の半導体素子の
電極から第1の半導体素子端部の上方まではほぼ水平と
し、第1の半導体素子の端部の上方から第1の半導体素
子の側部を通過して配線基板上の配線に降下するまで
は、ほぼ垂直な形状にする必要がある。したがって、金
属細線は第1の半導体素子の端部の上方で、急激に曲が
ったカーブを描くことになる。
As described above, the area where the wiring is formed on the wiring board is near the end of the first semiconductor element and the second semiconductor element is bonded to the upper surface of the first semiconductor element bonded to the wiring substrate. When the first semiconductor element is larger than that of the first semiconductor element, the loop shape of the thin metal wire is made substantially horizontal from the electrode of the second semiconductor element to above the end of the first semiconductor element. The shape needs to be substantially vertical from above the end of the element to passing through the side of the first semiconductor element and descending to the wiring on the wiring board. Therefore, the thin metal wire forms a sharply curved curve above the end of the first semiconductor element.

【0010】このように、金属細線を急激に曲げること
は、ワイヤボンディング装置の高度なループ形成技術の
開発を必要とし、特に、繰り返し精度が要求される量産
現場のワイヤボンディング工程においては課題となる。
したがって、多数の金属細線を全て第1の半導体素子端
部の上方で急激に曲げて、第1の半導体素子の端部に接
触させないことは困難であり、金属細線が第1の半導体
素子の端部に接触して断線等の不具合が発生しやすくな
る。
As described above, rapid bending of a thin metal wire requires the development of an advanced loop forming technique of a wire bonding apparatus, and is a problem particularly in a wire bonding process at a mass production site where repeatability is required. .
Therefore, it is difficult to sharply bend a large number of fine metal wires all over the end of the first semiconductor element so as not to contact the end of the first semiconductor element. In such a case, a trouble such as disconnection is likely to occur due to contact with the part.

【0011】また、第2の半導体素子の面積に対して第
1の半導体素子の面積が大きい場合、第1の半導体素子
の上方における金属細線の長さが長くなるので、封止工
程における封止樹脂の流動によって金属細線が受ける抵
抗が大きくなり、金属細線どうしが接触してショートす
る。
When the area of the first semiconductor element is larger than the area of the second semiconductor element, the length of the thin metal wire above the first semiconductor element becomes longer. The resistance of the thin metal wires increases due to the flow of the resin, and the thin metal wires come into contact with each other to cause a short circuit.

【0012】本発明は、前記従来の課題を解決するもの
であり、金属細線が、配線基板や半導体素子の接着に使
用される絶縁性樹脂に接触して固定されることにより、
金属細線の断線、ショート等の不具合を防止する半導体
装置およびその製造方法を提供するものである。
The present invention has been made to solve the above-mentioned conventional problems, and a thin metal wire is fixed by contacting an insulating resin used for bonding a wiring board or a semiconductor element.
An object of the present invention is to provide a semiconductor device for preventing a problem such as disconnection or short-circuit of a thin metal wire and a method for manufacturing the same.

【0013】[0013]

【課題を解決するための手段】前記従来の課題を解決す
るために、本発明の半導体装置は、配線基板上に複数の
半導体素子が積層して塔載された半導体装置であって、
前記配線基板上に形成された配線と前記半導体素子の電
極とが金属細線により電気的に接続され、前記配線基板
と前記配線基板上に接着された半導体素子との間からは
み出して前記半導体素子の側部に形成された絶縁性材料
に前記金属細線が接触して固定される。
In order to solve the above-mentioned conventional problems, a semiconductor device according to the present invention is a semiconductor device in which a plurality of semiconductor elements are stacked and mounted on a wiring board,
The wiring formed on the wiring board and the electrode of the semiconductor element are electrically connected by a thin metal wire, and protrude from between the wiring board and the semiconductor element bonded on the wiring board to form the semiconductor element. The thin metal wire contacts and is fixed to the insulating material formed on the side part.

【0014】これにより、金属細線が絶縁性材料により
固定されるので、金属細線の断線、ショート等の不具合
を防止することが可能となる。
Thus, since the thin metal wire is fixed by the insulating material, it is possible to prevent problems such as disconnection and short circuit of the thin metal wire.

【0015】また、配線基板上に接着された半導体素子
の電極と前記配線基板上に形成された配線とはバンプを
介して電気的に接続される。
Further, the electrodes of the semiconductor element adhered on the wiring board and the wiring formed on the wiring board are electrically connected via bumps.

【0016】これにより、半導体装置の薄型化を実現
し、配線長を短くできることから高周波デバイスに対応
できる。
As a result, the thickness of the semiconductor device can be reduced, and the wiring length can be reduced.

【0017】また、配線基板上に接着された半導体素子
は、前記半導体素子の裏面が前記配線基板上に接着され
ている。
Further, in the semiconductor element bonded on the wiring substrate, the back surface of the semiconductor element is bonded on the wiring substrate.

【0018】これにより、半導体素子の電極と配線基板
の配線とを金属細線によって電気的に接続できる。
Thus, the electrode of the semiconductor element and the wiring of the wiring board can be electrically connected by the thin metal wire.

【0019】また、配線基板の上面と第1の半導体素子
の電極形成面とが第1の絶縁性材料を介して接着され、
前記配線基板の上面に形成された配線と前記第1の半導
体素子の電極とがバンプを介して電気的に接続され、前
記第1の半導体素子の裏面に前記第1の半導体素子より
も小さい第2の半導体素子の裏面が第2の絶縁性材料を
介して接着され、前記第2の半導体素子の電極と前記配
線基板の配線とが金属細線によって電気的に接続され、
前記第2の絶縁性材料の前記第2の半導体素子の裏面か
らはみ出した部分に前記金属細線が接触して固定されて
いる。
Also, the upper surface of the wiring board and the electrode forming surface of the first semiconductor element are bonded via a first insulating material,
Wiring formed on the upper surface of the wiring substrate and the electrode of the first semiconductor element are electrically connected via bumps, and the first semiconductor element has a smaller surface than the first semiconductor element on the back surface. A back surface of the second semiconductor element is adhered via a second insulating material, and an electrode of the second semiconductor element is electrically connected to a wiring of the wiring board by a thin metal wire;
The thin metal wire is fixed in contact with a portion of the second insulating material protruding from the back surface of the second semiconductor element.

【0020】これにより、金属細線が絶縁性材料に接触
して固定されるので、金属細線の断線、ショート等の不
具合を防止できる。
Thus, the thin metal wire is in contact with and fixed to the insulating material, so that problems such as disconnection and short circuit of the thin metal wire can be prevented.

【0021】また、第2の絶縁性材料の形状および面積
は第1の半導体素子の裏面の形状および面積と同一であ
り、金属細線が前記第2の絶縁性材料の端部に接触して
固定されている。
The shape and area of the second insulating material are the same as the shape and area of the back surface of the first semiconductor element, and the fine metal wire is fixed by contacting the end of the second insulating material. Have been.

【0022】これにより、配線基板に接着された半導体
素子の端部の上部において、金属細線の断線および流動
する封止樹脂による金属細線の流れを防止でき、安定し
た金属細線のループ形成が可能となる。
[0022] With this, it is possible to prevent disconnection of the fine metal wire and flow of the fine metal wire due to the flowing sealing resin above the end of the semiconductor element adhered to the wiring board, and to form a stable loop of the fine metal wire. Become.

【0023】また、第2の絶縁性材料の面積は第1の半
導体素子の面積よりも大きく、金属細線が前記第2の絶
縁性材料の第1の半導体素子の端部からはみ出した部分
に接触して固定されている。
Also, the area of the second insulating material is larger than the area of the first semiconductor element, and the thin metal wire contacts the part of the second insulating material protruding from the end of the first semiconductor element. It is fixed.

【0024】これにより、第2の半導体素子よりも大き
い第2の絶縁性材料に金属細線を接触させて、金属細線
の断線および流動する封止樹脂による金属細線の流れが
防止でき、安定した金属細線のループ形成が可能とな
る。
Thus, the thin metal wire is brought into contact with the second insulating material which is larger than the second semiconductor element, so that the thin metal wire can be prevented from being broken and the thin metal wire can be prevented from flowing due to the flowing sealing resin. A loop of a thin line can be formed.

【0025】また、配線基板上に複数の半導体素子が積
層して塔載された半導体装置であって、前記配線基板上
に形成された配線と前記半導体素子の電極とが電気的に
金属細線により接続され、前記金属細線が前記配線上に
形成された第3の絶縁性材料を通過して固定されてい
る。
Further, in a semiconductor device in which a plurality of semiconductor elements are stacked and mounted on a wiring board, a wiring formed on the wiring board and an electrode of the semiconductor element are electrically connected by a thin metal wire. Connected, and the thin metal wire is fixed by passing through a third insulating material formed on the wiring.

【0026】これにより、配線基板と半導体素子との間
からはみ出す封止樹脂の量が不足しても、第3の絶縁性
材料により金属細線を半導体素子の端部に接触させるこ
となく、半導体素子の周囲で曲げて配線基板の配線部と
電気的に接続させるとともに固定することができる。
Thus, even if the amount of the sealing resin protruding from between the wiring board and the semiconductor element is insufficient, the third insulating material does not allow the thin metal wire to contact the end of the semiconductor element. Can be bent around and electrically connected to the wiring portion of the wiring board and fixed.

【0027】また、配線基板上に形成された配線と前記
配線基板内部のスルーホールによって電気的に接続さ
れ、前記配線基板の裏面に形成された外部電極にボール
電極が形成されている。
The wiring formed on the wiring board is electrically connected to the wiring through a through hole inside the wiring board, and a ball electrode is formed on an external electrode formed on the back surface of the wiring board.

【0028】これにより、配線基板を外部のマザーボー
ドに塔載し、電気的に接続することが可能となる。
Thus, the wiring board can be mounted on the external motherboard and electrically connected.

【0029】また、配線基板の上面に複数の半導体素子
を積層して塔載する工程と、前記半導体素子の電極と配
線基板の上面に形成された配線とを金属細線で電気的に
接続する工程とからなる半導体装置の製造方法であっ
て、前記半導体素子の電極と前記配線基板の上面に形成
された配線とを金属細線で電気的に接続する工程では、
前記配線基板の上面と前記半導体素子とを接着する第1
の絶縁性材料の前記半導体素子の側部にはみ出した部分
または前記複数の半導体素子どうしを接着する第2の絶
縁性材料の前記複数の半導体素子どうしの接着面からは
み出した部分に前記金属細線を接触させて固定する。
A step of laminating and mounting a plurality of semiconductor elements on the upper surface of the wiring board, and a step of electrically connecting electrodes of the semiconductor elements to wirings formed on the upper surface of the wiring board with thin metal wires. In the step of electrically connecting the electrode of the semiconductor element and the wiring formed on the upper surface of the wiring substrate with a thin metal wire,
A first adhesive bonding the upper surface of the wiring substrate to the semiconductor element;
The thin metal wire is applied to a portion of the insulating material protruding from the side of the semiconductor element or to a portion of the second insulating material that protrudes from the bonding surface of the plurality of semiconductor elements to bond the plurality of semiconductor elements together. Contact and fix.

【0030】このような半導体装置の製造方法によっ
て、金属細線が半導体素子端部に接触して断線したり、
封止樹脂の流動による金属細線どうしのショート等の不
具合を防止できる。
According to such a method of manufacturing a semiconductor device, a thin metal wire may be broken by contacting an edge of a semiconductor element.
Problems such as short-circuiting between thin metal wires due to the flow of the sealing resin can be prevented.

【0031】[0031]

【発明の実施の形態】以下、本発明の半導体装置および
その製造方法の一実施形態について図面を参照しながら
説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings.

【0032】最初に、本実施形態の第1の実施形態につ
いて説明する。
First, a first embodiment of the present embodiment will be described.

【0033】まず、本実施形態の半導体装置の製造方法
について説明する。
First, a method for manufacturing the semiconductor device of the present embodiment will be described.

【0034】図1および図2は、本実施形態の半導体装
置の製造方法の各製造工程を示す断面図である。
FIG. 1 and FIG. 2 are cross-sectional views showing respective manufacturing steps of the method of manufacturing a semiconductor device according to the present embodiment.

【0035】図1(a)に示すように、バンプ9が形成
された第1の半導体素子10を、シート状の第1の絶縁
性材料11が設置された配線基板12と対向させ、配線
基板12の配線(図示せず)と第1の半導体素子10の
電極に形成されたバンプ9とを位置合わせして電気的に
接続するとともに、第1の絶縁性材料11により第1の
半導体素子10と配線基板12の上面とを接着する。こ
の際、第1の絶縁性材料11は第1の半導体素子10と
配線基板12に挟まれて、第1の半導体素子10の側部
にはみ出す。本実施形態では、第1の絶縁性材料11は
エポキシ系の熱硬化性の絶縁性材料を用いている。
As shown in FIG. 1A, the first semiconductor element 10 on which the bumps 9 are formed is opposed to a wiring board 12 on which a sheet-like first insulating material 11 is provided. The wiring (not shown) 12 and the bumps 9 formed on the electrodes of the first semiconductor element 10 are aligned and electrically connected, and the first insulating element 11 is used for the first semiconductor element 10. And the upper surface of the wiring board 12 are bonded. At this time, the first insulating material 11 is sandwiched between the first semiconductor element 10 and the wiring board 12 and protrudes to the side of the first semiconductor element 10. In the present embodiment, the first insulating material 11 uses an epoxy-based thermosetting insulating material.

【0036】ここで、図1(b)に示すように、第1の
半導体素子10の裏面に第2の半導体素子13の裏面を
エポキシ系の樹脂からなる第2の絶縁性材料14を用い
て接着する。
Here, as shown in FIG. 1B, the back surface of the second semiconductor element 13 is formed on the back surface of the first semiconductor element 10 by using a second insulating material 14 made of epoxy resin. Glue.

【0037】次に、図1(c)に示すように、第2の半
導体素子13の電極と配線基板12上に形成された配線
とを金属細線15で電気的に接続するが、本実施形態で
は、金属細線15を第1の絶縁性材料11の第1の半導
体素子10の側部にはみ出した部分に接触させて固定し
ていることが特徴的構成となっている。
Next, as shown in FIG. 1C, the electrodes of the second semiconductor element 13 and the wiring formed on the wiring board 12 are electrically connected by the thin metal wires 15 in this embodiment. Is characterized in that the thin metal wire 15 is fixed in contact with the portion of the first insulating material 11 protruding from the side of the first semiconductor element 10.

【0038】次に、金属細線15のループ形成の方法に
ついて詳細に説明する。
Next, a method of forming a loop of the thin metal wire 15 will be described in detail.

【0039】まず、第2の半導体素子13の電極に金属
細線15の一端を接合させた後、キャピラリにより第1
の半導体素子10の上面にほぼ平行に金属細線15を誘
導する。そして、金属細線15を第1の半導体素子10
の端部の上方付近で曲げて下降させ、他端を配線基板1
2上の配線に接合させる。この際、金属細線15は、第
1の半導体素子10の側部にはみ出した第1の絶縁性材
料11の上部に接触して固定されるので、第1の半導体
素子10の端部に接触せず、金属細線15の断線を防止
できる。
First, one end of the thin metal wire 15 is joined to the electrode of the second semiconductor element 13, and then the first wire is connected by a capillary.
The thin metal wire 15 is guided substantially parallel to the upper surface of the semiconductor element 10. Then, the thin metal wire 15 is connected to the first semiconductor element 10.
Is bent down near the upper end of the wiring board, and the other end is
2 to the upper wiring. At this time, the thin metal wire 15 is fixed in contact with the upper portion of the first insulating material 11 protruding to the side of the first semiconductor element 10. Therefore, the disconnection of the thin metal wire 15 can be prevented.

【0040】次に、図2(a)に示すように、配線基板
12の上面の第1の半導体素子10、第2の半導体素子
13および金属細線15をエポキシ系の熱硬化性の封止
樹脂16を用いて封止する。
Next, as shown in FIG. 2A, the first semiconductor element 10, the second semiconductor element 13 and the fine metal wires 15 on the upper surface of the wiring board 12 are sealed with an epoxy-based thermosetting sealing resin. 16 and sealing is performed.

【0041】次に、図2(b)に示すように、配線基板
12の裏面の外部電極にハンダ等からなるボール電極1
7を塔載し、リフロ工程を経てハンダを溶融、硬化させ
る。なお、配線基板12の表面の配線と配線基板12の
裏面の外部電極とは、配線基板12の内部のスルーホー
ルによって電気的に接続されている。
Next, as shown in FIG. 2B, the ball electrode 1 made of solder or the like is
7 is mounted, and the solder is melted and cured through a reflow process. Note that the wiring on the front surface of the wiring board 12 and the external electrodes on the back surface of the wiring board 12 are electrically connected by through holes inside the wiring board 12.

【0042】以上、本実施形態の半導体装置の製造方法
は、第2の半導体素子の電極と配線基板の配線とを電気
的に接続する金属細線を、第1の半導体素子の側部には
み出した第1の樹脂に接触させて固定することにより、
金属細線が第1の半導体素子の端部に接触して断線する
ことを防止でき、また、封止工程における封止樹脂の流
動によって金属細線が流されることがないので金属細線
どうしのショートを防止できる。
As described above, in the method of manufacturing a semiconductor device according to the present embodiment, the thin metal wire for electrically connecting the electrode of the second semiconductor element and the wiring of the wiring board protrudes to the side of the first semiconductor element. By contacting and fixing the first resin,
The thin metal wire can be prevented from breaking due to contact with the end of the first semiconductor element, and a short circuit between the thin metal wires can be prevented because the thin metal wire does not flow due to the flow of the sealing resin in the sealing step. it can.

【0043】また、金属細線の高度なループ形成技術を
要することもないので、量産現場のワイヤボンディング
工程における歩留まり低下を防止することも可能であ
る。
Further, since there is no need for an advanced technique for forming a loop of a thin metal wire, it is possible to prevent a reduction in yield in a wire bonding process at a mass production site.

【0044】なお、本実施形態の半導体装置の製造方法
は、2個の半導体素子を積層した場合であるが、3個以
上の半導体素子を積層した場合にも、金属細線が配線基
板と半導体素子との間からはみ出した絶縁性材料に接触
して固定されることにより、金属細線の断線、ショート
等の不具合を防止できる。
The method of manufacturing a semiconductor device according to the present embodiment is a case in which two semiconductor elements are stacked. However, even when three or more semiconductor elements are stacked, a thin metal wire is By contacting and fixing the insulating material protruding from the space between them, it is possible to prevent problems such as disconnection and short-circuit of the thin metal wires.

【0045】次に、以上の半導体装置の製造方法によっ
て製造された本実施形態の半導体装置の実施形態につい
て図面を用いて説明する。なお、前記の本実施形態の半
導体装置の製造方法と同一の構成要件には同一の符号を
付す。
Next, an embodiment of the semiconductor device of the present embodiment manufactured by the above-described method for manufacturing a semiconductor device will be described with reference to the drawings. The same components as those in the method of manufacturing a semiconductor device according to the present embodiment are denoted by the same reference numerals.

【0046】図2(b)に示すように、ガラスエポキシ
絶縁性材料からなる配線基板12の上面と第1の半導体
素子10の電極形成面とが第1の絶縁性材料11を介し
て接着され、配線基板12の上面に形成された配線と第
1の半導体素子10の電極に形成されたバンプ9とが電
気的に接続されている。第1の絶縁性材料11は第1の
半導体素子10と配線基板12との間からはみ出し、第
1の半導体素子10の側部にも形成されている。そし
て、第1の半導体素子10の裏面と第1の半導体素子1
0よりも小さい第2の半導体素子13の裏面とが第2の
絶縁性材料14によって接着され、第2の半導体素子1
3の電極と配線基板12の配線とが金属細線15によっ
て電気的に接続されている。この金属細線15は、第1
の半導体素子10の側部にはみ出した第1の絶縁性材料
11に接触して固定されている。そして、第1の半導体
素子10、第2の半導体素子13および金属細線15は
配線基板12の上面においてエポキシ系の熱硬化性の封
止樹脂16によって封止されている。
As shown in FIG. 2B, the upper surface of the wiring board 12 made of a glass epoxy insulating material and the electrode forming surface of the first semiconductor element 10 are bonded via the first insulating material 11. In addition, the wiring formed on the upper surface of the wiring board 12 and the bump 9 formed on the electrode of the first semiconductor element 10 are electrically connected. The first insulating material 11 protrudes from between the first semiconductor element 10 and the wiring board 12 and is also formed on the side of the first semiconductor element 10. Then, the back surface of the first semiconductor element 10 and the first semiconductor element 1
The lower surface of the second semiconductor element 13 smaller than 0 is adhered to the second semiconductor element 13 by the second insulating material 14.
The third electrode and the wiring of the wiring board 12 are electrically connected by the thin metal wire 15. This thin metal wire 15 is
And is fixed in contact with the first insulating material 11 protruding from the side of the semiconductor element 10. The first semiconductor element 10, the second semiconductor element 13, and the thin metal wires 15 are sealed on the upper surface of the wiring board 12 with an epoxy-based thermosetting sealing resin 16.

【0047】なお、本実施形態では配線基板の配線と第
1の半導体素子の電極とがバンプによって電気的に接続
されているが、配線基板上に第1の半導体素子の裏面が
第1の絶縁性材料により接着され、第1の半導体素子の
電極形成面に第2の半導体素子の裏面が第2の絶縁性材
料により接着され、第1の半導体素子の電極、第2の半
導体素子の電極と配線基板の配線とが金属細線で電気的
に接続され、配線基板と第1の半導体素子との間からは
み出した第1の絶縁性材料に金属細線が接触して固定さ
れた場合でも同様に、金属細線の断線、ショート等の不
具合を防止できるものである。
In the present embodiment, the wiring of the wiring board and the electrode of the first semiconductor element are electrically connected by bumps, but the back surface of the first semiconductor element is provided on the wiring board with the first insulation. The back surface of the second semiconductor element is bonded to the electrode forming surface of the first semiconductor element with the second insulating material, and the electrode of the first semiconductor element and the electrode of the second semiconductor element are bonded together. Similarly, even when the wiring of the wiring board is electrically connected by a thin metal wire and the thin metal wire is in contact with and fixed to the first insulating material protruding from between the wiring board and the first semiconductor element, Problems such as disconnection and short-circuit of the thin metal wire can be prevented.

【0048】以上、本実施形態の半導体装置は、第2の
半導体素子の電極と配線基板の配線とを電気的に接続し
た金属細線が第1の半導体素子の側部にはみ出した第1
の絶縁性材料に接触して固定されることを特徴としてお
り、金属細線が半導体素子の端部に接触して断線するこ
との防止、金属細線の高さバラツキの防止および封止工
程における封止樹脂の流動で金属細線が流されて金属細
線どうしがショートすることの防止が可能となる。さら
に、高度な金属細線のループ形成技術が不要であるの
で、量産現場のワイヤボンディング工程における歩留ま
りの低下を防止することができる。
As described above, in the semiconductor device of this embodiment, the first thin metal wire electrically connecting the electrode of the second semiconductor element and the wiring of the wiring board protrudes to the side of the first semiconductor element.
To prevent the thin metal wire from being broken by contacting the end of the semiconductor element, preventing the height variation of the thin metal wire, and sealing in the sealing step. It is possible to prevent the metal thin wires from flowing due to the flow of the resin and short-circuiting between the metal thin wires. Further, since a sophisticated technique for forming a loop of a fine metal wire is unnecessary, it is possible to prevent a decrease in yield in a wire bonding process at a mass production site.

【0049】次に、第2の実施形態について図面を参照
しながら説明する。なお、第1の実施形態と同一の構成
要件については同一の符号を付し、共通の内容は省略す
る。
Next, a second embodiment will be described with reference to the drawings. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and common contents are omitted.

【0050】図3および図4は本実施形態の半導体装置
を示す断面図である。
FIGS. 3 and 4 are sectional views showing the semiconductor device of the present embodiment.

【0051】図3に示すように、配線基板12の上面と
第1の半導体素子10の電極形成面とが第1の絶縁性材
料11を介して接着され、第1の半導体素子10の電極
に形成されたバンプ9と配線基板12の配線とが電気的
に接続されている。また、第1の半導体素子10の裏面
に設置されたシート状のエポキシ系の絶縁性材料からな
る第2の絶縁性材料14の上面に第2の半導体素子13
の裏面が接着され、第2の半導体素子13の電極と配線
基板12の配線とが金属細線15によって電気的に接続
されている。そして、本実施形態の特徴的構成として、
金属細線15は、第1の半導体素子10の裏面の形状お
よび面積と同一の形状および面積の第2の絶縁性材料1
4の端部に接触して固定されている。
As shown in FIG. 3, the upper surface of the wiring board 12 and the electrode forming surface of the first semiconductor element 10 are bonded via a first insulating material 11, and the electrodes of the first semiconductor element 10 are The formed bumps 9 and the wiring of the wiring board 12 are electrically connected. Further, the second semiconductor element 13 is provided on the upper surface of a second insulating material 14 made of a sheet-like epoxy-based insulating material provided on the back surface of the first semiconductor element 10.
Are bonded, and the electrodes of the second semiconductor element 13 and the wiring of the wiring board 12 are electrically connected by the thin metal wires 15. And, as a characteristic configuration of the present embodiment,
The thin metal wire 15 is formed of the second insulating material 1 having the same shape and area as the shape and area of the back surface of the first semiconductor element 10.
4 and is fixed in contact therewith.

【0052】また、図4に示すように、シート状の第2
の絶縁性材料14が第1の半導体素子10の裏面の端部
からはみ出し、その第2の絶縁性材料14の第1の半導
体素子10の裏面からはみ出した部分に金属細線15が
接触して固定されてもよい。第2の絶縁性材料14のは
み出し量は、第1の半導体素子10の端部から配線基板
12の配線までの距離よりも小さい範囲ならば特に限定
されるものではない。
Further, as shown in FIG.
The insulating material 14 protrudes from the end of the back surface of the first semiconductor element 10, and the thin metal wire 15 contacts and is fixed to the part of the second insulating material 14 protruding from the back surface of the first semiconductor element 10. May be done. The amount of protrusion of the second insulating material 14 is not particularly limited as long as it is within a range smaller than the distance from the end of the first semiconductor element 10 to the wiring of the wiring board 12.

【0053】以上、本実施形態の半導体装置は、半導体
素子どうしを接着する第2の絶縁性材料の端部または第
1の半導体素子の裏面からはみ出した部分に金属細線が
接触して固定されているので、金属細線が第1の半導体
素子の端部に直接接触して断線することなく、また、封
止工程における封止樹脂注入時の抵抗によって金属細線
が流されて金属細線どうしがショートすることがないの
で、第2の半導体素子の電極と配線基板の配線との安定
した電気的接続を確保できる。
As described above, in the semiconductor device of the present embodiment, the thin metal wire is fixed in contact with the end of the second insulating material for bonding the semiconductor elements or the portion protruding from the back surface of the first semiconductor element. Therefore, the thin metal wires do not break by directly contacting the ends of the first semiconductor element, and the thin metal wires flow due to the resistance at the time of injection of the sealing resin in the sealing step, and the metal thin wires are short-circuited to each other. Therefore, stable electrical connection between the electrode of the second semiconductor element and the wiring of the wiring board can be ensured.

【0054】次に、第3の実施形態について図面を参照
しながら説明する。なお、第1の実施形態および第2の
実施形態と同一の構成要件については同一の符号を付
し、共通の内容は省略する。
Next, a third embodiment will be described with reference to the drawings. Note that the same components as those in the first embodiment and the second embodiment are denoted by the same reference numerals, and common contents are omitted.

【0055】図5は本実施形態の半導体装置を示す断面
図である。
FIG. 5 is a sectional view showing the semiconductor device of this embodiment.

【0056】図5に示すように、配線基板12上の配線
に形成された第3の絶縁性材料18に金属細線15が通
過することによって金属細線15が固定されている。こ
のように、金属細線15が第3の絶縁性材料18によっ
て固定されることにより金属細線15の断線を防止し、
封止工程における封止樹脂16の流動による金属細線1
5どうしのショートを防止することが可能となる。
As shown in FIG. 5, the fine metal wire 15 is fixed by passing the fine metal wire 15 through the third insulating material 18 formed on the wiring on the wiring board 12. In this manner, the thin metal wire 15 is fixed by the third insulating material 18, thereby preventing the thin metal wire 15 from breaking.
Fine metal wire 1 due to flow of sealing resin 16 in the sealing step
It is possible to prevent a short circuit between the five.

【0057】以上、本実施形態の半導体装置は配線基板
の配線上に形成された絶縁性材料に金属細線が通過して
固定されることにより、金属細線の断線、ショート等の
不具合を防止できる。
As described above, in the semiconductor device according to the present embodiment, since the fine metal wire passes through and is fixed to the insulating material formed on the wiring of the wiring board, problems such as disconnection and short circuit of the fine metal wire can be prevented.

【0058】[0058]

【発明の効果】本発明の半導体装置およびその製造方法
により、第2の半導体素子と配線基板の配線とを電気的
に接続する金属細線が、第1の半導体素子の電極形成面
と配線基板との間からはみ出した絶縁性材料または半導
体素子どうしを接着する絶縁性材料に接触して固定され
ることにより、金属細線の断線やショートを防止でき
る。
According to the semiconductor device and the method of manufacturing the same of the present invention, a thin metal wire for electrically connecting the second semiconductor element and the wiring of the wiring board is formed on the electrode forming surface of the first semiconductor element and the wiring board. Breaking or short-circuiting of the thin metal wire can be prevented by being fixed by contacting the insulating material protruding from the space or the insulating material for bonding the semiconductor elements together.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態の半導体装置の製造方法を
示す断面図
FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention;

【図2】本発明の一実施形態の半導体装置およびその製
造方法を示す断面図
FIG. 2 is a sectional view showing a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention;

【図3】本発明の一実施形態の半導体装置を示す断面図FIG. 3 is a sectional view showing a semiconductor device according to one embodiment of the present invention;

【図4】本発明の一実施形態の半導体装置を示す断面図FIG. 4 is a sectional view showing a semiconductor device according to one embodiment of the present invention;

【図5】本発明の一実施形態の半導体装置を示す断面図FIG. 5 is a sectional view showing a semiconductor device according to one embodiment of the present invention;

【図6】従来の半導体装置を示す断面図FIG. 6 is a sectional view showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 第1の半導体素子 2 第1の絶縁性材料 3 配線基板 4 第2の半導体素子 5 第2の絶縁性材料 6 金属細線 7 封止樹脂 8 ボール電極 9 バンプ 10 第1の半導体素子 11 第1の絶縁性材料 12 配線基板 13 第2の半導体素子 14 第2の絶縁性材料 15 金属細線 16 封止樹脂 17 ボール電極 18 第3の絶縁性材料 DESCRIPTION OF SYMBOLS 1 1st semiconductor element 2 1st insulating material 3 wiring board 4 2nd semiconductor element 5 2nd insulating material 6 Thin metal wire 7 Sealing resin 8 Ball electrode 9 Bump 10 1st semiconductor element 11 1st Insulating material 12 Wiring board 13 Second semiconductor element 14 Second insulating material 15 Metal wire 16 Sealing resin 17 Ball electrode 18 Third insulating material

フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 23/31 Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (reference) H01L 23/31

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 配線基板上に複数の半導体素子が積層し
て塔載された半導体装置であって、前記配線基板上に形
成された配線と前記半導体素子の電極とが金属細線によ
り電気的に接続され、前記配線基板と前記配線基板上に
接着された半導体素子との間からはみ出して前記半導体
素子の側部に形成された絶縁性材料に前記金属細線が接
触して固定されていることを特徴とする半導体装置。
1. A semiconductor device in which a plurality of semiconductor elements are stacked and mounted on a wiring board, wherein a wiring formed on the wiring board and an electrode of the semiconductor element are electrically connected by a thin metal wire. The thin metal wire is connected to and fixed to the insulating material formed on the side of the semiconductor element by protruding from between the wiring board and the semiconductor element bonded on the wiring board. Characteristic semiconductor device.
【請求項2】 配線基板上に接着された半導体素子の電
極と前記配線基板上に形成された配線とはバンプを介し
て電気的に接続されていることを特徴とする請求項1に
記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the electrodes of the semiconductor element bonded on the wiring board and the wiring formed on the wiring board are electrically connected via bumps. Semiconductor device.
【請求項3】 配線基板上に接着された半導体素子は、
前記半導体素子の裏面が前記配線基板上に接着されてい
ることを特徴とする請求項1に記載の半導体装置。
3. The semiconductor device bonded on the wiring board,
2. The semiconductor device according to claim 1, wherein a back surface of the semiconductor element is adhered on the wiring board.
【請求項4】 配線基板の上面と第1の半導体素子の電
極形成面とが第1の絶縁性材料を介して接着され、前記
配線基板の上面に形成された配線と前記第1の半導体素
子の電極とがバンプを介して電気的に接続され、前記第
1の半導体素子の裏面に前記第1の半導体素子よりも小
さい第2の半導体素子の裏面が第2の絶縁性材料を介し
て接着され、前記第2の半導体素子の電極と前記配線基
板の配線とが金属細線によって電気的に接続され、前記
第2の絶縁性材料の前記第2の半導体素子の裏面からは
み出した部分に前記金属細線が接触して固定されている
ことを特徴とする半導体装置。
4. An upper surface of a wiring board and an electrode formation surface of a first semiconductor element are adhered via a first insulating material, and a wiring formed on an upper surface of the wiring board and the first semiconductor element are bonded. Are electrically connected via bumps, and the back surface of a second semiconductor element smaller than the first semiconductor element is bonded to the back surface of the first semiconductor element via a second insulating material. The electrode of the second semiconductor element is electrically connected to the wiring of the wiring board by a thin metal wire, and the metal of the second insulating material protrudes from the back surface of the second semiconductor element. A semiconductor device, wherein thin wires are fixed in contact with each other.
【請求項5】 第2の絶縁性材料の形状および面積は第
1の半導体素子の裏面の形状および面積と同一であり、
金属細線が前記第2の絶縁性材料の端部に接触して固定
されていることを特徴とする請求項4に記載の半導体装
置。
5. The shape and area of the second insulating material are the same as the shape and area of the back surface of the first semiconductor element.
5. The semiconductor device according to claim 4, wherein a thin metal wire is fixed in contact with an end of said second insulating material.
【請求項6】 第2の絶縁性材料の面積は第1の半導体
素子の裏面の面積よりも大きく、金属細線が前記第2の
絶縁性材料の前記第1の半導体素子の裏面の端部からは
み出した部分に接触して固定されていることを特徴とす
る請求項4に記載の半導体装置。
6. The area of the second insulating material is larger than the area of the back surface of the first semiconductor element, and a thin metal wire is formed from the end of the back surface of the first semiconductor element of the second insulating material. The semiconductor device according to claim 4, wherein the semiconductor device is fixed in contact with the protruding portion.
【請求項7】 配線基板上に複数の半導体素子が積層し
て塔載された半導体装置であって、前記配線基板上に形
成された配線と前記半導体素子の電極とが電気的に金属
細線により接続され、前記金属細線が前記配線上に形成
された第3の絶縁性材料を通過して固定されていること
を特徴とする半導体装置。
7. A semiconductor device in which a plurality of semiconductor elements are stacked and mounted on a wiring board, wherein a wiring formed on the wiring board and an electrode of the semiconductor element are electrically connected by a thin metal wire. A semiconductor device, wherein the thin metal wire is connected and fixed through a third insulating material formed on the wiring.
【請求項8】 配線基板上に形成された配線と前記配線
基板内部のスルーホールによって電気的に接続され、前
記配線基板の裏面に形成された外部電極にボール電極が
形成されていることを特徴とする請求項1または請求項
4または請求項7に記載の半導体装置。
8. A wiring formed on the wiring board and electrically connected to each other by a through hole inside the wiring board, wherein a ball electrode is formed on an external electrode formed on a back surface of the wiring board. The semiconductor device according to claim 1 or claim 4 or claim 7.
【請求項9】 配線基板の上面に複数の半導体素子を積
層して塔載する工程と、前記半導体素子の電極と配線基
板の上面に形成された配線とを金属細線で電気的に接続
する工程とからなる半導体装置の製造方法であって、前
記半導体素子の電極と前記配線基板の上面に形成された
配線とを金属細線で電気的に接続する工程では、前記配
線基板の上面と前記半導体素子とを接着する第1の絶縁
性材料の前記半導体素子の側部にはみ出した部分または
前記複数の半導体素子どうしを接着する第2の絶縁性材
料の前記複数の半導体素子どうしの接着面からはみ出し
た部分に前記金属細線を接触させて固定することを特徴
とする半導体装置の製造方法。
9. A step of laminating and mounting a plurality of semiconductor elements on an upper surface of a wiring substrate, and a step of electrically connecting electrodes of the semiconductor elements to wirings formed on the upper surface of the wiring substrate by thin metal wires. Wherein in the step of electrically connecting an electrode of the semiconductor element and a wiring formed on an upper surface of the wiring board with a thin metal wire, the upper surface of the wiring board and the semiconductor element are formed. And a portion of the first insulating material that sticks out to the side of the semiconductor element or a part of the second insulating material that sticks the plurality of semiconductor elements together and sticks out from the bonding surface of the plurality of semiconductor elements. A method for manufacturing a semiconductor device, comprising: contacting and fixing the thin metal wire to a portion.
JP2001047867A 2001-02-23 2001-02-23 Semiconductor device and its manufacturing method Pending JP2002252325A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001047867A JP2002252325A (en) 2001-02-23 2001-02-23 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001047867A JP2002252325A (en) 2001-02-23 2001-02-23 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2002252325A true JP2002252325A (en) 2002-09-06

Family

ID=18909216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001047867A Pending JP2002252325A (en) 2001-02-23 2001-02-23 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2002252325A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008004650A (en) * 2006-06-21 2008-01-10 Hitachi Ulsi Systems Co Ltd Semiconductor, and its manufacturing method
JP4931908B2 (en) * 2006-03-14 2012-05-16 シャープ株式会社 Circuit board, electronic circuit device, and display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4931908B2 (en) * 2006-03-14 2012-05-16 シャープ株式会社 Circuit board, electronic circuit device, and display device
JP2008004650A (en) * 2006-06-21 2008-01-10 Hitachi Ulsi Systems Co Ltd Semiconductor, and its manufacturing method

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