JP2001357672A5 - - Google Patents
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- Publication number
- JP2001357672A5 JP2001357672A5 JP2000178105A JP2000178105A JP2001357672A5 JP 2001357672 A5 JP2001357672 A5 JP 2001357672A5 JP 2000178105 A JP2000178105 A JP 2000178105A JP 2000178105 A JP2000178105 A JP 2000178105A JP 2001357672 A5 JP2001357672 A5 JP 2001357672A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000178105A JP4717983B2 (ja) | 2000-06-14 | 2000-06-14 | 省消費電力型メモリモジュール及び計算機システム |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000178105A JP4717983B2 (ja) | 2000-06-14 | 2000-06-14 | 省消費電力型メモリモジュール及び計算機システム |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001357672A JP2001357672A (ja) | 2001-12-26 |
| JP2001357672A5 true JP2001357672A5 (enExample) | 2007-07-26 |
| JP4717983B2 JP4717983B2 (ja) | 2011-07-06 |
Family
ID=18679592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000178105A Expired - Fee Related JP4717983B2 (ja) | 2000-06-14 | 2000-06-14 | 省消費電力型メモリモジュール及び計算機システム |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4717983B2 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4410676B2 (ja) * | 2002-07-01 | 2010-02-03 | 株式会社日立製作所 | 方向性結合式バスシステム |
| JP5486812B2 (ja) * | 2009-01-09 | 2014-05-07 | 株式会社メガチップス | メモリ制御回路 |
| JP5668559B2 (ja) * | 2011-03-22 | 2015-02-12 | 日本電気株式会社 | 情報処理装置、その制御方法およびプログラム |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51128234A (en) * | 1975-04-30 | 1976-11-09 | Toshiba Corp | Mos-type semi-conductor memory |
| JPS56156985A (en) * | 1980-02-04 | 1981-12-03 | Texas Instruments Inc | Decoder |
| JPS5891591A (ja) * | 1981-11-27 | 1983-05-31 | Toshiba Corp | 半導体メモリのパワ−セ−ブ方式 |
| JPS61105795A (ja) * | 1984-10-29 | 1986-05-23 | Nec Corp | メモリ回路 |
| JPH01201890A (ja) * | 1988-02-05 | 1989-08-14 | Fujitsu Ltd | リード・オンリ・メモリ制御回路 |
| JPH0377158A (ja) * | 1989-08-18 | 1991-04-02 | Mitsubishi Electric Corp | マイクロプロセッサ |
| JP3189875B2 (ja) * | 1997-06-04 | 2001-07-16 | 日本電気株式会社 | ステートマシン |
| JPH1186526A (ja) * | 1997-09-12 | 1999-03-30 | Nec Eng Ltd | メモリ制御装置 |
| JP2000195287A (ja) * | 1998-12-28 | 2000-07-14 | Hitachi Ltd | シフトレジスタ及びシリアル／パラレル変換回路並びに通信用ｌｓｉ |
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2000
- 2000-06-14 JP JP2000178105A patent/JP4717983B2/ja not_active Expired - Fee Related