JP2001353334A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a judging process of an input signal from a detecting means provided on a game machine more efficient. SOLUTION: A CPU inputs data which is input in an input port 0 wherein a detected output of a switch is input. Then, '8' is set as a processing number, and the address of a switch timer for a first switch is set on a pointer. Then, a switch check process subsidiary routine is called. The processing number corresponds with the number of switches which are judgement objectives. In the switch check process subsidiary routine, a summing up process of the switch timers which are prepared in a manner to correspond with respective switches is performed. Since 8 and 4 are set as the processing numbers, when there are 12 switch inputs, the judgement process for all the switches is performed by one switch process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine, a coin game machine, a slot machine, etc., in which a game is played in accordance with a player's operation. A gaming machine in which a game is played in accordance with a game machine.

[0002]

2. Description of the Related Art As an example of a gaming machine, when a game medium such as a game ball is fired into a game area by a launching device, and a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of game media are played. Some prize balls and other values are paid out to players.

[0003] Further, the gaming machine is provided with a variable display device having a variable display section whose display state can be changed, and when the display result of the variable display section becomes a predetermined specific display mode, the player can change the display state. Is configured to shift to a jackpot game state which is advantageous to the game. The variable display device includes a plurality of variable display units, and is generally configured to display the display results of the plurality of variable display units at different times. On the variable display section, for example, a plurality of identification information such as symbols are variably displayed. The fact that the display result of the variable display unit is a combination of predetermined specific display modes is usually referred to as “big hit”. In addition, the game value is a right to make the state of the variable prize ball device provided in the game area of the gaming machine advantageous for a player who is easy to win a hit ball, or a right for the player to be in an advantageous state. Or to generate.

[0004] When a big hit occurs, for example, a big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state where a hit ball is easy to win. Then, in each open period, when a predetermined number (for example, 10) of winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. Further, if a predetermined condition (for example, winning in a V zone provided in the special winning opening) is not satisfied at the time when the special winning opening is closed, the big hit game is performed even if the predetermined number of times is not reached. The state ends.

[0005] In addition, among the combinations of the display modes of "outside" other than the combination of "big hit", at a stage where some of the display results of the plurality of variable display portions have not been derived and displayed yet, the display results are already displayed. The state in which the display mode of the variable display unit that is derived and displayed satisfies the display condition that is a combination of the specific display modes is referred to as “reach”. A player plays a game while enjoying how to generate a big hit.

As described above, the gaming machine is provided with a detecting means such as a switch for detecting that the game medium has won the prize area. In order to quickly pay out a value based on a prize, it is necessary to quickly detect that the prize has been won. Therefore, it is preferable to provide a detection means for each prize area. Further, in order to effectively perform a game effect using the variable display unit or the like, a detection unit such as a switch for detecting establishment of an effect start condition may be provided.
Furthermore, since the payout based on the winning is generally performed by the payout mechanism, a detection means such as a switch for detecting whether or not the payout is surely made from the payout mechanism is also required. In addition, various kinds of switches and other detection means are provided in the gaming machine so that the game by the player can be continued without any trouble.

[0007]

As described above, a game machine is provided with a large number of detecting means, but the progress of the game is generally controlled by a game control microcomputer. It is necessary to transmit to the game control microcomputer via the input port.

As described above, since a large number of detecting means are provided in the gaming machine, it is necessary for the game control microcomputer to perform input determination processing for the large number of detecting means. Then, if the input determination processing is not configured to be executed efficiently, the program capacity required for the input determination processing increases, or the time required for the input determination processing increases and the time required for the game effect processing is increased. The problem arises that the length is shortened.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gaming machine capable of efficiently performing a process of determining an input signal from a detecting means provided in the gaming machine.

[0010]

A gaming machine according to the present invention comprises:
A gaming machine in which a player can play a predetermined game, an electronic component control means for controlling an electrical component provided in the gaming machine, and a plurality of each providing a detection signal to the electrical component control means. Wherein the electrical component control means has an input determination module for determining the state of the detection signal from the detection means, and executes the input determination module once to determine the state of the plurality of detection signals. Is performed.

[0011] Measuring means capable of measuring the ON period of the detection signal from the detecting means is provided for each detecting means, and the input judging module updates the value of each measuring means corresponding to the plurality of detecting means. May be included.

[0012] A detecting means may be provided corresponding to each of all winning ports provided in the game area.

[0013] The plurality of detecting means may include detecting means for detecting whether or not the payout of the game medium is possible.

The processing for controlling the electric components provided in the gaming machine may be performed when the value of the measuring means reaches a predetermined judgment value.

[0015] The electric component control means may include an input judgment value table in which a predetermined judgment value is set.

[0016] The predetermined judgment value may be set to a different value depending on the type of the detecting means.

[0017] The determination result of the input determination module may be stored in storage means capable of storing the stored content even when the power supply to the gaming machine is stopped.

[0018]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as viewed from the front. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1 comprises:
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing game balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section (special symbol display device) 9 for variably displaying a plurality of types of symbols and an ordinary symbol display (ordinary symbol display device) 10 using 7-segment LEDs are provided. A variable display device 8 is provided. In the variable display section 9, for example, "left", "middle",
There are three symbol display areas of "right". Variable display device 8
Is provided with a passage gate 11 for guiding a hit ball. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. The winning ball that has entered the starting winning port 14 is guided to the back of the game board 6 and detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

Below the variable winning ball device 15, there is provided an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state). In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that has entered one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by a V count switch (specific area switch) 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. At the lower portion of the variable display device 8, a starting winning storage display 18 having four display sections for displaying the number of winning balls entering the starting winning port 14 is provided. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. And
Each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and the winning of the game balls into the respective winning ports 19 and 24 is determined by setting the corresponding winning port switches 19a and 19a.
19b, 24a and 24b. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. On the outer periphery of the game area 7, a game effect LED 2
8a and gaming effect lamps 28b and 28c are provided.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a premium ball is paid out, and a ball out lamp 52 which is lit up when the supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and that allows a ball to be lent by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is in a usable state. If there is a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the number displayed on the symbol display 10 normally changes. When a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17,
If the change of the symbol can be started, the symbol in the variable display section 9 starts rotating. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols accompanied by a probability change, the probability of the next big hit increases. That is, a high probability state, which is more advantageous for the player, is obtained. When the stop symbol on the ordinary symbol display 10 is a predetermined symbol (hit symbol = small hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the ordinary symbol display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, each board disposed on the back surface of the pachinko gaming machine 1 will be described. As shown in FIG. 2, on the back surface of the pachinko gaming machine 1, a ball storage tank 38 is provided above the mechanism plate in the frame 2A, and above the pachinko gaming machine 1 installed on the gaming machine installation island. The game ball is supplied to the ball storage tank 38 from. The game balls in the ball storage tank 38 pass through a guiding gutter 39 to reach a ball dispensing device covered with a prize ball case 40A.

On the rear side of the gaming machine, a variable display control unit 29 for controlling the variable display section 9 and a game control board (main board) 31 on which a game control microcomputer and the like are mounted are installed. A payout control board 37 on which a payout control microcomputer or the like for performing ball payout control is mounted;
And a hit ball launching device that launches a hit ball into the game area 7 using the rotational force of a motor. Furthermore, the decoration lamp 25, the game effect LED 28a, the game effect lamp 28
b, 28c, a lamp control board 35 for sending signals to the prize ball lamp 51 and the ball out lamp 52, a voice control board 70 for controlling the generation of voice from the speaker 27, and a launch control for controlling the hit ball launching device. A substrate 91 is also provided.

Further, DC30V, DC21V, DC1
A power supply board 910 on which a power supply circuit for generating 2V and 5V DC is mounted is provided, and a terminal board 1 provided with terminals for outputting various information to the outside of the gaming machine is provided above.
60 are installed. The terminal board 160 has at least an out-of-ball terminal for introducing and outputting the output of the out-of-ball detection switch, an award ball terminal for externally outputting the award ball number signal, and an externally outputting ball lending number signal. A ball lending terminal is provided. In the vicinity of the center, an information terminal board 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is provided. In FIG. 2, signals from the lamp control board 35 and the sound control board 70 are supplied to the game effect LEDs 28a, game effect lamps 28b and 28c, the prize ball lamp 51, and the ball cut lamp 52 provided on the frame side. Although the electric relay board A77 for performing the above is shown, other relay boards are provided as necessary for signal relay.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as viewed from the rear. As shown in FIG. 3, on the back surface of the gaming board 6, there is provided a winning ball set cover 40 for guiding a winning ball that has won each winning port and a winning ball device along a predetermined winning route. Of the winning balls guided to the winning ball collection cover 40, those winning through the opening / closing plate 20 are controlled so that the ball payout device 97 pays out a relatively large number of prize balls (for example, 15). The winnings through the starting winning opening 14 are controlled so that the ball payout device (not shown in FIG. 3) pays out a relatively small number of prize balls (for example, 6). Then, the winning prize through the other prize port 24 and the winning ball device is controlled so that the ball payout device pays out a relatively medium number of prize balls (for example, 10).
Note that FIG. 3 illustrates the relay board 33 as an example.

To perform the prize ball payout control, a winning opening switch 19a, 19b, 24a, 24b, a starting opening switch 1
7, count switch 23 and V count switch 2
2 are sent to the main board 31. When the starting port switch 17 is turned on, for example, "6" is output as the winning ball number signal for the payout control board, and when the count switch 23 is turned on, "15" is output as the winning ball number signal, for example. Then, the winning opening switches 19a, 19b, 24a,
When 24b is turned on, for example, "10" is output as the prize ball number signal. Since a detection switch is provided for each winning opening, winning detection is quickly performed, and as a result, prize payout according to the winning is quickly performed.

FIG. 4 is a block diagram showing an example of the circuit configuration of the main board 31. FIG. 4 also shows the payout control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the symbol control board 80.
On the main board 31, the pachinko machine 1
, A gate switch 12, a starting port switch 17, a V count switch 22, a count switch 23, winning port switches 19a, 19b, 24a,
24b, the full tank switch 48, the ball out switch 187, and the switch circuit 58 that supplies signals from the prize ball count switch 301A to the basic circuit 53, and the variable prize ball device 1
A solenoid 16 that opens and closes the opening 5, a solenoid 21 that opens and closes the opening and closing plate 20, and a solenoid circuit 59 that drives a switching solenoid 21 A for switching a path in the special winning opening in accordance with a command from the basic circuit 53 are mounted.

Although not shown in FIG. 4, the count switch short-circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58. In addition, the ball out switch 187 is
It is installed at a position where a shortage of game balls supplied to the ball payout device can be detected.

According to the data supplied from the basic circuit 53, jackpot information indicating occurrence of a jackpot, effective start information indicating the number of start winning balls used to start image display of the variable display section 9, and probability fluctuation have occurred. An information output circuit 64 for outputting an information output signal such as probability change information indicating the fact to an external device such as a hall computer is mounted.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as an example of a storage means used as a work memory, a CPU 56 for performing a control operation according to the program, and an I / O port unit 5.
7 inclusive. In this embodiment, the ROM 54 and the RAM 5
5 is built in the CPU 56. That is, the CPU 5
Reference numeral 6 denotes a one-chip microcomputer. In addition, 1
The chip microcomputer has at least the RAM 55
And the ROM 54 and the I / O port unit 57 may be external or internal.

Further, the main board 31 is provided with a system reset circuit 65 for resetting the basic circuit 53 when the power is turned on. Note that there is also switch information input from the ball dispensing device 97 to the main board 31, but these are omitted in FIG.

A hit ball launching device that hits and fires a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 is used to display the start memory display 18, the gate passage memory display 41 and the decorative lamp 25 provided on the game board. Controls the game and the game effect lamp / LED 28 provided on the frame side.
a, 28b, and 28c, display control of the award ball lamp 51, and the ball out lamp 52 are performed. The display control of the variable display unit 9 for variably displaying special symbols and the ordinary symbol display 10 for variably displaying ordinary symbols is performed by display control means mounted on the symbol control board 80.

FIG. 5 is a block diagram showing an example of the configuration of the power supply board 910. The power supply board 910 includes a main board 31, a symbol control board 80, a voice control board 70, and a lamp control board 3.
5 and a payout control board 37, etc., which are installed independently of the electric component control boards (boards on which the electric component control means for controlling the electric components provided in the game machine are mounted), and each of the electric component control boards in the game machine and Generates voltages used by mechanical components. In this example, AC24V, VSL (DC + 30
V), generate + 21V DC, + 12V DC and + 5V DC. A capacitor 9 serving as a backup power supply
16 is charged from DC + 5V, that is, a power supply line for driving an IC or the like on each substrate.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 21V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
5 is connected to, for example, a relay board, from which electric power of a voltage required for each electric component control board and mechanism components is supplied.

However, the power supply board 910 may be provided with each connector leading to each electric component control board, and the power supply board 910 may supply each voltage reaching each board without passing through the relay board. FIG. 5 shows one connector 9.
Although 15 is shown as a representative, a connector is provided for each electric component control board.

+ 5V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is provided with an electric power so as to be able to hold a storage state in a backup RAM (power-backed-up RAM, that is, storage means that can be in a storage state) when the power supply to the gaming machine is cut off. Backup power supply. Also,
A diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

Note that a battery that can be charged from a +5 V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

The power supply board 910 includes a power supply monitoring I
C902 is mounted. The power supply monitoring IC 902
The occurrence of power interruption is detected by introducing the VSL power supply voltage and monitoring the VSL power supply voltage. Specifically, when the VSL power supply voltage falls below a predetermined value (+22 V in this example),
It outputs a voltage drop signal (power-off signal) assuming that power-off occurs. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is the voltage immediately after conversion from AC to DC,
Is used. The voltage drop signal from the power supply monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect the power-off is lower than the normal voltage, but is a voltage that allows the CPU on each electric component control board to operate for a while. Further, the power supply monitoring IC 902 is configured to monitor a voltage higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and a voltage immediately after conversion from AC to DC. Therefore, the monitoring range can be extended for the voltage required by the CPU. Therefore,
More precise monitoring can be performed. Furthermore, when VSL (+30 V) is used as the monitoring voltage, since the voltage supplied to the various switches of the gaming machine is +12 V, prevention of erroneous switch-on detection upon momentary power interruption can be expected. That is, when monitoring the voltage of the + 30V power supply,
The drop can be detected at a stage before + 12V generated after the generation of 0V starts to fall.

Therefore, when the voltage of the +12 V power supply drops, the switch output comes to an on state,
If the power supply interruption is recognized by monitoring the +30 V power supply voltage that falls earlier than V, the power supply wait state can be entered before the switch output turns on, and the switch output can not be detected.

Further, since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the power supply monitoring circuit can supply a power-off signal to the plurality of electric component control boards. No matter how many electrical component control boards need a power-off signal, it is sufficient that only one power supply monitoring means is provided. Therefore, even if each electrical component control means in each electrical component control board performs return control described later, However, the cost of gaming machines does not increase much.

In the configuration shown in FIG. 5, the detection output (power cutoff signal) of the power supply monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control signal) via the buffer circuits 918 and 919. Although transmitted to the board 37), for example, a configuration in which one detection output is transmitted to the relay board, and the same signal is distributed from the relay board to each electric component control board may be employed. Further, a buffer circuit may be provided according to the number of substrates that require a power-off signal.

FIG. 6 is a block diagram showing an example of a configuration around the CPU 56 on the main board 31. As shown in FIG. As shown in FIG. 6, a power supply cutoff signal (voltage drop signal) from a power supply monitoring circuit (power supply monitoring means) of the power supply board 910 is connected to a non-maskable interrupt terminal (XNMI terminal) of the CPU 56. The power supply monitoring circuit is a circuit that monitors a voltage of any one of various DC power supplies used by the gaming machine and detects a power supply voltage drop. In this embodiment, the power supply voltage of VSL is monitored, and when the voltage value becomes equal to or lower than a predetermined value, a low-level power-off signal is generated. VSL is the largest DC voltage used in gaming machines, and is +30 V in this example. Therefore, the CPU 56 can confirm the occurrence of power interruption by the interrupt processing.

FIG. 6 also shows a system reset circuit 65. The reset IC 651 sets the output to a low level for a predetermined time determined by the capacity of an external capacitor when the power is turned on, and sets the output to a high level after a predetermined time has elapsed. That is, the reset signal is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors the power supply voltage VSL, which is the same power supply voltage as the power supply voltage monitored by the power supply monitoring circuit, and determines that the voltage value is a predetermined value (lower than the power supply voltage value at which the power supply monitoring circuit outputs a power-off signal) Value), the output goes low.
Therefore, the CPU 56 performs a predetermined power supply stop processing in response to a power-off signal from the power supply monitoring circuit, and then performs a system reset.

As shown in FIG. 6, the reset signal from the reset IC 651 is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. Counter I
When the input to the clear terminal goes low, the C941 counts the clock signal from the oscillator 943.
The Q5 output of the counter IC 941 is output to the NOT circuit 9
45, 946 and input to the NAND circuit 947. The Q6 output of the counter IC 941 is input to a clock terminal of a flip-flop (FF) 942.
The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The other input of the OR circuit 949 is connected to the NAND circuit 9.
The output of 47 is introduced via NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration, two reset signals (low-level signals) are supplied to the reset terminal of the CPU 56 when the power is turned on.
Starts operation reliably.

For example, the detection voltage of the power supply monitoring circuit (the voltage at which the power supply cutoff signal is output) is set to +22 V, and the detection voltage for setting the reset signal to low level is set to +9 V. In such a configuration, the power supply monitoring circuit and the system reset circuit 65 are connected to the same power supply VSL.
, The difference between the timing at which the voltage monitoring circuit outputs the power-off signal and the timing at which the system reset circuit 65 outputs the system reset signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop processing in response to the power supply cutoff signal from the power supply monitoring circuit until the power supply stop processing is completely completed.

While power is not supplied from the + 5V power supply which is the driving power supply of the CPU 56 and the like, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board, and the contents are maintained even if the power supply to the gaming machine is cut off. Is saved. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to the normal operation state. At that time, since the necessary data is stored in the backup RAM, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

In the configuration shown in FIG. 6, two reset signals (low-level signals) are supplied to the reset terminal of the CPU 56 when the power is turned on. However, even if the reset signal rises only once, the reset is reliably performed. When the CPU to be released is used, the circuit elements indicated by reference numerals 941 to 949 are unnecessary. In that case, reset I
The output of C651 is directly connected to the reset terminal of CPU56.

CPU 56 used in this embodiment
Incorporates an I / O port (PIO) and a timer / counter circuit (CTC). PIO is PB0-PB
It has a port of 3 4 bits and 1 byte of PA0 to PA7. The ports PB0 to PB3 and PA0 to PA7 can be set for both input and output. However, in this embodiment, no built-in PIO is used. In that case, for example, all ports are set to the input mode, and all ports are connected to the ground level. When power is turned on, P
IO is automatically set to input mode.

Next, the operation of the gaming machine will be described. FIG.
9 is a flowchart showing a main process executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56 first performs necessary initial settings.

In the initial setting process, the CPU 56 first sets interrupt prohibition (step S1a). When the interrupt is set to be prohibited, the CPU 56 sets the interrupt mode to the interrupt mode 2 (step S1b), and sets the stack pointer designated address to the stack pointer (step S1).
c). Then, the CPU 56 initializes the built-in device register (step S1d). After initializing a built-in device (built-in peripheral circuit) CTC (counter / timer) and PIO (parallel input / output port) (step S1e), the RAM is set to an accessible state (step S1f).

CPU 5 used in this embodiment
6 has the following three types of modes as maskable interrupt (INT) modes. When an interrupt that can be masked occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter on the stack.

Interrupt mode 0: The built-in device that has issued the interrupt request receives an RST instruction (1 byte) or a CALL instruction (3 bytes).
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. Upon reset, CPU 56 automatically switches to interrupt mode 0
become. Therefore, when it is desired to set the mode to the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the mode to the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
In this mode, the camera always jumps to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is an interrupt address. Mode. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary (albeit skipped) even address. Each built-in device has a function of sending an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to set an interrupt process at an arbitrary position in a program. Will be possible. Further, unlike the interrupt mode 1, it is easy to prepare an interrupt process for each interrupt occurrence factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S1b of the initial setting process.

Then, it is checked whether or not the data protection processing of the backup RAM area (for example, the power failure occurrence NMI processing such as the addition of parity data) has been performed when the power is turned off (step S2). In this embodiment, when an unexpected power failure occurs, a process for protecting data in the backup RAM area is performed. The case where such protection processing has been performed is regarded as backup. After confirming that there is no backup, the CPU 56 executes an initialization process (steps S2 and S3).

When the backup is confirmed, the CPU 5
6 performs a game state restoring process for returning the internal state to the state when the power is turned off (step S6). Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the program returns to that address.

Execution of normal initialization processing (step S3)
Is completed, the process shifts to a loop process in which the monitoring of the timer interrupt flag (step S9) is confirmed in the main process. In the loop, a display random number update process (step S8) is also performed.

FIG. 8 shows a normal initialization process (step S
It is a flowchart which shows the process of 3). As shown in FIG. 8, in the initialization process, the RAM is cleared (step S3a). Then, based on the address value of the work area initial setting table, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a payout command storage pointer, etc.) is initialized. An initial value setting process for setting a value (step S3b) is performed. Then, the register of the CTC provided in the CPU 56 is set so that the timer is interrupted periodically every 2 ms (step S3).
c). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interrupt is prohibited (see FIG. 7) in step S1a of the initial setting process, the interrupt is permitted before the initialization process is completed (step S3d).

Therefore, in this embodiment, the CPU 56
Is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2 ms
Is set to Then, as shown in FIG. 9, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S12).

When detecting that the timer interrupt flag has been set in step S9, the CPU 56 resets the timer interrupt flag (step S1).
0), a game control process is executed (step S11). According to the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process.
The game control process may be executed by a timer interrupt process.

As described above, in this embodiment, the interrupt mode 2 is set in the CPU 56 having a built-in CTC or PIO in the initial setting process. Accordingly, a periodic timer interrupt process using the built-in CTC can be easily realized. Further, the timer interrupt processing can be set at an arbitrary position on the program. Further, switch detection processing using the built-in PIO can be easily realized by interruption processing. As a result, effects such as simplification of the program configuration and reduction in the number of program development steps can be obtained.

Further, in this embodiment, it is determined whether or not the power is restored to the state at the time of power failure based on the presence or absence of backup data. Therefore, when the power is turned on, for example, when the power is restored after a power failure, it is possible to determine whether or not to restore the state at the time of the power failure according to the contents of the backup data storage area.

Further, it is determined whether or not the power is restored to the power-off state according to the state of the backup data. Therefore, when the power is turned on when the power is restored after a power failure, the contents of the backup data storage area are restored. It is possible to determine whether to restore the power-off state according to the state.

FIG. 10 shows a step S in the main processing.
It is a flowchart which shows the game control process of No. 11. In the game control process, the CPU 56 firstly controls the gate sensor 12, the starting port sensor 17,
Count sensor 23 and winning opening switches 19a, 19
The switch states such as b, 24a, and 24b are input, and their states are determined (switch processing: step S2).
1).

Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

Next, a process of updating each counter indicating each random number for determination such as a random number for big hit determination used in game control is performed (step S23). The CPU 56 further includes:
A process for updating a display random number such as a random number for determining the type of stop symbol is performed (step S24).

Further, the CPU 56 performs a special symbol process (step S25). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Also, a normal symbol process is performed (step S26). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

The CPU 56 sets a control command to be sent to each electric component board in a predetermined area of the RAM 55 and performs a process of sending the control command (command control process: step S27).

Next, the CPU 56 performs an information output process of outputting data such as jackpot information, start information, and probability variation information supplied to the hall management computer (step S29).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 in response to the drive command, and brings the variable winning ball device 15 or the open / close plate 20 into an open state or a closed state.

The CPU 56 has switches 17, 23, 19a, 19b, and 19 for detecting winning in each winning opening.
The number of prize balls is set based on the detection outputs of 24a and 24b (step S31). Specifically, a payout control command is output to the payout control board 37 in response to the winning detection.
The payout control CPU 3 mounted on the payout control board 37
71 drives the ball payout device 97 in response to the payout control command.

As described above, the main processing includes the processing for determining whether or not to shift to the game control processing.
Since a flag is set to determine whether or not to shift to the game control process in the timer interrupt process based on the timer interrupt that is periodically generated by the 56 internal timers, all the game control processes are reliably executed. Is done. In other words, until all of the game control processes have been executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process will be completed. ing.

Here, the CPU 56 of the main board 31
Is executed in response to a flag set in a timer interrupt process based on a timer interrupt that is periodically generated by an internal timer of the CPU 56, but the signal is periodically (for example, every 2 ms). A hardware circuit which generates the signal may be provided, a signal from the circuit may be introduced to an external interrupt terminal of the CPU 56, and a flag for determining whether or not to shift to the game control process based on the interrupt signal may be set. Good.

Even in such a configuration, the flag is not determined until all the game control processes are executed, so that it is guaranteed that all processes in the game control process are completed. You.

FIG. 11 is an explanatory diagram showing each random number. Each random number is used as follows. (1) Random 1: Determine whether or not to generate a big hit (for big hit determination = for special symbol determination) (2) Random 2-1 to 2-3: For left and right middle missing symbol determination (3) Random 3: Determine the combination of symbols at the time of the big hit (for big hit symbol determination = for special symbol judgment)

Incidentally, random numbers other than the above-mentioned random numbers (1) to (3) are used to enhance the game effect. In step S23, the CPU 56 counts up (adds 1) a counter for generating the jackpot determination random number (1) and the jackpot symbol determination random number (3).
That is, these are the random numbers for determination, and the other random numbers are the random numbers for display.

FIG. 12 is a flow chart showing an example of a special symbol processing program executed by the CPU 56. The special symbol processing shown in FIG.
Is a specific process of step S25 in the flowchart of FIG. When performing the special symbol process process, the CPU 56 performs a variation reduction timer subtraction process (step S310), and then performs steps S300 to S300 according to the internal state.
309 is performed. The fluctuation shortening timer is a timer for setting the fluctuation time when the fluctuation time of the special symbol is shortened.

Special symbol change waiting process (step S30)
0): The start winning port 14 (in this embodiment, the winning port of the variable winning ball device 15) is hit and the start port sensor 17 is turned on. When the starting port sensor 17 is turned on, the starting winning memory number is increased by + if the starting winning memory number is not full.
1 and a random number for jackpot determination is extracted.

Special symbol determination processing (step S301):
When the state in which the variable display of the special symbol can be started, the number of start winning prize stored is confirmed. If the starting prize memory number is not 0,
It is determined whether to make a big hit or an out according to the value of the extracted big hit determining random number.

Stop symbol setting processing (step S302):
The stop symbol of the left and right middle symbols is determined.

Reach operation setting processing (step S30)
3): A pattern variation pattern is determined based on a variation pattern determining random number (not shown in FIG. 11).

All symbols change start processing (step S30)
4): In the variable display section 9, control is performed so that all symbols start to change. At this time, with respect to the symbol control board 80,
The left and right middle final stop symbols and information instructing the variation mode are transmitted. When processing is completed, the internal state (process flag)
Is updated to shift to step S305.

All symbols stop wait processing (step S30)
5): When a predetermined time (time indicated by the fluctuation shortening timer in step S310) elapses, control is performed so that all the symbols displayed on the variable display unit 9 are stopped. And
If the stop symbol is a combination of big hit symbols, the internal state (process flag) is updated so as to shift to step S306. If not, the internal state is updated to shift to step S300.

Opening process of opening the special winning opening (step S30)
6): Control for opening the special winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening. Also, a big hit flag (a flag indicating that a big hit is being made) is set. Upon completion of the process, the internal state (process flag) is updated so as to shift to step S307.

Processing during opening of the special winning opening (step S30)
7): Control for sending display control command data for the special winning opening round display to the symbol control board 80, processing for confirming establishment of the closing condition of the special winning opening, and the like are performed. When the final closing condition of the special winning opening is satisfied, the internal state is updated to shift to step S308.

Specific area effective time processing (step S30)
8): The presence or absence of passage of the V count switch 22 is monitored, and a process of confirming that the big hit game state continuation condition is satisfied is performed. If the condition of the jackpot game state continuation is satisfied and there is still a remaining round, the internal state is changed to step S30.
Update to move to 6. If the big hit game state continuation condition is not satisfied within the predetermined effective time, or if all rounds have been completed, the internal state is updated to shift to step S309.

Big hit end processing (step S309): A display for notifying the player that the big hit gaming state has ended is performed. When the display is completed, the internal state is updated so as to shift to step S300.

FIG. 13 is a flowchart showing a process for determining whether or not to make a big hit. This processing corresponds to the processing executed in steps S301 and S302 in the special symbol process processing.

When the CPU 56 is ready to start the variable display of symbols, the CPU 56 checks the value of the number of stored winning prizes as shown in FIG. 13 (step S51). If the start winning storage number is not 0, each random value stored in the buffer area corresponding to the starting winning storage number = 1 is read out (step S52), the value of the starting winning storage number is reduced by 1, and The value of the buffer area is shifted (Step S53). That is, the number of start winning prize memories = n (n =
The value stored in the buffer area corresponding to (2, 3, 4) is stored in the buffer area corresponding to the number of stored start winnings = n-1.

Then, the CPU 56 determines a hit / miss based on the value read in step S52, specifically, the value of the extracted random number for jackpot determination (step S54). Here, the big hit determination random numbers are 0 to 29
A value in the range of 9 will be taken. As shown in FIG.
At the time of low probability, for example, if the value is “3”, it is determined as “big hit”, and if the value is any other value, “out”.
Is determined. When the probability is high, for example, the value is "3",
If it is one of "7", "79", "103", and "107", it is determined as "big hit", and if it is any other value, it is determined as "out".

When it is determined that the big hit is a big hit, a big hit symbol determining random number (random 3) is extracted, and the big hit symbol is determined according to the value (step S55). The big hit symbol is a combination of symbols in which the left and right middle symbols are the same.
If it is determined that the pattern is out of position, the left and right out-of-position symbols are determined. In this embodiment, the left symbol is determined according to the value of the random 2-1 (step S56), and the random symbol is determined.
The middle symbol is determined according to the value of 2 (step S57), and the right symbol is determined according to the value of random 2-3 (step S58). That is, random 2-1 to random 2-3
Any symbol corresponding to the value of 0 to 11 is determined as a stopped symbol. Here, when the determined middle symbol matches the left and right symbols, the symbol corresponding to the value obtained by adding 1 to the value of the random number corresponding to the middle symbol is set as the fixed symbol of the middle symbol so that it does not match the big hit symbol. I do.

The switch signal input processing and the determination processing executed by the CPU 56 will be described below. FIG.
FIG. 3 is an explanatory diagram illustrating an example of a relationship between assignment of each switch and input ports. In this embodiment, two 8-bit input ports (input port 0 and input port 1) are used for inputting a switch detection signal (switch signal), and each I / O address is 0E (H). , 0F
(H).

Bits 0 to 7 of the input port 0 are respectively assigned to a winning opening switch 24a, a winning opening switch 24b, a winning opening switch 19a, a winning opening switch 19b, a starting opening switch 17, a count switch 23, and a V count switch (specifying). The detection signals of the area switch 22 and the gate switch 12 are input. The detection signals of the prize ball count switch 301A, the full tank switch 48, and the ball out switch 187, and the count switch short-circuit signal are input to bits 0 to 3 of the input port 1, respectively.

In this embodiment, when the ON state of the detection signal continues for a predetermined time, it is determined that the switch has been turned on. A switch timer is used to measure a predetermined time. Switch timer is backup RAM
This is a 1-byte counter formed in the area, and is incremented by 1 every 2 ms when the detection signal indicates the ON state.
As shown in FIG. 16, the switch timer determines the number n of detection signals.
Only provided. In this embodiment, n = 12. In the RAM, the addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports (the order from the top to the bottom shown in FIG. 15).

FIG. 17 is a flowchart showing a processing example of the switch processing (see FIG. 10) in step S21.
In addition, as shown in FIG. 10, the switch process is first executed in the game control process. In the switch processing, the CPU 56 first inputs data input to the input port 0 (step S71). Next, "8" is set as the number of processes (step S72), and the address of the switch timer for the winning opening switch 24a is set in the pointer (step S73). Then, the switch check processing subroutine is called (step S
74).

FIG. 18 is a flowchart showing a switch check processing subroutine. In the switch check processing subroutine, the CPU 56 sets the port input data, in this case, the input data from the input port 0, as a “comparison value” (step S81). Also,
Set clear data (00) (step S8)
2). Then, the switch timer indicated by the pointer (the address of the switch timer is set) is loaded (step S83), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S8).
4). The data of the input port 0 is set as the comparison value. Then, in this case, the detection signal of the winning opening switch 24a is pushed out by the carry flag.

If the value of the carry flag is "1", that is, if the detection signal of the winning opening switch 24a is on, the value of the switch timer is incremented by 1 (step S8).
7). If the value after the addition is not 0, the added value is returned to the switch timer (steps S88 and S89). Value after addition is 0
In case of, the added value is not returned to the switch timer.
That is, the value of the switch timer is already the maximum value (255)
If it has reached, do not increase the value any further.

If the value of the carry flag is "0", that is, if the detection signal of the winning opening switch 24a is in the OFF state, clear data is set in the switch timer (step S86). That is, if the switch is off, the value of the switch timer returns to zero.

Thereafter, the CPU 56 increments the pointer (address of the switch timer) by 1 (step S90) and decrements the number of processes by 1 (step S91). If the number of processes has not become zero, the process returns to step S82. Then, the processing of steps S82 to S92 is repeated.

The processes of steps S82 to S92 are repeated for the number of processes, that is, eight times. In the meantime, the detection signals of the switches input to the 8 bits of the input port 0 are sequentially turned on or off. A check process is performed, and if it is in the ON state, the value of the corresponding switch timer is incremented by one.

The CPU 56 executes the step S of the switch process.
At 75, the data input to the input port 1 is input. Next, "4" is set as the number of processes (step S76), and the address of the switch timer for the winning ball count switch 301A is set in the pointer (step S77). Then, a switch check processing subroutine is called (step S78).

In the switch check processing subroutine,
Since the above-described processing is executed, steps S82 to S9 are performed.
2 is repeated for the number of processes, that is, four times. During that time, the detection signal of the switch input to the 4 bits of the input port 1 is sequentially checked to determine whether it is on or off. If it is in the ON state, the value of the corresponding switch timer is increased by one.

As described above, since the input determination processing has a module configuration (one integrated processing block in the control program), the program capacity can be reduced and it can be easily used for other models. . Further, when a plurality of electrical component control means use the same program in the same model, the input determination processing module in one electrical component control means can be easily ported to another electrical component control means. For example, the payout control means is provided with a prize ball count switch, a ball lending count switch, and the like for detecting a paid out game medium, for payout control. An input determination processing module can be used. Since the input determination processing module can be easily ported to other electric component control means, there is an effect that the development period of the gaming machine is shortened.

Further, as in this embodiment, the input determination module (switch processing) is executed only once at the time of executing one game control processing, and all the switches are turned on or off. A check is made to see if there is. Therefore, the program capacity is further reduced and the program execution time is reduced as compared with the configuration in which the input determination module is called for each switch.

Also, a timer counter (switch timer) is provided for each switch, and whether or not the switch is on or off is checked based on the number of processes and a pointer indicating the timer counter. Increase. That is, it is possible to cope with an increase or decrease in the number of switches in the gaming machine by changing the number of processes.

Furthermore, it is easy to divert the input determination module used in this embodiment to another model having a different number of switches or a different port address. If the number of switches is different or the port address is different, for example, in the flowchart shown in FIG. 17, steps S71, S72, S73, S75, S76, S7
Only the value at 7 needs to be changed.

In this embodiment, since the game control process is started every 2 ms, the switch process is also executed once every 2 ms. Therefore, the switch timer is incremented by 1 every 2 ms.

FIG. 19 is an explanatory diagram showing the relationship between the ON state of the switch and the switch check processing. In this embodiment, the starting port switch 17 and each winning port switch 19
a, 19b, 24a, 24b, count switch 23,
Regarding the detection outputs of the V count switch 22, the gate switch 12, and the winning ball count switch 301A, when the value of the corresponding switch timer becomes "2", it is determined that the switch has been turned on.

When the value of the corresponding switch timer of the full tank switch 48 becomes "50", it is determined that the switch has certainly been turned on. When the value of the switch timer of the out-of-ball switch 187 becomes "250", it is determined that the switch has certainly been turned on.

If it is determined that the switch has been turned on, a process related to control of the corresponding electric component is started. For example, when it is determined that the starter switch 17 has been turned on, control for starting variable display of symbols on the variable display unit 9 as an electric component is started, and the ball dispensing device 97 as an electric component is started. Is executed to start the processing in which six game balls are paid out as premiums. In this embodiment, the control for starting variable display of symbols is, specifically, a process of extracting random numbers required for variable display, and a process of paying out six game balls as prizes is a specific process. More specifically, the processing is to send a payout control command to the payout control board 37.

If it is determined that the full tank switch 48 or the out-of-ball switch 187 has been turned on,
A process for stopping the operation of the ball payout device 97 is performed.
Specifically, the process is a process of sending a payout control command designating stop of payout to the payout control board 37.

Next, an example will be described in which the switch is turned on and the processing relating to the control of the electric components is started. First, a start-up switch check process will be described with reference to the flowchart of FIG. The starting port switch check process is a process executed in step S300 in the special symbol process process shown in FIG. In the starting port switch check processing, the CPU 56 sets “0” as an offset of the input determination value table (Step S).
41), "4" is set as the offset of the address of the switch timer (step S42). Although the input judgment value table will be described later, the offset “0” means that the first data of the input judgment value table is used. Further, the offset “4” of the address of the switch timer means that the fourth (starting from 0) switch timer is used. Then, the switch-on check routine is called (step S43).

FIG. 21 is a flowchart showing a switch-on check routine. In the switch-on check routine, the CPU 56 sets the start address of the input determination value table (Step S91). And
An offset (in this case, “0”) is added to the address (step S92), and the switch-on determination value is loaded from the address after the addition (step S93).

FIG. 22 is an explanatory diagram showing a configuration example of the input judgment value table. As shown in FIG. 22, in the input determination value table, "2", "50", "250", "3"
Determination values of “0”, “250”, and “1” are set.
These numerical values are for determining whether or not the switch has been turned on. In other words, based on the value of the timer counter (switch timer), it is a numerical value for determining whether or not to start the processing related to the corresponding electric component control.

In this case, since the offset is “0”, the switch-on judgment value “2” is loaded.

When such an input judgment value table is provided, it can be easily used for other models. When diverting to another model, it is only necessary to change the judgment value in the table. At this time, if the number of switches is different, the table size may be changed. Furthermore, in the same model, the input judgment value table in one electric component control means and the input judgment value table in another electric component control means differ only in the judgment values and table sizes in the table. For example, the payout control means is provided with a prize ball count switch, a ball lending count switch, and the like for detecting a paid out game medium for the payout control. Can be used.

Next, the CPU 56 sets the start address of the switch timer (step S94), adds an offset (in this case, "4") to the address (step S95), and sets the start address of the switch timer from the added address. The value is loaded (step S96). Since the switch timers are arranged in the same order as the bit order of the input port shown in FIG. 15, the value of the switch timer corresponding to the starting port switch 17 is loaded in this case.

Then, the CPU 56 compares the loaded value of the switch timer with the switch-on judgment value (step S97). If they match, a switch-on flag is set (step 98).

In the start-up opening check process shown in FIG. 20, when it is detected that the switch-on flag has been set (step S44), it is confirmed whether or not the number of start winning storages has reached the maximum value of 4 (step S45). .
If the number of memorized start winnings has not reached 4, the number of memorized start winnings is increased by 1 (step S46), and values such as random numbers for judging big hits are extracted. Then, they are stored in the buffer area corresponding to the value of the number of stored start winnings (step S4).
7). If the number of stored start winnings has reached 4, the process of increasing the number of stored start winnings is not performed. That is, in this embodiment, the number of hit balls that have won the maximum of four starting winning openings 17 can be stored.

FIG. 23 is an explanatory diagram showing random numbers and the like set in the buffer. As shown in FIG.
3 and the fluctuation time reduction determination time (3.6 in this example).
s) is set in the buffer. Note that the process of setting a random number or the like in the buffer corresponds to a process for controlling the variable display unit 9 as an electric component.

FIG. 24 is a flowchart showing an example of the winning ball signal processing in step S31 (see FIG. 10) in the game control processing. In this embodiment, in the winning ball signal processing, the winning opening switches 19a, 19b, 24a, 2
4b, count switch 23 and starting port switch 17
Is turned on without fail, and when turned on, control is performed so that a predetermined payout control command is sent to the payout control board 37, and the full tank switch 48 and the ball out switch 187 are turned on without fail. It is determined whether or not it is turned on, and when it is turned on, processing such as controlling to send a predetermined payout control command to the payout control board 37 is performed.

In the winning ball signal processing, the CPU 56
“0” is set as the offset of the input determination value table (step S121), and “0” is set as the offset of the address of the switch timer (step S12).
2). The offset “0” of the input judgment value table means that the first data of the input judgment value table is used. Further, since the respective switch timers are arranged in the same order as the bit order of the input port shown in FIG.
This means that the switch timer corresponding to 4a is designated. Also, “4” is set as the number of repetitions (step S123). Then, the switch-on check routine is called (step S124).

In this case, in the switch-on check routine (see FIG. 21), if the value of the switch timer corresponding to the winning opening switch 24a matches the switch-on determination value "2", the switch-on flag is set. (Step S125). When the switch-on flag is set, 10 counters are incremented by 1 (step S126). The switch check-on routine is executed for the initially set number of repetitions (Steps S127 and S128) while the offset of the address of the switch timer is updated (Step S129).
As for the winning opening switches 19a, 19b, 24a and 24b, the value of the corresponding switch timer is compared with the switch-on determination value "2". The ten counter is a counter that indicates the number of ten game ball payouts as prizes.

Next, the CPU 56 sets "0" as an offset of the input judgment value table (step S13).
0), “4” is set as the offset of the address of the switch timer (step S131). The offset “0” of the input judgment value table means that the first data of the input judgment value table is used. Further, since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 15, the offset “4” of the address of the switch timer indicates that the switch timer corresponding to the starting port switch 17 is designated. Means Then, the switch-on check routine is called (step S1).
32).

In the switch-on check routine,
If the value of the switch timer corresponding to the starting port switch 17 matches the switch-on determination value "2", the switch-on flag is set (step S133), and the six counters are incremented by 1 (step S134). . In addition,
The six counter is a counter that indicates the number of payouts of six game balls as prizes.

Next, the CPU 56 sets "0" as an offset of the input judgment value table (step S13).
5), “5” is set as the offset of the address of the switch timer (step S136). The offset “0” of the input judgment value table means that the first data of the input judgment value table is used. Further, since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 15, the offset “5” of the address of the switch timer indicates that the switch timer corresponding to the count switch 23 is designated. means. Then, the switch-on check routine is called (step S).
137).

In the switch-on check routine,
If the value of the switch timer corresponding to the count switch 23 matches the switch-on determination value "2", the switch-on flag is set (step S138).
The five counters are incremented by 1 (step S134). The 15 counter is a counter indicating the number of payouts of 15 game balls as prizes.

Further, the CPU 56 sets "1" as an offset of the input judgment value table (step S15).
0), “9” is set as the offset of the address of the switch timer (step S151). The offset “1” in the input judgment value table is equal to 2 in the input judgment value table.
This means that the second data “50” is used. Further, since the switch timers are arranged in the same order as the bit order of the input port shown in FIG. 15, the switch timer address offset “9” indicates that the switch timer corresponding to the full switch 48 is designated. Means Then, the switch-on check routine is called (step S152).

In the switch-on check routine,
If the value of the switch timer corresponding to the full tank switch 48 matches the full tank switch-on determination value "50", the switch-on flag is set (step S15).
3) The full tank flag is set (step S15)
4). Although not explicitly shown in FIG. 25, when the value of the switch timer corresponding to the full tank switch 48 becomes 0, the full tank flag is reset.

Further, the CPU 56 sets “2” as the offset of the input judgment value table (step S15).
6), “0A (H)” is set as the offset of the address of the switch timer (step S157). The offset “2” in the input determination value table means that the third data “250” in the input determination value table is used. Further, since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 15, the offset “0A (H)” of the address of the switch timer is designated by the switch timer corresponding to the out-of-ball switch 187. Means to be done. Then, the switch-on check routine is called (step S158).

In the switch-on check routine,
If the value of the switch timer corresponding to the out-of-ball switch 187 matches the out-of-ball switch-on determination value "250", the switch-on flag is set (step S1).
59), a ball out flag is set (step S16)
0). Although not explicitly shown in FIG. 25, a switch-off timer corresponding to the out-of-ball switch 187 is prepared, and when its value reaches 50, the out-of-ball flag is reset.

Then, the CPU 56 checks whether or not the payout is stopped (step S201). The payout stop state is a state after a payout stop state designation command is sent to the payout control board 37. If it is not the payout stop state, it is checked whether the above-mentioned ball out-of-ball state flag or the full tank flag is turned on (step S202).

When either of them changes to the ON state,
The command transmission table for the payout stop state designation is set (step S203). When predetermined data is set in the command transmission table, for example, a payout control command transmission process is executed in the command control process (step S27) in the game control process shown in FIG. In step S202, when one of the flags is already on and the other flag is on, the command transmission table is not set (step S203).

If the payout is stopped, it is checked whether both the out-of-ball state flag and the full tank flag have been turned off (step S204). When both are turned off, a command transmission table relating to the payout stop release designation is set (step S205).

Next, the CPU 56 controls to set a payout control command relating to the number of winning balls according to the winning in the command transmission table. First, the values of the 15 counters are checked (step S221). As mentioned above, 1
The five counters are counted up when the game ball wins the big winning opening and the count switch 23 is turned on. Fifteen
If the value of the number counter is not 0, a command transmission table relating to the fifteen winning ball number instructions is set (step S222). Further, the value of the 15 counters is decremented by one (step S223). Further, 15 is added to the payout command number cumulative value (step S224).

If the value of the 15 counter is 0, the value of the 10 counter is checked (step S225). As described above, the ten counters indicate that the gaming ball has won the winning opening and the winning opening switches 19a, 19b, 24a, 24b
Counts up when turns on. If the value of the ten counter is not 0, a command transmission table relating to the ten winning ball number instructions is set (step S22).
6). Further, the value of the ten counters is decremented by one (step S227). Further, 10 is added to the payout command number cumulative value (step S228).

If the value of the ten counter is 0, the value of the six counter is checked (step S231). As described above, the six counters are counted up when the game ball wins the starting winning port and the starting port switch 17 is turned on. If the value of the six counter is not 0, the command transmission table for the six winning ball number instructions is set (step S232). Also, the value of the six counters is-
1 (step S233). Further, 6 is added to the payout command number cumulative value (step S234).

As described above, when the payout control command is to be output from the game control means to the payout control board 37, the command transmission table is set. When the command transmission table is set,
The award ball paying flag is turned on (step S235). When the award ball paying flag is on (step S236), the award ball number monitoring process is performed (step S236).
237).

In the prize ball number monitoring process, a switch-on check is performed on the prize ball count switch 301A.
1 is done. The switch-on check of the prize ball count switch 301A is performed, for example, by setting “0” as the offset of the input determination value table and “8” as the offset of the address of the switch timer, and setting the switch-on shown in FIG. This is performed by calling a check routine.

As described above, when the value of the switch timer matches the value set in the input determination value table, a process for controlling electric components provided in the gaming machine is started. In the above example, for example, when the value of the switch timer corresponding to the winning opening switches 19a, 19b, 24a, 24b matches the value set in the input determination value table, the ball payout device 97 as an electric component is controlled. Control processing for sending out a payout command is started.

Further, the determination value for determining whether or not to start the processing for controlling the electric components is not common to all the switches. In the above example, the switch relating to the winning etc. is “2”. , But "50" for the full tank switch 48 and the ball out switch 1
87 is “250”. As described above, if the determination value is changed, it is possible to perform appropriate control according to the switch setting purpose. For example, a switch related to winning is set to detect that the game ball has passed the winning opening path, so that the detectable period is relatively short. In such a case, the judgment value is reduced. In addition, the full tank switch 48 and the out-of-ball switch 187 are generally provided to detect the degree of storage of the game ball storage portion. There is a possibility that the ON state will be exhibited instantaneously. The determination value is increased so that such an ON state is not detected.

Further, since the judgment value is set in the input judgment value table, it can be easily changed. That is, when it is desired to change the judgment value, it is only necessary to change the data area after the ROM, and it is not necessary to change the program.

In the switch processing (input determination module), the detection signals are determined for all the switches, so that there is no deviation in the switch-on check. For example, the switch-on check of the starting port switch 17 includes a special symbol process process (step S25) and a winning ball signal process (step S25) in the game control process.
31). In the special symbol process processing, a switch-on check is performed in connection with the control of the variable display unit 9, and in the winning ball signal processing, a switch-on check is performed in connection with the prize payout from the ball payout device 97.

In this case, for example, if the input determination module is called for the start-up switch 17 in connection with the control of the variable display section 9 and the input determination module is called in connection with the prize withdrawal, Between the execution of the input determination module related to the control of the variable display unit 9 and the execution of the input determination module related to the prize payout, when the detection signal of the starting port switch 17 changes from the OFF state to the ON state, A shift occurs in the switch-on check. That is, although it is determined that the start port switch 17 has not been turned on at the time of execution of the input determination module related to the control of the variable display unit 9, the startup is performed at the time of execution of the input determination module related to prize payout. There is a possibility that it is determined that the mouth switch 17 is reliably turned on.

However, in this embodiment, since the ON / OFF state of the switch is determined by one input determination module, such a shift does not occur.
That is, in the game control process shown in FIG. 10, the on / off state of the switch is determined in the switch process of step S21, and the determination result is, for example, a special symbol process process (step S25) and a winning ball. Since it is used in the signal processing (step S31), during one game control processing, it is determined on the one hand that the switch has been reliably turned on, and on the other hand, it has been determined that the switch has not been reliably turned on yet. There is no such thing.

FIG. 27 is an explanatory diagram showing a configuration example of a switch-on determination value table used in another embodiment. In the switch-on determination value table shown in FIG. 27, the address of the input port, the address of the switch timer corresponding to each switch, and the number of processes (the number of process repetitions) are set.

FIG. 28 is a flowchart showing the switch processing (step S21 shown in FIG. 10) in this embodiment. In this embodiment, in the switch processing, the CPU 56 specifies the start address of the switch-on determination value table (Step S401) and calls the switch check processing (Step S402).

FIG. 29 is a flowchart showing the switch check processing (step S402). In the switch check processing, the CPU 56 first obtains the address of the input port 0 from the designated address (designated address) (step S411). Then, data of the input port 0 is input (step S412), and the input data is set as a comparison value (step S413).
Further, the designated address is incremented by 1, and the number of processes is obtained from the switch-on determination value table based on the added value (steps S414 and S415). And the specified address is +
After performing 1 (step S416), the determination processing is called (step S417).

FIG. 30 shows the determination process (step S417).
It is a flowchart which shows. In the determination process, the CP
U56 sets the clear data (00) (step S431). Then, the switch timer indicated by the designated address is loaded (step S432), and the comparison value is shifted right (from the upper bit to the lower bit) (step S433). The data of the input port 0 is set as the comparison value. Then, in this case, the detection signal of the winning opening switch 24a is pushed out by the carry flag.

If the value of the carry flag is "1", that is, if the detection signal of the winning opening switch 24a is on, the value of the switch timer is incremented by 1 (step S4).
36). If the value after the addition is not 0, the added value is returned to the switch timer (steps S437, S438). When the value after the addition becomes 0, the added value is not returned to the switch timer.

If the value of the carry flag is "0", that is, if the detection signal of the winning opening switch 24a is off, clear data is set in the switch timer (step 435). That is, if the switch is off, the value of the switch timer returns to zero.

Thereafter, the CPU 56 sets the designated address to 1
While adding (step S439), 1 is subtracted from the number of processes (step S440). If the number of processes has not become zero, the process returns to step S432 (step S441).
Then, the processing of steps S432 to S441 is repeated.

The processes of steps S432 to S441 are repeated for the number of processes, that is, eight times. In the meantime, the detection signals of the switches input to the 8 bits of the input port 0 are sequentially turned on or off. A check process is performed, and if it is in the ON state, the value of the corresponding switch timer is incremented by one.

Further, in the switch check processing,
In step S421, the CPU 56 acquires the address of the input port 1 from the switch-on determination table based on the designated address. Then, the data input to the input port 1 is input (step S422). Next, the input data is set as a comparison value (step S
423). After the designated address is incremented by one and the switch-on decision address is incremented by one based on the added value (step S426), the judgment process is called (step S426).
427).

In the determination process, since the above-described process is executed, the processes of steps S432 to S441 are repeated for the number of processes, that is, four times.
The detection signal of the switch input to the bit is sequentially checked to determine whether it is in the on state or the off state. If the state is the on state, the value of the corresponding switch timer is incremented by one.

Also in this embodiment, when one game control process is executed, the input determination module (switch process) is executed only once, and it is checked whether all the switches are on or off. Is performed.
Therefore, the program capacity is reduced and the program execution time is reduced as compared with the configuration in which the input determination module is called for each switch.

In particular, in a gaming machine provided with a large number of detecting means such as a gaming machine provided with a switch corresponding to each winning opening, the load required for the CPU 56 to determine an input is large.
In such a case, if the input determination module is configured to be called corresponding to each detection unit, the program capacity increases and the processing time increases. But,
As in the above embodiments, if the input determination module (switch processing) is executed only once and all switches are checked whether they are on or off, It is not necessary to increase the program capacity, and the processing time is not lengthened.

In each of the above-described embodiments, the special symbol process process and the winning ball signal process have been described as examples. However, in other processes in the game control process, it is determined whether or not the switch is reliably turned on depending on the determination value. Checks have been made. For example, in the error processing (step S22), a value of a count switch timer for detecting a count switch disconnection error or a count switch short-circuit error timer for detecting a count switch short-circuit error is checked. These timers can also be configured to perform addition processing in the switch processing.

In the error processing, if the value of the count switch timer is "250", it is determined that a count switch disconnection error has occurred. If the value of the count switch short-circuit error timer is "1", the count switch is short-circuited. It is determined that an error has occurred.

In each of the above embodiments, the value of each switch timer is stored in the backup RAM, so that when power is restored after a power failure or the like, the disadvantage given to the player is minimized. Can be stopped.
For example, if a power failure occurs when the value of the switch timer corresponding to the start-up switch 17 becomes “2”, it is recognized that, at the time of recovery, a start winning prize was obtained immediately before the power failure in the special symbol process process. And can perform processing based on it.

In the above embodiment, the game control means is exemplified as the electric component control means, but the present invention can be applied to other electric component control means, for example, a payout control means.
The payout control means is provided with a prize ball count switch, a ball lending count switch, and the like for detecting the paid out game media, for payout control, but in order to detect those switch states, The input determination module and the input determination value table as described above can be applied.

Further, in the pachinko gaming machine 1 of each of the above-described embodiments, when a special symbol is variably displayed on the variable display section 9 based on a start winning prize, a predetermined symbol combination becomes a predetermined game value. Although it was a first-class pachinko gaming machine that can be given to a player, a predetermined game value that can be given to a player when there is a prize in a predetermined area of an electric accessory that is opened based on a start winning prize. Two types of pachinko machines,
A third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize in a predetermined electric accessory which is opened when a stop symbol of a symbol variably displayed based on a start winning prize is a predetermined combination of symbols. Even so, the present invention can be applied.
Further, the present invention is not limited to pachinko gaming machines, but may be applied to slot machines and the like.

[0172]

As described above, according to the present invention, the gaming machine is provided with an input determination module in which the electric component control means determines the state of the detection signal from the detection means, and the input determination module is operated once. Since the configuration is such that the state of a plurality of detection signals is determined by executing the processing, the processing of determining the input signal from the detection unit can be made more efficient, and the program capacity required for the input determination processing increases. ,
This has the effect of preventing the time required for the input determination processing from being lengthened. Further, in a case where a plurality of controls are performed in response to one detection signal, it is possible to prevent a deviation from occurring between the respective controls.

Measuring means capable of measuring the ON period of the detection signal from the detecting means is provided for each detecting means, and the input determining module updates the value of each measuring means corresponding to the plurality of detecting means. In the case where the detection signal is turned on, the on period of the detection signal can be measured by the measuring means. Therefore, it is determined that the detection signal has been turned on when the measured value has exceeded a predetermined value. And the reliability of the detection signal can be improved.

In the case where the detecting means is provided for each of the winning ports provided in the game area, it is possible to quickly detect that there is a prize, so that a prize for the player based on the prize is provided. The application can be performed quickly.

When the plurality of detecting means include detecting means for detecting whether or not the payout of the game medium is possible, the determination of the detection signal for determining whether or not the payout is possible is also performed. Can be performed in a lump.

When the processing for controlling the electric components provided in the game machine is performed when the value of the measuring means reaches a predetermined judgment value, the electric components are controlled. Can be easily determined.

When the electric component control means has an input judgment value table in which predetermined judgment values are set, the program capacity can be reduced and the versatility of the judgment processing can be improved.

If the predetermined judgment value is set to a different value according to the type of the detecting means, appropriate control can be performed according to the setting purpose of the detecting means.

If the determination result of the input determination module is configured to be stored in the storage means capable of storing the stored content even when the power supply to the gaming machine is stopped, the disadvantage given to the player is reduced. Can be minimized.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is an explanatory view showing each substrate provided on the back surface of the pachinko gaming machine.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram illustrating an example of a circuit configuration on a main board.

FIG. 5 is a block diagram illustrating a configuration example of a power supply board.

FIG. 6 is a block diagram illustrating an example of a configuration around a CPU on a main board.

FIG. 7 is a flowchart showing a main process executed by a CPU on a main board.

FIG. 8 is a flowchart illustrating an initialization process.

FIG. 9 is a flowchart showing a 2 ms timer interrupt process.

FIG. 10 is a flowchart showing a game control process.

FIG. 11 is an explanatory diagram showing each random number.

FIG. 12 is a flowchart showing a special symbol process process.

FIG. 13 is a flowchart showing a jackpot / outlier determination process.

FIG. 14 is a flowchart showing a jackpot determination process.

FIG. 15 is an explanatory diagram showing an example of the relationship between each switch and the assignment of input ports.

FIG. 16 is an explanatory diagram showing an example of forming a switch timer in a RAM.

FIG. 17 is a flowchart illustrating an example of a switch process.

FIG. 18 is a flowchart illustrating an example of a switch check process.

FIG. 19 is an explanatory diagram illustrating a relationship between a switch on state and a switch check process.

FIG. 20 is a flowchart showing a starting port switch check process.

FIG. 21 is a flowchart showing a switch-on check process.

FIG. 22 is an explanatory diagram illustrating a configuration example of an input determination value table.

FIG. 23 is an explanatory diagram showing random numbers and the like set in a buffer.

FIG. 24 is a flowchart showing winning ball signal processing.

FIG. 25 is a flowchart showing winning ball signal processing.

FIG. 26 is a flowchart showing winning ball signal processing.

FIG. 27 is an explanatory diagram showing another configuration example of the switch-on determination value table.

FIG. 28 is a flowchart illustrating another example of the switch processing.

FIG. 29 is a flowchart illustrating another example of the switch check process.

FIG. 30 is a flowchart illustrating a determination process.

[Explanation of symbols]

 9 Variable display unit 31 Game control board (main board) 12 Gate switch 17 Starter switch 19a, 19b, 24a, 24b Winner switch 22 V count switch (specific area switch) 23 Count switch 48 Full switch 56 CPU 57 I / O port 187 Ball out switch 301A Prize ball count switch

Claims (8)

[Claims] 1. A gaming machine in which a player can play a predetermined game, comprising: an electronic component control means for controlling an electrical component provided in the gaming machine; A plurality of detection means for providing a detection signal by means of the electronic component control means, wherein the electric component control means has an input determination module for determining the state of the detection signal from the detection means, and executes the input determination module once to execute the input determination module. A gaming machine for determining a state of a plurality of detection signals. 2. A measuring means capable of measuring an on-period of a detection signal from a detecting means is provided for each detecting means, and an input determining module calculates a value of each measuring means corresponding to a plurality of detecting means. The gaming machine according to claim 1, further comprising a process of updating. 3. The gaming machine according to claim 1, wherein a detecting means is provided corresponding to each of all winning ports provided in the gaming area. 4. The gaming machine according to claim 1, wherein the plurality of detecting means include detecting means for detecting whether or not payout of the game medium is possible. 5. The gaming machine according to claim 2, wherein a process for controlling an electric component provided in the gaming machine is performed when the value of the measuring means reaches a predetermined determination value. 6. The gaming machine according to claim 5, further comprising an input judgment value table in which a predetermined judgment value is set. 7. The gaming machine according to claim 5, wherein the predetermined judgment value is set to a different value depending on the type of the detecting means. 8. The gaming machine according to claim 1, wherein the determination result of the input determination module is stored in storage means capable of storing the stored content even when the power supply to the gaming machine is stopped.