JP2001161910A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine by which cost is not raised even if additional functions for original game control are equipped by equipping a power source monitoring IC. SOLUTION: A power monitoring IC 902 to constitute the first power source monitoring circuit is mounted on the power source circuit board 910. The power monitoring IC 902 guide in the VSL power voltage and monitors the VSL power source voltage to detect generation of power OFF. Specifically, when the VSL power source voltage became below a prescribed value, a low power source voltage signal is outputted to inform of the power OFF. An electric parts control microcomputer recognizes the power OFF by a low power source voltage signal and processes necessary data storage. Because a circuit to realize additional functions such as data storing process is mounted on the power source circuit board 910, other circuit boards are not required to mount on such a circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko gaming machine in which a game is played according to a player's operation.
In particular, the present invention relates to a gaming machine in which a game is played according to a player's operation in a gaming area of a gaming board.

[0002]

2. Description of the Related Art As a gaming machine, for example, a game medium such as a game ball is fired into a game area by a launch device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prizes are won. Some balls are paid out to players. Further, a variable display unit whose display state can be changed is provided, and when a display result of the variable display unit becomes a predetermined specific display mode, a predetermined game value is provided to the player. There is.

[0003] The game value means that the state of the variable prize ball device provided in the game area of the gaming machine is in an advantageous state for a player who is likely to win a hit ball, or in an advantageous state for the player. Or a condition that the conditions for paying out prize game media are easily satisfied.

In a pachinko gaming machine, when a display result of a variable display section for displaying a special symbol is a combination of a predetermined specific display mode, it is generally called a "big hit". When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. In each open period, a predetermined number (for example, 10
) Will be closed when there is a prize in the special winning opening.
The number of opening of the special winning opening is a predetermined number (for example, 16
Round). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. Further, at the time when the special winning opening is closed, predetermined conditions (for example, winning in the V zone provided in the special winning opening)
Is not established, the big hit gaming state ends.

[0005] The progress of the game including the occurrence of a big hit is controlled by a microcomputer circuit for game control mounted on a game control board (main board) installed on the back of the game board. Further, a lamp, an LED, a speaker, and the like for enhancing a game effect are installed on the game board surface or inside the frame. A board on which a circuit for performing the on / off control is mounted is also installed on the back of the game board. Also, a display control board equipped with circuits for controlling the display of a variable display unit such as a liquid crystal display (LCD) for generating a big hit, a launch control board equipped with each circuit for controlling the launch of a hit ball, a prize ball A payout control board and the like for controlling payout of ball rental are also provided on the back of the game board. Hereinafter, each substrate may be referred to as an electric component control substrate. The control means mounted on the electric component control board may be referred to as an electric component control means.

[0006] Each circuit mounted on each electric component control board and each component provided in the gaming machine have a DC 5V.
, Those using DC12V, and those using other voltages. Therefore, in the gaming machine, it is necessary to create various power supply voltages. Therefore, a power supply board for generating various voltages used in each electric component control board and each component may be provided separately from each electric component control board.

[0007]

In a gaming machine, there are cases where various additional functions are provided in addition to the configuration for each electric component control means to perform the original control. Additional functions include, for example, a function for controlling the progress of the game so as not to be impaired even when a momentary power interruption or the like occurs, setting an advantage for the player, and a game clerk easily recovering from a failure of the gaming machine There is a function to make it. To implement these additional functions, additional circuit components and control signals must be added. As a result, disadvantages such as an increase in the cost of the gaming machine occur.

Accordingly, an object of the present invention is to provide a gaming machine which does not increase the cost as much as possible even when an additional function for the original game control is provided in the gaming machine.

[0009]

A gaming machine according to the present invention comprises:
A gaming machine in which a gaming area is provided on a gaming board, and which provides a player with a predetermined value in accordance with a prize of a game ball to a prize area provided in the gaming area. An electric component control board mounted with an electric component control means for performing processing for controlling the component, and a power supply board for creating a voltage used in the gaming machine, which is a board different from the electric component control board, and The circuit board is characterized in that, in addition to a circuit for generating a voltage, an element that affects processing performed by the electric component control unit is mounted.

[0010] An element which influences the processing performed by the electric component control means is, for example, monitoring a predetermined potential power supply used in the game machine and sending a detection signal to the electric component control means when the first detection condition is satisfied. This is a first power supply monitoring means for outputting.

The electric component control means may be configured to perform a predetermined power supply stop processing based on a detection signal from the first power supply monitoring means.

The first power supply monitoring means monitors a potential power supply which is the same as or different from the predetermined potential power supply, and the execution of at least the power supply stop processing is completed after the first detection condition is satisfied in the first power supply monitoring means. A second power supply monitoring unit that outputs a detection signal when a second detection condition set to be satisfied after the second power supply monitoring unit is satisfied, wherein the electric component control unit receives the detection signal from the second power supply monitoring unit The system may be configured to be reset in response to the request.

The first power supply monitoring means and the second power supply monitoring means monitor the voltage of the same predetermined potential power supply, and the voltage of the predetermined potential power supply at which the second power supply monitoring means outputs a detection signal is The first power supply monitoring means may be configured to be lower than the voltage at which the detection signal is output.

In the power supply stop processing, for example, the storage means capable of holding the contents immediately before the power supply is stopped includes:
This includes a process for storing data capable of restarting control when power supply is restarted.

A detection signal from the first power supply monitoring means is outputted to a plurality of the plurality of electric component control means, and the first detection condition is configured to be the same for the plurality of electric component control means. May be.

The electric component control means includes a microcomputer, and the second power supply monitoring means for outputting a detection signal for resetting the microcomputer is provided on an electric component control board on which the microcomputer is mounted. It may be.

An element affecting the processing performed by the electric component control means is, for example, a power switch for switching between supplying and shutting off power.

An element affecting the processing performed by the electric component control means is, for example, a reset switch for clearing the storage contents of the storage means capable of holding the contents immediately before the power supply is stopped. Note that in the gaming machine, the microcomputer is not mounted on the power supply board.

[0019]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as viewed from the front.

As shown in FIG. 1, the pachinko gaming machine 1 comprises:
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing payout balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7-segment L
A variable display device 8 including a variable display 10 using an ED is provided. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In the passage between the passage gate 11 and the ball exit 13, there is a gate switch 12 for detecting a hit ball passing through the passage gate 11. In addition, the winning ball that entered the starting winning port 14 is
It is guided to the back of the game board 6 and is detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

An opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball apparatus 15. In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and winning of the game balls to the winning ports 19 and 24 is detected by the winning port switches 19a and 24a. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A gaming effect LED 2 is provided on the outer periphery of the gaming area 7.
8a and gaming effect lamps 28b and 28c are provided.

In this example, one of the speakers 27
Prize ball lamp 5 that lights up when there are remaining prize balls near
1 is provided, and near the other speaker 27, a ball-out lamp 52 is provided, which lights up when the supply ball is out. Further, FIG. 1 also shows a card unit 50 which is installed adjacent to the pachinko gaming table 1 and enables lending of a ball by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is ready for use. If there is a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the display number of the variable display 10 is changed continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols with probability fluctuation, the probability of the next big hit becomes high. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, each board disposed on the back of the pachinko gaming machine 1 will be described. As shown in FIG. 2, on the back surface of the pachinko gaming machine 1, a ball storage tank 38 is provided above the mechanism plate in the frame 2A, and above the pachinko gaming machine 1 installed on the gaming machine installation island. The game ball is supplied to the ball storage tank 38 from. The game balls in the ball storage tank 38 pass through a guiding gutter 39 to reach a ball dispensing device covered with a prize ball case 40A.

On the back side of the gaming machine, a variable display control unit 29 for controlling the variable display section 9 and a game control board (main board) 31 on which a game control microcomputer and the like are mounted are installed. A payout control board 37 on which a payout control microcomputer or the like for performing ball payout control is mounted;
And a hit ball launching device that launches a hit ball into the game area 7 using the rotational force of a motor. Furthermore, the decoration lamp 25, the game effect LED 28a, the game effect lamp 28
b, 28c, a lamp control board 35 for sending signals to the prize ball lamp 51 and the ball out lamp 52, a voice control board 70 for controlling the generation of voice from the speaker 27, and a launch control for controlling the hit ball launching device. A substrate 91 is also provided.

Further, DC30V, DC21V, DC1
A power supply board 910 on which a power supply circuit for generating 2V and 5V DC is mounted is provided, and a terminal board 1 provided with terminals for outputting various information to the outside of the gaming machine is provided above.
60 are installed. Also, near the center, the main substrate 3
An information terminal board (external information output device) 34 having terminals for outputting various types of information from 1 to the outside of the gaming machine is installed. In FIG. 2, signals from the lamp control board 35 and the sound control board 70 are transmitted to the game effect LEDs 28a, game effect lamps 28b, 28 provided on the frame side.
c, an illuminated relay board A77 for supplying to the prize ball lamp 51 and the ball cut lamp 52 is shown, but other relay boards are provided as needed for signal relay.

FIG. 3 is a rear view of the mechanical plate of the pachinko gaming machine 1 as viewed from the rear. The game balls stored in the ball storage tank 38 pass through the guide gutter 39 and, as shown in FIG. 3, the ball-out detectors (ball-out switches) 187a and 187.
b passes through the ball supply gutters 186a and 186b to reach the ball dispensing device 97. The game balls paid out from the ball payout device 97 are supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed. A large number of prize balls are paid out based on the prize, and the hitting ball supply tray 3 becomes full. Finally, after the game balls reach the contact port 45, the game balls are further paid out. It is led to the ball tray 4. When the game ball is further paid out, the sensing lever 47 is set to the full switch 4.
By pressing 8, the full tank switch 48 is turned on. In that state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hit ball firing device 34 also stops.

Signals from a winning port switch (not shown), a starting port switch 17 and a V count switch 22 are sent to the main board 31 in order to perform the prize ball payout control. When the starting port switch 17 is turned on, the CPU 56 of the main board 31 knows that a winning corresponding to the payout of six winning balls has occurred. Further, when the count switch 23 is turned on, it is known that a winning corresponding to the payout of 15 prize balls has occurred. Then, when the winning opening switch is turned on, it is known that a winning corresponding to the payout of 10 prize balls has occurred. In this embodiment, for example, a game ball that has won the winning opening 24 is detected by the winning opening switch 24 a provided in the winning ball flow path from the winning opening 24, and the game ball that has won the winning opening 19 is detected. Is
It is detected by a winning opening switch 19a provided in a winning ball flow path from the winning opening 19.

FIG. 4 is a block diagram showing an example of a circuit configuration of the main board 31. FIG. 6 also shows the payout control board 37, the lamp control board 35, the audio control board 70, the emission control board 91, and the display control board 80. On the main board 31, a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 12,
The switch circuit 58 that supplies signals from the starting port switch 17, the V count switch 22, the count switch 23, the winning port switches 19a and 24a, the full tank switch 48, and the prize ball count switch 301A to the basic circuit 53, and the variable prize ball device 15 A solenoid circuit 59 for driving the solenoid 16 for opening and closing and the solenoid 21 for opening and closing the opening and closing plate 20 in accordance with a command from the basic circuit 53, a lighting and extinguishing of the start storage display 18 and a variable display 10 with 7-segment LEDs; A lamp / LED circuit 60 for driving the decorative lamp 25 is mounted.

According to the data supplied from the basic circuit 53, jackpot information indicating the occurrence of a jackpot, start information indicating the number of start winning balls used to start displaying an image on the variable display section 9, and probability fluctuation occurring. Is output to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as an example of a storage means used as a work memory, a CPU 56 for performing a control operation according to a control program, and an I / O port unit 57. including. In this embodiment, the ROM 54,
The RAM 55 is built in the CPU 56. That is,
The CPU 56 is a one-chip microcomputer.
The one-chip microcomputer has at least R
It is sufficient if the AM 55 is built-in.
The / O port section 57 may be externally mounted or built-in. The I / O port unit 57 is a terminal capable of inputting and outputting information in the microcomputer.

Further, the main board 31 has an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on.
And an address decode circuit 67 that decodes an address signal provided from the basic circuit 53 and outputs a signal for selecting one of the I / O ports in the I / O port unit 57. Although there is switch information input from the ball dispensing device 97 to the main board 31, FIG.
Then they are omitted.

A hit ball launching device that hits and fires a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

In this embodiment, the CPU 56 of the main board 31 controls the display of the variable display (ordinary symbol display) 18, but the normal symbol display also has the display mounted on the display control board 80. You may comprise so that it may be controlled by a control means. Also, the lamp control means mounted on the lamp control board 35 is used to control the lamps / LEDs in the game area.
May also be controlled.

FIG. 5 is a block diagram showing a signal transmission / reception part of the main board 31 and a lamp control board 35 as a control means for controlling the lamp. In this embodiment, a game effect LED provided outside the game area 7
The lamp control command indicating the lighting / extinguishing of the game effect lamps 28b and 28c and the decoration lamp 25, the lamp controlling command indicating the turning on / off of the award ball lamp 51 and the ball out lamp 52, and the interrupt signal are mainly described. The signal is output from the board 31 to the lamp control board 35.

As shown in FIG. 5, signals related to the lamp control are output from output ports 573A and 573B of the I / O port unit 57 in the basic circuit 53. In the lamp control board 35, each signal from the main board 31 is input to the lamp control CPU 351 via the buffer circuit 355. If the lamp control CPU 351 does not include an I / O port, an I / O port is provided between the buffer circuit 355 and the lamp control CPU 351. In the main board 31, the output port 573
A buffer circuit 62 is provided outside A, 573B as signal transmission direction regulating means.

In the lamp control board 35, the CPU 351 for lamp control includes a game effect LED 28a, game effect lamps 28b and 28c defined according to each command.
And according to the lighting / extinguishing pattern of the decorative lamp 25,
Game effect LED 28a, game effect lamps 28b, 28c
The lighting / extinguishing signal is output to the decorative lamp 25. The lighting / extinguishing signal is output to the game effect LED 28a, the game effect lamps 28b and 28c, and the decoration lamp 25 via an amplifier (not shown). The lighting / extinguishing pattern is stored in a built-in ROM or an external ROM of the lamp control CPU 351.

On the main board 31, the basic circuit 53 outputs a lamp control command for instructing to turn on the prize ball lamp when there is a prize ball remaining, and the basic circuit 53 runs out of balls set in the game ball supply path on the back of the game board. When the detection switch is turned on, a lamp control command for instructing the lamp to be turned off is output. In the lamp control board 35, those signals are input to the lamp control CPU 351 via the buffer circuit 355. The lamp control CPU 351 turns on / off the prize ball lamp 51 and the ball out lamp 52 according to those signals.

As the buffer circuit 355, for example, a 74HC540 which is a general-purpose CMOS-IC is used.
A low level (GND level) is always applied to the enable terminal of the 74HC540. Therefore, the output level of each buffer is determined as the input level, that is, the signal level from the main board 31. Therefore, there is no room for a signal to be transmitted from the lamp control board 35 side to the main board 31 side. Even if a circuit in the lamp control board 35 is tampered with, a signal output by the tampering is not transmitted to the main board 31.
It does not reach the side.

Accordingly, the main board 3 is moved from the lamp control board 35 to the main board 3.
It is possible to eliminate a signal line to which a signal may be given to the first signal line. That is, the unidirectionality of the signal from the main board 31 to the lamp control board 35 is ensured, and the possibility that the lamp control board 35 influences the game control on the main board 31 is eliminated. As a result, even if, for example, the lamp control board 35 is modified to give an illegal signal for causing a big hit to the basic circuit 53 of the main board 31, the illegal signal cannot be transmitted to the main board 31.

FIG. 6 is a block diagram showing a signal transmission / reception portion of the main board 31 and an audio control board 70 as control means for controlling audio. In this embodiment, a voice control command and an interrupt signal for instructing a voice output of the speaker 27 provided outside the game area 7 are output from the main board 31 to the voice control board 70.

As shown in FIG. 6, the voice control command and the interrupt signal are transmitted to the I / O port unit 5 in the basic circuit 53.
7 are output from the output ports 575A and 575B. In the audio control board 70, each signal from the main board 31 is
The data is input to the audio control CPU 701 via the buffer circuit 705. When the audio control CPU 701 does not include an I / O port, an I / O port is provided between the buffer circuit 705 and the audio control CPU 701. For example, a voice synthesis circuit 702 using a digital signal processor generates a voice or sound effect according to the instruction of the voice control CPU 701 and generates a volume switching circuit 703.
Output to The volume switching circuit 703 is a CPU for voice control.
The output level 701 is set to a level corresponding to the set volume and output to the volume amplification circuit 704. The volume amplification circuit 704 outputs the amplified audio signal to the speaker 27. In the main board 31, the output ports 575A,
A buffer circuit 71 as a signal transmission direction regulating means is provided outside 575B.

On the voice control board 70, the voice control C
The PU 701 executes the voice synthesis circuit 70 according to the voice / sound effect pattern defined according to each voice control command.
2. Output sound. The voice / sound effect pattern is stored in a built-in ROM or an external ROM of the voice control CPU 701.

As the buffer circuit 705, for example, a 74HC250 which is a general-purpose CMOS-IC is used.
A low level (GND level) is always applied to the enable terminal of the 74HC250. Therefore, the output level of each buffer is determined as the input level, that is, the signal level from the main board 31. Therefore, the voice control board 7
There is no room for a signal to be transmitted from the 0 side to the main board 31 side. For example, even if a circuit in the voice control board 70 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side.

FIG. 7 is a block diagram showing components related to the prize ball, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 7, the detection signal from the full tank switch 48 is transmitted to the main board 3 via the relay board 71.
1 is input to the I / O port 57. Full tank switch 4
Reference numeral 8 denotes a switch that detects whether the surplus ball tray 4 is full.

The ball out switch 187 (187a, 187)
The detection signal from b) is transmitted to the relay board 72 and the relay board 7.
1 is input to the I / O port 57 of the main board 31. The out-of-ball detection switch 167 is a switch that detects the shortage of replenishment balls in the ball storage tank 38, and the out-of-ball switch 187 is a switch that detects the presence or absence of game balls in the payout ball passage.

When there is a prize, a prize ball control command indicating the number of prize balls is input to the payout control board 37 from the main board 31. The award ball control command indicating the number of award balls is input to the I / O port 372a via the input buffer circuit 373. Each buffer in the input buffer circuit 373 can pass a signal only in a direction from the main board 31 to the payout control board 37. Therefore, the payout control board 37
There is no room for a signal to be transmitted from the side to the main board 31 side. Even if the circuit in the payout control board 37 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side. Further, on the main board 31, a buffer circuit 68 (irreversible raw transmission means) is provided outside the output ports 577 and 578 for outputting award ball control commands. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be given from the payout control board 37 to the main board 31 is more reliably eliminated. be able to.

The CPU 56 of the main board 31 checks whether the detection signal from the ball out switch 187 indicates that the ball is out.
Alternatively, when the detection signal from the full tank switch 48 indicates the full tank state, the prize ball control command for instructing the ball payout prohibition is transmitted. When receiving the prize ball control command instructing the ball payout prohibition, the payout control CPU of the payout control board 37
Step 371 stops the ball payout process.

Further, detection signals from the prize ball count switch 301A and the ball lending count switch 301B are also transmitted to the main board 3 via the relay board 72 and the relay board 71.
1 is input to the I / O port 57. The prize ball count switch 301A and the ball lending count switch 30
1B is provided in the prize ball mechanism portion of the ball payout device 97, and detects an actually paid prize ball.

When there is a prize, the payout control board 37 has output ports (ports G, H) 577, 578 of the main board 31.
, A prize ball control command indicating the number of prize balls is input. The output port 577 outputs 8-bit data, and the output port 578 outputs a 1-bit strobe signal (INT signal). The award ball control command indicating the number of award balls is input to the I / O port 372a via the input buffer circuit 373. The payout control CPU 371 is connected to the I / O port 37.
A prize ball control command is input via 2a, and the ball payout device 97 is driven in accordance with the prize ball control command to perform a prize ball payout. In this embodiment, the payout control CPU 37 is used.
Reference numeral 1 denotes a one-chip microcomputer having at least a RAM.

The payout control CPU 371 is connected to the output port 3
Via 72g, a ball lending number signal indicating the lending ball number is output to the terminal board 160, and a buzzer driving signal is output to the buzzer board 75. A buzzer is mounted on the buzzer board 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

Further, the input port 3 of the payout control board 37
The detection signal of the detection signal of the winning ball count switch 301A is input to 72b via the relay board 72. The drive signal from the payout control board 37 to the payout motor 289 is:
The output is transmitted to the payout motor 289 in the winning ball mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72. A drive signal from the payout control board 37 to the sorting solenoid 310 is transmitted to the sorting solenoid 310 of the ball payout device 97 via the output port 372d and the relay board 72.

The card unit 50 has a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the operation of the player, a ball lending switch signal and a return switch signal are given via the payout control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the payout control board 37. Between the card unit 50 and the payout control board 37, a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal)
A pachinko machine operation signal (PRDY signal) is exchanged via the I / O port 372f.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the payout control board 37. The payout control CPU 37 of the payout control board 37
1 turns on the XS signal in response to the BRQ signal, drives the payout motor 289, and pays out a predetermined number of loaned balls to the player. When the payout is completed, the payout control CPU 371 causes the card unit 50 to turn off the EXS signal.

As described above, all signals from the card unit 50 are input to the payout control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31. Although the main board 31 and the payout control board 37 are provided with a solenoid and a driver circuit for driving a motor or a lamp, those circuits are omitted in FIG.

In this embodiment, the RAM in the main board 31 and the payout control board 37 is backed up by a backup power supply. That is, even if the power supply to the gaming machine is stopped, the contents of the RAM are stored for a predetermined period. When detecting a drop in the power supply voltage, each CPU performs a predetermined process, and then enters a power recovery wait state. When the power is turned on, when data is stored in the RAM, each CPU restores the state before the power was turned off based on the stored data.

FIG. 8 is a block diagram showing a signal transmission / reception part of the payout control board 37 and a firing control board 91 as a control means for controlling the launching of a hit ball. As shown in FIG. 8, a firing control signal is output from the output port 577 of the payout control board 37 to the firing control board 91. In the firing control board 91, the firing control signal from the payout control board 37 is transmitted to the firing control CP via the buffer circuit 915.
Input to U911. When the firing control CPU 911 does not include an I / O port, an I / O port is provided between the buffer circuit 915 and the firing control CPU 911.

The firing control CPU 911 outputs a voltage for controlling the rotation speed of the drive motor 94 in each period of a ball hitting operation for firing a game ball and a recovery / ball replenishing operation in preparation for firing the next game ball. appear. In the ball hitting operation period, a voltage that gradually increases in accordance with the rotation operation angle with respect to the operation knob 5 is generated, and in the recovery / ball replenishment operation period, a predetermined voltage is generated.

The touch sensor circuit (not shown in FIG. 8) sends a firing permission signal to the firing control CPU 911 while the human body is in contact with the human body detecting electrode (touch sensor) 93 attached to the operation knob 5. Output to The firing control CPU 911 is supplied with a firing control signal from the main board 31. When the firing control signal and the firing permission signal are turned on, the firing control CPU 911 controls the switching of the sequence operation between the ball hitting operation period and the recovery / ball replenishment operation period, and sets a driving pattern signal and a driving pattern signal necessary for driving the driving motor 94. A drive voltage switching signal is generated.

As the buffer circuit 915, for example, a 74HC250 which is a general-purpose CMOS-IC is used.
A low level (GND level) is always applied to the enable terminal of the 74HC250.

FIG. 9 is a block diagram showing a configuration example of a power supply board 910 of a gaming machine. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the display control board 80, the audio control board 70, the lamp control board 35, and the payout control board 37, and each of the electric component control boards in the gaming machine and Generates voltages used by mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21
V, + 12V DC and + 5V DC. Also,
The capacitor 916 serving as a backup power supply is DC + 5
V, that is, charged from a power supply line for driving an IC or the like on each substrate.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 21V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
5 is connected to, for example, a relay board, from which electric power of a voltage required for each electric component control board and mechanism components is supplied.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is provided with an electric power so as to be able to hold a storage state in a backup RAM (power-backed-up RAM, that is, storage means that can be in a storage state) when the power supply to the gaming machine is cut off. Backup power supply. Also,
A diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

Note that a battery that can be charged from a +5 V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

A power supply monitoring IC 902 constituting a first power supply monitoring circuit is mounted on the power supply board 910. The power supply monitoring IC 902 introduces the VSL power supply voltage,
By monitoring the VSL power supply voltage, the occurrence of power interruption is detected. Specifically, when the VSL power supply voltage becomes equal to or lower than a predetermined value (+22 V in this example), a voltage drop signal is output in order to notify that the power is cut off. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after conversion from AC to DC, is used. The voltage drop signal from the power supply monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

The predetermined value for the power monitoring IC 902 to detect the power-off is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. Further, the power supply monitoring IC 902 is configured to monitor a voltage higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and a voltage immediately after conversion from AC to DC. Therefore, the monitoring range can be extended for the voltage required by the CPU. Therefore,
More precise monitoring can be performed. Furthermore, when VSL (+30 V) is used as the monitoring voltage, since the voltage supplied to the various switches of the gaming machine is +12 V, prevention of erroneous switch-on detection upon momentary power interruption can be expected. That is, when monitoring the voltage of the + 30V power supply,
The drop can be detected at a stage before + 12V generated after the generation of 0V starts to fall. Therefore, when the voltage of the + 12V power supply decreases, the switch output comes to the on state. However, if the + 30V power supply voltage that drops faster than + 12V is monitored and the power cutoff is recognized, the power supply is turned on before the switch output turns on. It is possible to enter a state of waiting for restoration and to enter a state where the switch output is not detected.

Since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the first power supply monitoring circuit supplies a voltage drop signal to the plurality of electric component control boards. Can be. Regardless of how many electric component control boards require a voltage drop signal, it is sufficient that only one first power supply monitoring means is provided, so that each electric component control means in each electric component control board performs a return control described later. Doing so does not add much to the cost of the gaming machine.

In the configuration shown in FIG. 9, the detection output (voltage drop signal) of the power supply monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control) via the buffer circuits 918 and 919. Although transmitted to the board 37), for example, a configuration in which one detection output is transmitted to the relay board, and the same signal is distributed from the relay board to each electric component control board may be employed. Further, a buffer circuit may be provided according to the number of substrates requiring a voltage drop signal.

FIG. 10 is a block diagram showing the flow of main signals between the substrates and the state of DC power supply. As shown in FIG. 10, AC power is supplied to the power supply board 910 from the outside. In this example, AC power of 24 V AC is supplied. The power supply board 910 has, for example,
A power supply circuit for generating DC 30 V, DC 21 V, DC 12 V, and DC 5 V is mounted. Then, the necessary voltage of each DC voltage and 24 V AC is supplied to the main board 31, the lamp control board 35, the payout control board 37, and the voice control board 7.
0, supply to the display control board 80 and the emission control board 91. In the configuration example shown in FIG. 10, the main board 31A is provided between the main board 31 and the game component.

FIG. 11 is a block diagram showing a DC voltage supplied from the power supply substrate 910 to each substrate. As shown in FIG. 11, a power supply circuit for generating various DC voltages is mounted on a power supply board 910. Note that FIG. 11 shows only the DC voltage, but 24 V AC is also supplied to each substrate as needed.

In this embodiment, the main substrate 31 has a D
C30V, DC12V and DC5V are supplied. 30V DC, 21V DC, DC
12V and 5V DC are supplied. Dispensing control board 37
Are supplied with DC30V, DC12V and DC5V. In addition, DC 30 V, D
C12V and DC5V are supplied. The voice control board 70 is supplied with DC12 and DC5V.
The display control board 80 is supplied with 12 V DC and 5 V DC.

As shown in FIG. 11, the ground side of the voltage supplied to each substrate is shared by the power supply substrate 910. Therefore, the ground level in each substrate is common. Then, a voltage level can be used as it is as a signal transmitted from one substrate to another substrate. If there is a substrate whose ground level is not shared, when transmitting signals to such a substrate, it is necessary to use a non-contact type information transmitting means such as a photocoupler, which causes an increase in cost. However, when the ground levels of all the substrates are common as in this embodiment, it is not necessary to use a photocoupler or the like.

FIG. 12 is a block diagram showing an example of a configuration around the CPU 56 for power supply monitoring and power supply backup. As shown in FIG. 12, a voltage drop signal from a first power supply monitoring circuit (first power supply monitoring means) is
Are connected to the non-maskable interrupt terminal (NMI terminal). The first power supply monitoring circuit is a circuit that monitors the voltage of any one of various DC power supplies used by the gaming machine and detects a drop in the power supply voltage. In this embodiment, VSL
The power supply voltage is monitored and a low-level voltage drop signal is generated when the voltage value falls below a predetermined value. VSL is the largest DC voltage used in gaming machines, and is +30 V in this example. Therefore, the CPU 56 can confirm the occurrence of power interruption by the interrupt processing. In this embodiment, the first power supply monitoring circuit is a power supply board 9
10 mounted.

FIG. 12 also shows the initial reset circuit 65, but in this embodiment, the initial reset circuit 6
Reference numeral 5 also serves as a second power supply monitoring circuit (second power supply monitoring means). That is, the reset IC 651 sets the output to a low level for a predetermined time determined by the capacity of an external capacitor when the power is turned on, and sets the output to a high level after a predetermined time has elapsed. That is, the reset signal is raised to a high level to make the CPU 56 operable. Also,
The reset IC 651 monitors the power supply voltage of VSL, which is the power supply voltage equal to the power supply voltage monitored by the first power supply monitoring circuit, and sets the voltage value to a predetermined value (the power supply voltage at which the first power supply monitoring circuit outputs a voltage drop signal). (Lower value), a low-level voltage drop signal is generated. Therefore, CPU5
6 performs a predetermined power supply stop processing in response to a voltage drop signal from the first power supply monitoring circuit, and then performs a system reset. In this embodiment, the reset signal and the voltage drop signal from the second power supply monitoring circuit are the same signal.

As shown in FIG. 12, the reset IC 651
Is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. When the input to the clear terminal goes low, the counter IC 941 counts the clock signal from the oscillator 943.
The Q5 output of the counter IC 941 is output to the NOT circuit 9
45, 946 and input to the NAND circuit 947. The Q6 output of the counter IC 941 is input to a clock terminal of a flip-flop (FF) 942.
The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The other input of the OR circuit 949 is connected to the NAND circuit 9.
The output of 47 is introduced via NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration, two reset signals (low-level signals) are supplied to the reset terminal of the CPU 56 when the power is turned on.
Starts operation reliably.

Then, for example, the detection voltage of the first power supply monitoring circuit (the voltage at which the voltage drop signal is output) is set to +
22 V, and the detection voltage of the second power supply monitoring circuit is +9 V. In such a configuration, since the first power supply monitoring circuit and the second power supply monitoring circuit monitor the voltage of the same power supply VSL, the timing at which the first voltage monitoring circuit outputs the voltage drop signal The difference between the timings at which the second voltage monitoring circuit and the second voltage monitoring circuit output the voltage drop signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop processing in response to the voltage drop signal from the first power supply monitoring circuit until the power supply stop processing is completely completed.

In this example, the first detection condition that the first power supply monitoring means outputs a detection signal is that the +30 V power supply voltage has dropped to +22 V, and the second power supply monitoring means outputs the detection signal. The second detection condition to be output is that the +30 V power supply voltage has dropped to +9 V.
However, the voltage value used here is an example,
Other values may be used.

Although the monitoring range is narrowed, the monitoring voltage of the first voltage monitoring circuit and the second voltage monitoring circuit is +
It is also possible to use a 5V power supply voltage. Also in that case, the detection voltage of the first voltage monitoring circuit is set higher than the detection voltage of the second voltage monitoring circuit.

While power is not supplied from the +5 V power supply, which is the driving power supply of the CPU 56, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board, and the contents are maintained even if the power supply to the gaming machine is cut off. Is saved. Then, when the +5 V power supply is restored, a reset signal is issued from the initial reset circuit 65, and the CPU 56 returns to the normal operation state. At that time, since the necessary data is backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

In FIG. 12, when the power is turned on, the CPU 5
6 shows a configuration in which a reset signal (low-level signal) is applied twice to the reset terminal. However, in the case of using a CPU in which reset is surely released even if the reset signal rises only once, , Reference numerals 941 to 9
The circuit element indicated by 49 is unnecessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

Next, the operation of the gaming machine will be described. FIG.
3 is a flowchart showing a main process executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56
First, it is confirmed whether or not it is time to recover from a power failure (step S1). Whether or not recovery from a power failure has occurred is confirmed by, for example, a power-off flag set in the backup RAM area when the power is turned off.

If it is time to recover from a power failure, a data check (parity check in this example) of the backup RAM area is performed (step S3). If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power failure, an initialization process executed at the time of power-on without power recovery is executed (steps S4 and S2).

If the check result is normal, the CPU 56
Performs the game state restoring process for returning the internal state to the state at the time of power-off (step S5), and clears the power-off flag (step S6).

If it is not at the time of recovery from the power failure, the CPU
56 executes a normal initialization process (step S1,
S2). Thereafter, in the main process, the process shifts to a loop process in which the monitoring of the timer interrupt flag (step S6) is confirmed. In the loop, a display random number update process (step S7) is also executed.

Here, in step S1, it is confirmed whether or not the power is restored from the power failure. If the power is restored from the power failure, the parity check is performed. First, the parity check is executed, and the check result is normal. Otherwise, it is determined that it is not the recovery from the power failure, and the initialization processing of step S2 is executed, and if the check result is normal, the game state return processing may be performed. That is, it may be determined based on the result of the parity check whether recovery from a power failure has occurred.

Further, when determining whether or not to execute the power failure recovery process, that is, when determining whether or not to recover the gaming state, a special process flag or the like in the stored RAM data and the number of start winning prizes are stored. According to the data, the gaming machine is in the game waiting state (the symbol is not changing, the jackpot is not playing, the probability is not changing, and there is no start winning memory)
When it is confirmed that the game state is restored, the initialization processing may be executed without performing the game state restoration processing.

In the normal initialization process, as shown in FIG. 14, the register and RAM are cleared (step S2).
a) and the initial setting (timeout is 2 ms) of the timer register provided in the CPU 56 so that the timer is periodically interrupted every 2 ms after the necessary initial value setting processing (step S2b) is performed. And a setting for operating the repetition timer) is performed (step S2c). That is, in step S2c, a process of activating a timer interrupt and a process of setting a timer interrupt interval are executed.

Therefore, in this embodiment, the CPU 56
Is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2 ms
Is set to Then, as shown in FIG. 15, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S11).

When detecting that the timer interrupt flag is set in step S8, the CPU 56 resets the timer interrupt flag (step S8).
9), a game control process is executed (step S10). According to the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process.
The game control process may be executed by a timer interrupt process.

FIG. 16 is a flowchart showing the game control processing in step S10. In the game control process,
The CPU 56 first performs processing for setting a display control command sent to the display control board 80 in a predetermined area of the RAM 55 (display control data setting processing: step S
21), a process of outputting a display control command is performed (display control data output process: step S22).

Next, processing for outputting the contents of the storage area for various output data to each output port is performed (data output processing: step S23). Further, an output data setting process for setting output data such as big hit information, start information, and probability variation information output to the hall management computer in the storage area is performed (step S24). Further, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S25).

Next, a process of updating each counter indicating a random number for determination such as a random number for big hit determination used in game control is performed (step S26).

Further, the CPU 56 performs a special symbol process (step S27). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S28). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

Further, the CPU 56 includes a switch circuit 58
, The state of the gate sensor 12, the starting port sensor 17, the count sensor 23, and the winning port switches 19a and 24a are input, and it is determined whether or not each of the winning ports and the winning device has a winning (switch processing: step S29). .
The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S3).
0).

The CPU 56 performs signal processing with the payout control board 37 (step S31). That is,
When a predetermined condition is satisfied, a prize ball control command is output to the payout control board 37. The payout control CPU mounted on the payout control board 37 drives the ball payout device 97 according to the prize ball control command.

As described above, the main processing includes the processing for determining whether or not to shift to the game control processing.
Since a flag is set to determine whether or not to shift to the game control process in the timer interrupt process based on the timer interrupt that is periodically generated by the 56 internal timers, all the game control processes are reliably executed. Is done. In other words, until all of the game control processes have been executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process will be completed. ing.

In the conventional general game control process, the game machine is forcibly returned to the initial state by an external interrupt that occurs periodically. Explaining with reference to the example shown in FIG. 16, for example, even during the process of step S31, the process is forcibly returned to the process of step S21. In other words, there is a possibility that the next game control process will be started before all the processes in the game control process are completed.

Here, the CPU 56 of the main board 31
Is executed in response to a flag set in a timer interrupt process based on a timer interrupt that is periodically generated by an internal timer of the CPU 56, but the signal is periodically (for example, every 2 ms). A hardware circuit which generates the signal may be provided, a signal from the circuit may be introduced to an external interrupt terminal of the CPU 56, and a flag for determining whether or not to shift to the game control process based on the interrupt signal may be set. Good.

Even in such a configuration, the flag is not determined until all the game control processes have been executed, so that it is guaranteed that all the processes in the game control process are completed. You.

FIG. 17 is a flowchart showing an example of a power failure occurrence NMI process executed in response to an NMI based on a voltage drop signal from the first power supply monitoring circuit of the power supply board 910. In the power failure occurrence NMI process, the CPU 56
Sets interrupt prohibition first (step S41). In the power failure occurrence NMI process, a checksum generation process is performed to ensure that the contents of the RAM are preserved. If another interrupt process is performed during that process, the voltage may drop to a level at which the CPU cannot operate before the checksum generation process is completed. The setting is made so that no interrupt occurs. In addition, the power failure occurrence NM
Steps S43 to S49 in the I process are an example of a process at the time of stopping power supply.

If a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the processing in step S41 is unnecessary.

Next, the CPU 56 checks whether or not the power-off flag has already been set (step S4).
2). If the power-off flag has already been set, no further processing is performed. If the power-off flag is not set, the following power supply stop processing is executed. That is,
The processing from step S43 to step S49 is executed.

First, the contents of each register are backed up R
It is stored in the AM area (step S43). Further, an appropriate initial value is set in the backup check data area of the backup RAM area (step S44), and exclusive OR is sequentially performed on the initial value and the data of the backup RAM area (step S45) to obtain a final operation value. Is set in the backup parity data area (step S46). Thereafter, the power-off flag is set (step S47). Further, the RAM access is prohibited (step S48). When the power supply voltage decreases, the levels of various signal lines may become unstable and the contents of the RAM may be corrupted. However, if the RAM access is prohibited in this manner, the data in the backup RAM may be corrupted. There is no. Then, all the output ports are turned off (step S49).

Next, the CPU 56 enters a loop process. That is, no processing is performed. Therefore, before the operation is disabled from the outside by the reset signal from the reset IC 651 shown in FIG. 12, the operation is internally stopped. Therefore, when the power is turned off, the operation of the CPU 56 is reliably stopped. As a result, the RAM
The access prohibition control and the operation stop control can reliably prevent the contents of the RAM from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases.

In this embodiment, the power failure occurrence NM
In I processing, the program was looped in the last part,
It may be configured to issue a HALT instruction.

The power-off flag set before the RAM access is prohibited is used to determine whether or not recovery from a power failure has occurred at power-on, as described above. Further, the processing of steps S41 to S49 is completed before the second power supply monitoring unit generates the voltage drop signal.
In other words, the detection voltages of the first voltage monitoring means and the second voltage monitoring means are set so that the detection is completed before the second power supply monitoring means generates the voltage drop signal.

In this embodiment, the power-off flag is checked at the start of the power-supply-stop processing. If the power-off flag has already been set, the power supply stop processing is not executed. As described above, the power-off flag is a flag indicating that the power-supply-stop processing has been completed. Therefore, for example, even if the NMI occurs again for some reason in the reset waiting loop state, the power supply stop processing will not be repeatedly executed.

However, if a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the determination in step S42 is unnecessary.

FIG. 18 is an explanatory diagram for explaining a backup parity data creating method. However, FIG.
In the example shown in FIG.
The size of the data in the M area is 3 bytes. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 18A, initial data (00H in this example) is set in the backup check data area. Next, "00
The exclusive OR of “H” and “F0H” is calculated, and the result is exclusive ORed with “16H”. Further, an exclusive OR of the result and “DFH” is obtained. Then, the result (“39H” in this example) is set in the backup parity data area.

When the power is turned on again, the parity diagnosis is performed in the power failure recovery process. FIG. 18B is an explanatory diagram showing an example of the parity diagnosis. If all the data in the backup area is stored as it is, the data as shown in FIG. 18A is set in the backup area when the power is turned on again.

In the process of step S51, the CPU 5
6 is the data set in the backup parity data area of the backup RAM area (in this example, “39”).
H)) as initial data, a process of sequentially taking an exclusive OR for each data in the backup data area is performed.
If all the data in the backup area is stored as it is, the final calculation result is “00H”, that is, the same as the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result is “00”.
H ".

Therefore, the CPU 56 compares the final operation result with the data set in the backup check data area, and if they match, determines that the parity diagnosis is normal. If they do not match, it is determined that the parity diagnosis is abnormal.

As described above, in this embodiment, the game control means is provided with the storage means (backup RAM in this example) which is backed up for a predetermined period of time even if the power of the game machine is turned off. At the time of insertion, the CPU 56 (specifically, a program executed by the CPU 56) is configured to perform a game state restoration process (step S5) for restoring the game state based on the backup data if the storage means is in the backup state. .

In this embodiment, the first power supply monitoring means is mounted on the power supply board 910 as shown in FIG. 9, and the second power supply monitoring means is mounted on the main board 31 as shown in FIG. It is installed. Then, when the power supply voltage decreases, the second power supply monitoring means (the reset IC 6 in this example)
51) generates a voltage drop signal (system reset signal) such that the first power supply monitoring means (the power supply monitoring IC 902 in this example) generates a voltage drop signal later. .

Then, the CPU 56 enters the loop state after executing the power failure generation processing (power supply stop processing) based on the voltage drop signal from the first power supply monitoring means (power supply monitoring IC 902). In a loop state, a reset state is entered. That is, CPU
The operation at 56 stops completely. + In loop state
Since the 5V power supply voltage value gradually decreases, the input / output state becomes unstable. However, since the CPU 56 is in the reset state, abnormal operation based on the unstable data is prevented.

As described above, in this embodiment, the CPU
56 is configured so as to enter a loop state in response to the input of the detection output from the first power supply monitoring means and to be system reset in response to the input of the detection output from the second power supply monitoring means. It is possible to reliably store data at the time of disconnection, and prevent disadvantages from being brought to the player.

Although the first and second power supply monitoring circuits monitor the same power supply voltage in this embodiment, they may monitor different power supply voltages. For example, the first power supply monitoring circuit of the power supply board 910 monitors the + 30V power supply voltage, and the second power supply monitoring circuit of the main
The 5V power supply voltage may be monitored. Then, the second power supply monitoring circuit generates the low-level voltage drop signal at a timing later than the timing at which the first power supply monitoring circuit generates the voltage drop signal, so that the second power supply The threshold level (voltage level at which a voltage drop signal is generated) of the monitoring circuit is set. For example, the threshold is 4.2
5V. 4.25V is lower than the normal voltage,
The voltage is such that the CPU 56 can operate for a while.

In the above embodiment, the CPU 56
Detected the first voltage drop signal from the power supply board (voltage drop signal from the first power supply monitoring means) via the non-maskable interrupt terminal (NMI terminal), but masked the first voltage drop signal. A possible interrupt may be introduced to an interrupt terminal (IRQ terminal). In that case, the power supply stop processing is executed in the interrupt processing (IRQ processing).

FIG. 19 is a block diagram showing a more detailed circuit configuration example of the audio control board 70. As shown in FIG. 19, in this embodiment, DC 12 V and DC 5 V are supplied to the audio control board 70 from the power supply board 910.

The DC 12V from the power supply board 910 becomes VDD (+ 12V power supply) via the noise filter 711. VDD is also supplied to a three-terminal regulator 712. The three-terminal regulator 712 operates from + 12V to +
Create a 5V voltage (AVcc). AVcc is analog +
5V power supply.

In the configuration shown in FIG. 19, the audio control CPU
701 receives a voice control command via an input buffer 705A in response to an interrupt signal (INT signal) input via a buffer circuit 705B. Then, information for designating a predetermined voice pattern in accordance with the voice control command is stored in a voice synthesis circuit (voice synthesis LS).
I) Output to 702. In this example, for information transmission, the SCLK signal, SI signal, SIRQ signal, SRDY
The signal and the SIAK signal are used. The SCLK signal, the SI signal, the SIRQ signal, and the SRDY signal are transmitted from the voice control CPU 701 to the voice synthesis circuit 70 through the transistor circuits 721, 722, 723, 724, and 725.
2 is transmitted. The transistor circuits 722 and 72
3, 724, and 725, the transistor circuit 721
The configuration is the same as The SIAK signal is transmitted from the voice synthesis circuit 702 to the voice control CPU 701 via the transistor circuit 726. Note that the configuration of the transistor circuit 726 is the same as the configuration of the transistor circuit 721, but the signal input / output directions are reversed.

The voice synthesis circuit 702 has a voice control CPU.
When information is input from 701, according to the input information,
It reads out pattern data stored in a ROM (not shown) and outputs an audio signal.

Transistor circuits 721, 722, 72
3, 724, 725, and 726 play a role of a power supply conversion circuit. That is, the voice control CPU 701 determines that Vcc
(Digital +5 V), but the voice synthesis circuit 702 is driven by AVcc (analog +5 V). Therefore, the voice control CPU 701 and the voice synthesis circuit 7
Signals exchanged with the device 02 are converted into signals driven by AVcc by the transistor circuits 721, 722, 723, 724, 725, and 726.

The audio signal from the audio synthesizing circuit 702 is adjusted in level by the volume switching circuit 703,
The signal is supplied to the speaker 27 via the terminals 04A and 705B.

In this embodiment, the analog + 5V is
In the voice control board 70, the potential is higher than that +
It is created from a 12V power supply. That is, analog +5 V is generated from a power supply capable of supplying a higher voltage. In addition, DC5V for driving each digital IC is different from + 5V used in the analog processing system. Therefore, even if a relatively large current flows when the speaker 27 is driven and the +5 V used in the analog processing system fluctuates, the influence is not transmitted to each digital IC via the power supply.

FIG. 20 is a block diagram showing a more detailed configuration example of the display control board 80. As shown in FIG. As shown in FIG.
In this embodiment, DC 12 V and DC 5 V are supplied to the display control board 80 from the power supply board 910.

The DC 12 V from the power supply board 910 becomes VDD (+12 V power supply) via the noise filter 711. VDD is also supplied to a three-terminal regulator 712. The three-terminal regulator 712 operates from + 12V to +
Create a 5V voltage (AVcc). AVcc is analog +
5V power supply.

In the configuration shown in FIG. 20, the display control CPU
101 receives a display control command via an input buffer 105A in response to an interrupt signal (INT signal) input via a buffer circuit 105B. Display control CPU1
01 is the VDP 10 according to the received display control command.
The information for display control is output to 3. VDP103
Is a ROM (not shown), if necessary, according to the information.
Of the image data to be displayed on the variable display unit, and a synchronizing signal. Although one VDP 103 is provided in this example, a plurality of VDPs may be used.

The R, G, and B signals from the VDP 103 are supplied to a liquid crystal display device that implements a variable display section via transistor circuits 121, 122, and 123 and noise filters 131, 132, and 133. VDP10
3 is also supplied to the liquid crystal display device.

Transistor circuits 121, 122, 123
Performs an amplifying function and plays a role of a power conversion circuit. That is, the R, G, B signals from the VDP 103 are converted into signals driven by AVcc by the transistor circuits 121, 122, 123.

In this embodiment, the analog + 5V is
In the display control board 80, the potential +
Analog + 5V is created from a 12V power supply. That is, analog +5 V is generated from a power supply capable of supplying a higher voltage. In addition, each digital I
DC 5 V for driving C and +5 V used in the analog processing system are separate systems. Therefore, even if the + 5V used in the analog processing system fluctuates,
The influence is not transmitted to each digital IC via the power supply. Further, even if noise is added to a circuit for driving an analog component such as a variable display unit, there is no possibility that the noise will be transmitted to the digital IC circuit via the power supply.

In the above embodiment, in the audio control board 70 and the display control board 80, the voltage (+5 in this example) for driving each digital IC on the board is used.
V), the analog processing system voltage generating means for generating a power supply voltage used in the analog processing system from a voltage (+12 V in this example) is exemplified. Creation means may be provided. Further, although the three-terminal regulator has been exemplified as the analog processing system voltage generating means, the analog processing system voltage generating means can be realized by using another circuit configuration.

In the above embodiment, the power supply voltage used in the analog processing system is created from the DC voltage.
A power supply voltage used in the analog processing system may be created from the AC voltage. In that case, for example, the power supply board 910
After rectifying 24V AC supplied from the power supply, a regulator generates a power supply voltage used in an analog processing system of a desired voltage.

As shown in FIG. 9, a power supply monitoring IC 90 constituting a first power supply monitoring means is provided on a power supply board 910.
2 is mounted. The first power supply monitoring means is not related to the game control inherent in the gaming machine, but is a means for performing processing for saving data when the power is turned off. If such additional means is mounted on the power supply board 910, as shown in FIG. 9, a control signal (a voltage drop signal in this example)
Can be supplied to any electric component control board. That is, one first power supply monitoring means may be provided regardless of how many boards need a control signal. As a result, an increase in the cost of the gaming machine can be suppressed.

The means that can be mounted on the power supply board 910 is not limited to the power supply monitoring means.
10 may be mounted. For example, as shown in FIG.
A setting switch 931 may be mounted. Setting switch 9
Reference numeral 31 denotes, for example, a switch for the game control means to set the player's advantage. For example, in a pachinko game machine, it is used to set a jackpot probability. If the setting switch 931 is mounted on the power supply board 910, the main board 31
It is not necessary to provide a switch for the switch, and the switch setting can be easily changed without operating the main board 31 generally covered with the cover.

Further, as shown in FIG.
A reset switch 932 may be mounted at 0. The output of the reset switch 932 is sent to the electric component control board. For example, when temporary ball clogging occurs in the ball dispensing device 97, the game store clerk can release the device and press the reset switch 932 to restore the dispensing control. If the reset switch 932 is mounted on the power supply board 910, there is no need to provide a switch on the payout control board 37 or the like, and the switch setting can be easily changed without operating the payout control board 37 or the like generally covered with a cover. Can be. Also, a reset signal can be supplied to a plurality of electrical component control boards from one location.

FIG. 22 also shows a switch 933. When the switch 933 is turned off, no AC power (for example, 24 V AC) is supplied to the power supply board 910, so that the gaming machine enters a power supply cutoff state. When the switch 933 is turned on, AC power (for example, 24 V AC) is supplied to the power supply board 910.
The gaming machine enters a power supply enabled state. That is, the switch 933 can be used as a power switch.

Further, the reset switch 932 can be used as a reset switch for clearing the backup RAM. For example, the output of the reset switch 932 is supplied to an electric component control board having a backup RAM. The program executed by the CPU mounted on the electric component control board is configured to clear the backup RAM area when the reset switch 932 is turned on in the initialization processing. Therefore, for example, if the switch 933 is switched from the OFF state to the ON state in a state where the power can be supplied to 24 V AC, the power supply is started, and at that time, the reset switch 932 is pressed,
Even when data is stored in the backup RAM, the contents can be cleared. If the power supply is started in a state where the reset switch is not pressed, the backup RAM is not cleared.

The switch 933 is connected to the backup RA
It may be used as a switch for determining whether or not to perform the M clearing process. For example, when the switch 933 is switched from the on state to the off state in a state where power is supplied to the game machine from the outside, the electric component control means of the electric component control board having the backup RAM performs a clearing process of the backup RAM. Do. Also, switch 933
When the power supply to the gaming machine is cut off while the power supply is turned on, the power-off processing (the power supply stop processing) described above is performed to perform the data storage processing of the backup RAM. In this case, the output of the switch 933 is
Introduced into the electrical component control means.

As described above, in each of the above embodiments,
Since the power supply board 910 is provided with means for realizing various additional functions, it provides convenient functions without supplying signals to the respective electric component control boards and operating the electric component control boards. it can. As a result, various additional functions can be realized without increasing the cost of the gaming machine.

The board configuration (main board 31, lamp control board 35, payout control board 3) in each of the above embodiments is described.
7, the voice control board 70, the display control board 80, and the launch control board 91), ie, the configuration of each control means is an example, and the present invention is applicable even if another configuration according to the form of the gaming machine is adopted. Can be applied.

Further, in the above-described embodiment, a gaming machine in which game balls are paid out according to a prize is taken as an example. The present invention can be applied to a gaming machine that adds points.

[0149]

As described above, according to the present invention, a gaming machine is provided with an electrical component control board mounted with electrical component control means for performing processing for controlling electrical components provided in the gaming machine, and an electrical component. A power supply board for creating a voltage used in the gaming machine, which is different from the control board, and the power supply board affects a process performed by an electric component control unit in addition to a circuit for creating a voltage. Since the components are mounted, there is an effect that additional functions in the gaming machine can be realized without increasing the cost.

An element which influences the processing performed by the electric component control means monitors a predetermined potential power supply used in the gaming machine and outputs a detection signal to the electric component control means when the first detection condition is satisfied. In the case of the first power supply monitoring means, the timing at which such control is to be performed can be easily recognized in a gaming machine configured to perform control according to the power supply condition.

In the case where the electric component control means is configured to perform predetermined power supply stop processing based on a detection signal from the first power supply monitoring means, processing for storing data necessary for recovery of the game state, etc. It is possible to reliably start the processing that is preferably performed when the power supply is stopped.

When the electric component control means is configured to reset the system in response to the input of the detection signal from the second power supply monitoring means, an unstable period when the power supply voltage decreases is provided. Since the system reset is performed, the operation of the electric component control means can be stopped after the electric component control means has completed the predetermined power supply stop processing, so that data is not destroyed when the power supply voltage drops. Can be.

The first power supply monitoring means and the second power supply monitoring means monitor the voltage of the same predetermined potential power supply, and the voltage of the predetermined potential power supply at which the second power supply monitoring means outputs a detection signal is When the first power supply monitoring means is configured to be lower than the voltage at which the detection signal is output, the first power supply monitoring means monitors the same power supply voltage. The predetermined period, which is the difference between the output timing and the timing at which the second voltage monitoring means outputs the voltage drop signal, can be reliably set to a desired value.

In the case where the power supply stop processing includes a processing for storing data that allows control to be restarted when power supply is restarted in the storage means capable of holding the contents immediately before the power supply is stopped. In this configuration, a configuration in which data necessary for the recovery of the game state is securely stored and control is resumed when the power is restored is realized at low cost.

When the detection signal from the first power supply monitoring means is output to the plurality of electric component control means, and the first detection condition is configured to be the same for the plurality of electric component control means, the voltage may be reduced. No matter how many electrical component control means need a detection output indicating a drop, the first power supply monitoring means is one.
Since it is only necessary to provide one, the cost of the gaming machine does not increase so much even if each electric component control means performs the power return control. Further, output control of a detection output indicating a voltage drop is easy.

The electric component control means includes a microcomputer, and the second power supply monitoring means for outputting a detection signal for resetting the microcomputer is provided on an electric component control board on which the microcomputer is mounted. In this case, control for generating a detection output at a timing suitable for each electric component control means can be easily realized.

When the element that influences the processing performed by the electric component control means is a power switch for switching between supplying and shutting off power, power is cut off or turned on by operating only the power supply board. It is possible,
For example, in a game arcade, there is an effect that processing for a game clerk to recover from a failure is facilitated.

When the factor affecting the processing performed by the electric component control means is a reset switch for clearing the storage contents of the storage means, the reset operation can be performed by operating only the power supply board. Therefore, it is possible to easily perform the clearing process of the storage unit backed up by the power supply.

Since a plurality of types of voltages are generally used in a game machine, it is preferable that a circuit for generating a plurality of types of voltages is mounted on the power supply board, but a microcomputer is not mounted on the power supply board. So
The microcomputer is not affected by noise that tends to occur in a circuit that generates a plurality of types of voltages.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is an explanatory view showing each board arranged on the back surface of the pachinko gaming machine.

FIG. 3 is a rear view of the mechanical plate of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram illustrating an example of a circuit configuration on a main board.

FIG. 5 is a block diagram showing a signal transmission / reception portion of the main board and the lamp control board.

FIG. 6 is a block diagram illustrating a signal transmission / reception portion of the main board and the voice control board.

FIG. 7 is a block diagram showing components related to a prize ball, such as components of a payout control board and a ball payout device.

FIG. 8 is a block diagram illustrating a signal transmission / reception portion of the main board and the emission control board.

FIG. 9 is a block diagram illustrating a configuration example of a power supply board.

FIG. 10 is a block diagram showing a flow of a main signal between respective substrates and a state of DC power supply.

FIG. 11 is a block diagram illustrating a DC voltage supplied from a power supply substrate to each substrate.

FIG. 12 is a block diagram illustrating a configuration example around a CPU for power supply monitoring and power supply backup.

FIG. 13 is a flowchart showing a main process executed by a CPU on a main board.

FIG. 14 is a flowchart illustrating initialization processing.

FIG. 15 is a flowchart showing a 2 ms timer interrupt process.

FIG. 16 is a flowchart showing a game control process.

FIG. 17 is a flowchart showing a power failure occurrence NMI process.

FIG. 18 is an explanatory diagram for describing a backup parity data creation method.

FIG. 19 is a block diagram illustrating a more detailed circuit configuration example of the audio control board.

FIG. 20 is a block diagram illustrating a more detailed configuration example of a display control board.

FIG. 21 is a block diagram showing another configuration example of the power supply board.

FIG. 22 is a block diagram showing still another configuration example of the power supply board.

[Explanation of symbols]

 31 game control board (main board) 35 lamp control board 37 payout control board 53 basic circuit 70 audio control board 80 display control board 91 launch control board 902 power monitoring IC 910 power board 931 setting switch 932 reset switch 933 switch

Claims (11)

[Claims] 1. A game machine having a game area provided on a game board and providing a predetermined value to a player in accordance with a prize of a game ball in a prize area provided in the game area, An electric component control board mounted with an electric component control means for performing processing for controlling an electric component provided in the machine; and a board different from the electric component control board to create a voltage used in the gaming machine. A gaming machine, comprising: a power supply board, wherein the power supply board is provided with, in addition to a circuit for generating a voltage, an element that influences processing performed by the electric component control means. 2. An element influencing the processing performed by the electric component control means is to monitor a predetermined potential power supply used in the gaming machine and to output a detection signal to the electric component control means when the first detection condition is satisfied. The gaming machine according to claim 1, wherein the gaming machine is a first power supply monitoring unit that outputs the power. 3. The gaming machine according to claim 2, wherein the electric component control means performs predetermined power supply stop processing based on a detection signal from the first power supply monitoring means. 4. A potential power supply which is the same as or different from the predetermined potential power supply monitored by the first power supply monitoring means, and
A second power supply monitor that outputs a detection signal when a second detection condition set to be satisfied at least after execution of the power supply stop processing is completed after the first detection condition is satisfied by the power supply monitoring unit. 4. The system according to claim 3, further comprising: means for resetting the electric component control means in response to a detection signal input from the second power supply monitoring means.
The gaming machine described. 5. The first power supply monitoring means and the second power supply monitoring means monitor the voltage of the same predetermined potential power supply, and the second power supply monitoring means outputs a detection signal. 5. The gaming machine according to claim 4, wherein the voltage is lower than a voltage at which the first power supply monitoring means outputs a detection signal. 6. The process at the time of power supply stop includes a process of storing data capable of resuming control when power supply is restarted in a storage unit capable of holding contents immediately before power supply stop. The gaming machine according to claim 3. 7. A plurality of electric component control means are provided, a detection signal from the first power supply monitoring means is output to a plurality of the plurality of electric component control means, and the first detection condition is 7. The gaming machine according to claim 2, wherein the plurality of electric component control means are the same. 8. The electric component control means includes a microcomputer, and the second power supply monitoring means for outputting a detection signal for resetting the microcomputer is provided on an electric component control board on which the microcomputer is mounted. The gaming machine according to claim 4, wherein 9. The gaming machine according to claim 1, wherein the element affecting the processing performed by the electric component control means is a power switch for switching between supplying and shutting off power. 10. The reset switch for clearing the storage contents of the storage means capable of holding the contents immediately before the stop of the power supply, wherein the element which influences the processing performed by the electric component control means. The gaming machine according to claim 9. 11. The gaming machine according to claim 1, wherein the microcomputer is not mounted on the power supply board.