JP2001345381A - 半導体集積回路装置の製造方法 - Google Patents

半導体集積回路装置の製造方法

Info

Publication number
JP2001345381A
JP2001345381A JP2000165781A JP2000165781A JP2001345381A JP 2001345381 A JP2001345381 A JP 2001345381A JP 2000165781 A JP2000165781 A JP 2000165781A JP 2000165781 A JP2000165781 A JP 2000165781A JP 2001345381 A JP2001345381 A JP 2001345381A
Authority
JP
Japan
Prior art keywords
insulating film
forming
film
wiring
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000165781A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001345381A5 (https=
Inventor
Katsuhiro Torii
克裕 鳥居
Takeshi Fujiwara
剛 藤原
Kazutoshi Omori
一稔 大森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000165781A priority Critical patent/JP2001345381A/ja
Publication of JP2001345381A publication Critical patent/JP2001345381A/ja
Publication of JP2001345381A5 publication Critical patent/JP2001345381A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP2000165781A 2000-06-02 2000-06-02 半導体集積回路装置の製造方法 Pending JP2001345381A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000165781A JP2001345381A (ja) 2000-06-02 2000-06-02 半導体集積回路装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000165781A JP2001345381A (ja) 2000-06-02 2000-06-02 半導体集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
JP2001345381A true JP2001345381A (ja) 2001-12-14
JP2001345381A5 JP2001345381A5 (https=) 2005-01-13

Family

ID=18669205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000165781A Pending JP2001345381A (ja) 2000-06-02 2000-06-02 半導体集積回路装置の製造方法

Country Status (1)

Country Link
JP (1) JP2001345381A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004241568A (ja) * 2003-02-05 2004-08-26 Tokyo Electron Ltd 基板脱着装置、基板脱着方法及び基板処理システム
JP2015228522A (ja) * 2015-09-02 2015-12-17 ルネサスエレクトロニクス株式会社 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004241568A (ja) * 2003-02-05 2004-08-26 Tokyo Electron Ltd 基板脱着装置、基板脱着方法及び基板処理システム
JP2015228522A (ja) * 2015-09-02 2015-12-17 ルネサスエレクトロニクス株式会社 半導体装置

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