JP2001267363A - Piezoelectric device and manufacturing method for the same - Google Patents
Piezoelectric device and manufacturing method for the sameInfo
- Publication number
- JP2001267363A JP2001267363A JP2000070668A JP2000070668A JP2001267363A JP 2001267363 A JP2001267363 A JP 2001267363A JP 2000070668 A JP2000070668 A JP 2000070668A JP 2000070668 A JP2000070668 A JP 2000070668A JP 2001267363 A JP2001267363 A JP 2001267363A
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- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- package
- piezoelectric device
- piezoelectric
- Prior art date
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2924/01—Chemical elements
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- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体集積回路と
圧電振動子とをパッケージに内蔵した圧電デバイス及び
その製造方法に関する。The present invention relates to a piezoelectric device having a semiconductor integrated circuit and a piezoelectric vibrator built in a package, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】近年、ＨＤＤ（ハード・ディスク・ドラ
イブ）、モバイルコンピュータ、あるいはＩＣカード等
の小型の情報機器や、携帯電話や自動車電話等の移動体
通信機器において装置の小型薄型化がめざましく、それ
らに用いられる圧電発振器や電圧制御発振器（ＶＣＸ
Ｏ）や温度補償発振器（ＴＣＸＯ）やＳＡＷ発振器、あ
るいはリアルタイムクロックモジュール等の圧電デバイ
スも小型薄型化が要求されている。又、それとともに、
装置の回路基板に両面実装が可能な表面実装タイプの圧
電デバイスが求められている。2. Description of the Related Art In recent years, devices such as HDDs (hard disk drives), mobile computers, and small information devices such as IC cards, and mobile communication devices such as mobile phones and car phones have been remarkably reduced in size and thickness. Piezoelectric oscillators and voltage-controlled oscillators (VCX
O), a temperature-compensated oscillator (TCXO), a SAW oscillator, and a piezoelectric device such as a real-time clock module are also required to be small and thin. In addition,
There is a need for a surface mount type piezoelectric device that can be mounted on both sides of a circuit board of an apparatus.
【０００３】そこで、従来の圧電デバイスの一例を、発
振回路を有するワンチップの半導体集積回路と、圧電振
動子にＡＴカット水晶振動子とを用いた図６（ａ）、６
（ｂ）の構造図で示される水晶発振器を用いて説明す
る。Therefore, an example of a conventional piezoelectric device is shown in FIGS. 1A and 1B using a one-chip semiconductor integrated circuit having an oscillation circuit and an AT-cut quartz oscillator as a piezoelectric oscillator.
Description will be made using the crystal oscillator shown in the structural diagram of FIG.
【０００４】図６（ａ）、６（ｂ）の従来の水晶発振器
の構成において、発振回路を有するＩＣチップ１０１
は、セラミック絶縁基板で形成されたベース１０２の底
面に導電性接着剤等により接着固定され、Ａｕワイヤー
ボンディング線１０３により、ベース１０２の底面外周
部にＷ（タングステン）あるいはＭｏ（モリブデン）等
の金属でメタライズされ、Ｎｉ＋Ａｕメッキされた入出
力用電極１０４等に電気的に接続されている。In the configuration of the conventional crystal oscillator shown in FIGS. 6A and 6B, an IC chip 101 having an oscillation circuit is provided.
Is bonded and fixed to the bottom surface of the base 102 formed of a ceramic insulating substrate by a conductive adhesive or the like, and a metal such as W (tungsten) or Mo (molybdenum) is formed on an outer peripheral portion of the bottom surface of the base 102 by an Au wire bonding wire 103. , And are electrically connected to the Ni + Au-plated input / output electrode 104 and the like.
【０００５】又、矩形タイプのＡＴカット水晶振動子１
０５が、ベース１０２のマウント部１０６に導電性接着
剤等で電気的に接続され固定されている。そして、Ｎ2
（窒素）雰囲気あるいは真空雰囲気に内部を保ち、ベー
ス１０２の最上部のシールリング１０７と、金属製のリ
ッド１０８とをシーム溶接により接合し気密に封止して
いる。[0005] A rectangular type AT-cut quartz resonator 1
Reference numeral 05 is electrically connected to and fixed to the mount portion 106 of the base 102 with a conductive adhesive or the like. And N 2
While maintaining the inside in a (nitrogen) atmosphere or a vacuum atmosphere, the seal ring 107 at the top of the base 102 and the metal lid 108 are joined by seam welding to hermetically seal them.
【０００６】[0006]
【発明が解決しようとする課題】以上に示す従来の水晶
発振器は、ＩＣチップ１０１の周囲にＡｕワイヤーボン
ディング線１０３を配線するエリアが必要であること。
又、パッケージの厚み方向でも、Ａｕワイヤーボンディ
ング線１０３のループ高さの確保や、Ａｕワイヤーボン
ディング線１０３とＡＴカット水晶振動子１０５との隙
間の確保が必要であること等、この構成が水晶発振器を
小型薄型にするための制約となっている。The above-described conventional crystal oscillator requires an area around the IC chip 101 for wiring the Au wire bonding wire 103.
In addition, in the thickness direction of the package, the crystal oscillator is required to secure the loop height of the Au wire bonding wire 103 and to secure a gap between the Au wire bonding wire 103 and the AT-cut crystal oscillator 105. Are small and thin.
【０００７】本発明の目的は、以上の従来技術の課題を
解決するためになされたものであり、その目的とすると
ころは小型薄型サイズで厚み１ｍｍ以下の水晶発振器等
の圧電デバイスを安価に提供することである。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art. It is an object of the present invention to provide a small and thin piezoelectric device such as a crystal oscillator having a thickness of 1 mm or less at a low cost. It is to be.
【０００８】[0008]
【課題を解決するための手段】請求項１記載の発明は、
半導体集積回路と圧電振動子とを配線基板で形成された
パッケージに内蔵した圧電デバイスにおいて、半導体集
積回路はパッケージの電極パターンと複数のバンプによ
り接合されてなり、電極パターンとバンプの接合部に応
力緩和作用を有する導電性接着剤を用いたことを特徴と
する。According to the first aspect of the present invention,
In a piezoelectric device in which a semiconductor integrated circuit and a piezoelectric vibrator are built in a package formed of a wiring board, the semiconductor integrated circuit is bonded to the electrode pattern of the package and a plurality of bumps. It is characterized by using a conductive adhesive having a relaxing effect.
【０００９】請求項２記載の発明は、請求項１におい
て、半導体集積回路と圧電振動子とを配線基板で形成さ
れたパッケージに内蔵した圧電デバイスにおいて、半導
体集積回路は樹脂接着剤で配線基板に接合されてなり、
電極パターンとバンプの接合部に応力緩和作用を有する
導電性接着剤を用いたことを特徴とする。According to a second aspect of the present invention, in the piezoelectric device according to the first aspect, the semiconductor integrated circuit and the piezoelectric vibrator are incorporated in a package formed of a wiring board. Become joined,
The present invention is characterized in that a conductive adhesive having a stress relaxing action is used at the joint between the electrode pattern and the bump.
【００１０】請求項３記載の発明は、請求項１におい
て、半導体集積回路と圧電振動子とを配線基板で形成さ
れたパッケージに内蔵した圧電デバイスにおいて、導電
性接着剤がシリコン系の導電性接着剤であることを特徴
とする。According to a third aspect of the present invention, in the piezoelectric device according to the first aspect, the semiconductor integrated circuit and the piezoelectric vibrator are built in a package formed of a wiring board, and the conductive adhesive is a silicon-based conductive adhesive. It is characterized by being an agent.
【００１１】請求項４記載の発明は、請求項２におい
て、半導体集積回路と圧電振動子とを配線基板で形成さ
れたパッケージに内蔵した圧電デバイスにおいて、樹脂
接着剤が半導体集積回路の裏面に塗布されており、樹脂
接着剤が圧電振動子の先端を保持していることを特徴と
する。According to a fourth aspect of the present invention, in the piezoelectric device according to the second aspect, wherein the semiconductor integrated circuit and the piezoelectric vibrator are incorporated in a package formed of a wiring substrate, a resin adhesive is applied to the back surface of the semiconductor integrated circuit. And the resin adhesive holds the tip of the piezoelectric vibrator.
【００１２】請求項５記載の発明は、半導体集積回路と
圧電振動子とを配線基板で形成されたパッケージに内蔵
した圧電デバイスにおいて、パッケージに樹脂接着剤を
塗布する工程と、バンプの接合部に応力緩和作用を有す
る導電性接着剤を付着させる工程と、パッケージに半導
体集積回路を接合する工程と、半導体集積回路の裏面に
樹脂接着剤を塗布する工程と、圧電振動子をマウントす
る工程と、パッケージに金属製のリッドを気密封止する
工程とからなることを特徴とする。According to a fifth aspect of the present invention, in a piezoelectric device in which a semiconductor integrated circuit and a piezoelectric vibrator are built in a package formed of a wiring board, a step of applying a resin adhesive to the package, A step of attaching a conductive adhesive having a stress relaxing action, a step of bonding the semiconductor integrated circuit to the package, a step of applying a resin adhesive to the back surface of the semiconductor integrated circuit, and a step of mounting the piezoelectric vibrator, Sealing the metal lid in the package.
【００１３】[0013]
【発明の実施の形態】本発明の圧電デバイスの実施の一
形態を、発振回路を有するワンチップの半導体集積回路
と、圧電振動子にＡＴカット水晶振動子とを用いた、水
晶発振器を例として図面に基づいて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the piezoelectric device of the present invention will be described with reference to a one-chip semiconductor integrated circuit having an oscillation circuit and a crystal oscillator using an AT-cut crystal resonator as a piezoelectric resonator. This will be described with reference to the drawings.
【００１４】（実施例１）図１は、請求項１、２、３、
４、５記載の発明に係わる表面実装タイプの水晶発振器
の構造図である。(Embodiment 1) FIG.
FIG. 6 is a structural view of a surface-mounted type crystal oscillator according to the inventions described in 4 and 5.
【００１５】図１（ａ）の平面図及び図１（ｂ）の正面
図に示すように、少なくとも３層からなるセラミック絶
縁基板と、Ｆｅ−Ｎｉ合金等で枠状に型抜きされたシー
ルリングとで形成されたベース１の第１層に、半導体集
積回路（ＩＣチップ：以下ＩＣチップと記す）２と接続
するための電極パターン３が、Ｗ（タングステン）ある
いはＭｏ（モリブデン）等の金属配線材料で印刷等によ
りメタライズされている。そしてその上にＮｉメッキ及
びＡｕメッキ等が施されている。As shown in the plan view of FIG. 1 (a) and the front view of FIG. 1 (b), a ceramic insulating substrate having at least three layers, and a seal ring cut into a frame shape with an Fe-Ni alloy or the like. An electrode pattern 3 for connecting to a semiconductor integrated circuit (IC chip: hereinafter, referred to as an IC chip) 2 is formed on the first layer of the base 1 formed of a metal wiring such as W (tungsten) or Mo (molybdenum). Metallized by printing or the like with the material. Then, Ni plating, Au plating or the like is applied thereon.
【００１６】又、ＩＣチップ２の電極パッドにはＡｕ等
の金属のバンプ４が形成され、フリップチップボンディ
ング工法により、導電性接着剤５を用いてベース１に形
成された電極パターン３と接合されている。このフリッ
プチップボンディング工法には、種々の加工法がある
が、本発明で用いている工法は接合部に導電性の接着剤
を用い、適当な加圧と温度を印加して接合する加工方法
である。A bump 4 made of metal such as Au is formed on an electrode pad of the IC chip 2 and is joined to the electrode pattern 3 formed on the base 1 by a flip chip bonding method using a conductive adhesive 5. ing. There are various processing methods for this flip chip bonding method, and the method used in the present invention is a processing method in which a conductive adhesive is used for a joint portion and bonding is performed by applying appropriate pressure and temperature. is there.
【００１７】又、ＡＴカット水晶振動子６はその支持部
７を、ベース１の第２層に設けられたマウント部８に導
電性接着剤９で接続固定されている。The AT-cut crystal unit 6 has its support 7 connected and fixed to a mount 8 provided on the second layer of the base 1 by a conductive adhesive 9.
【００１８】更に、金属製のリッド（蓋）１１をベース
１のＦｅ−Ｎｉ合金等で枠状に型抜きされたシールリン
グ１２に位置合わせして固定し、シーム溶接により気密
に封止している。Further, a metal lid (lid) 11 is positioned and fixed to a seal ring 12 cut out in a frame shape with an Fe--Ni alloy or the like of the base 1, and is hermetically sealed by seam welding. I have.
【００１９】以上により、小型薄型の表面実装パッケー
ジの水晶発振器１３が完成する。As described above, the crystal oscillator 13 of a small and thin surface mount package is completed.
【００２０】次に、ＩＣチップ２にＡｕ等で形成された
バンプ４を形成するバンプ形成プロセスと、ＩＣチップ
２をベース１に形成された電極パターン３に接合する、
フリップチップボンディングのプロセスについて詳細に
説明する。Next, a bump forming process for forming bumps 4 made of Au or the like on the IC chip 2 and bonding the IC chip 2 to the electrode patterns 3 formed on the base 1 are performed.
The flip chip bonding process will be described in detail.
【００２１】例えば、図２及び図３に示すように４イン
チ〜６インチのウェハー状態のＩＣチップ２の各パッド
１４に、その線径がΦ２５〜３５μｍ程度のＡｕボンデ
ィング細線を用いて超音波バンプボンディングにより、
複数のバンプ４を形成する。For example, as shown in FIGS. 2 and 3, each pad 14 of the IC chip 2 in a wafer state of 4 inches to 6 inches is covered with an ultrasonic bump using a Au bonding thin wire having a wire diameter of about 25 to 35 μm. By bonding
A plurality of bumps 4 are formed.
【００２２】又、ウェハー状態で複数個（数千個程度）
のＩＣチップ２にバンプ形成加工を行うため、このバン
プ形成加工の温度は低いことが望ましく、本実施例では
１８０℃前後の温度でバンプ加工を行っている。この温
度については、接合強度及び共晶の程度の評価実験によ
り１８０℃〜２３０℃程度の範囲が適当である。Also, a plurality of wafers (about several thousands) in a wafer state
Since the bump forming process is performed on the IC chip 2 described above, it is desirable that the temperature of the bump forming process is low. In this embodiment, the bump process is performed at a temperature of about 180 ° C. As for this temperature, a range of about 180 ° C. to 230 ° C. is appropriate according to an experiment for evaluating the bonding strength and the degree of eutectic.
【００２３】又、バンプ４の２段目の先端部については
その平坦度を良くするために、図４に示すようにバンプ
４の先端部を潰してレベリングを施した形状を用いても
よい。In order to improve the flatness of the second end of the bump 4, a shape in which the end of the bump 4 is crushed and leveled may be used as shown in FIG.
【００２４】次に、以上の形状でバンプ４が形成された
ＩＣチップ２を、ベース１にフリップチップボンディン
グするプロセスについて詳細に説明する。Next, a process of flip-chip bonding the IC chip 2 having the bumps 4 formed in the above-described shape to the base 1 will be described in detail.
【００２５】図５のフリップチップボンディングの接合
拡大図に示すように、ウェハー上のＩＣチップ２が角錐
コレット等のノズルによりピックアップされ、反転し
て、接合用のノズルに受け渡しされる。そして、バンプ
４の先端に応力緩和作用の高い導電性接着剤５を適量付
着させて、フリップチップボンディング装置に設けられ
た画像認識等のシステムにより、ＩＣチップ２がアライ
メントされて精度良くベース１のマウントエリアにチッ
プマウントされる。As shown in the enlarged view of the bonding of the flip chip bonding in FIG. 5, the IC chip 2 on the wafer is picked up by a nozzle such as a pyramid collet, inverted, and delivered to the bonding nozzle. Then, an appropriate amount of a conductive adhesive 5 having a high stress relaxation effect is applied to the tip of the bump 4, and the IC chip 2 is aligned by a system such as an image recognition provided in the flip chip bonding apparatus, so that the base 1 can be precisely formed. The chip is mounted on the mounting area.
【００２６】ここで本実施例で用いている導電性接着剤
５は、シリコン系の銀ペーストである。シリコン系の導
電性接着剤５は、耐熱性が良く高温に放置しても特性の
劣化が少なく非常に安定している。またバンプ４の接合
界面に働く応力を緩和する作用が高く、エポキシ系等の
他の導電性接着剤に比較して信頼性の高い接合を得るこ
とができる。Here, the conductive adhesive 5 used in this embodiment is a silicon-based silver paste. The silicon-based conductive adhesive 5 has excellent heat resistance and is very stable with little deterioration in characteristics even when left at high temperatures. Also, the effect of relieving the stress acting on the bonding interface of the bumps 4 is high, and a highly reliable bonding can be obtained as compared with other conductive adhesives such as epoxy-based adhesives.
【００２７】また、それと同時にＩＣチップ２がチップ
マウントされる前に、ベース１のマウントエリアのほぼ
中央に、絶縁性の樹脂接着剤１５を塗布している。この
樹脂接着剤１５も応力緩和作用の高い樹脂のものが好ま
しい。また、樹脂接着剤１５の塗布量は、ＩＣチップ２
の表面積の１／４〜１／３程度が好ましい。At the same time, before the IC chip 2 is mounted, an insulating resin adhesive 15 is applied to almost the center of the mounting area of the base 1. The resin adhesive 15 is also preferably a resin having a high stress relaxation action. The amount of the resin adhesive 15 to be applied is
Is preferably about 1/4 to 1/3 of the surface area.
【００２８】更に、図１（ｂ）に示すようにＩＣチップ
２がベース１にフリップチップボンディングされた後、
ＩＣチップ２の裏面の縁部１６に先に用いた樹脂接着剤
１５を適量塗布する。Further, after the IC chip 2 is flip-chip bonded to the base 1 as shown in FIG.
An appropriate amount of the previously used resin adhesive 15 is applied to the edge 16 on the back surface of the IC chip 2.
【００２９】ここで、ＩＣチップ２がベース１の電極パ
ターン３上に接しフリップチップボンディング装置がそ
の負荷を検出すると、１バンプ当たり１００ｇｒ前後の
荷重を印可する。又、この接合には適度の熱も必要であ
り、ベース１にはあらかじめ１５０℃〜２００℃前後の
熱が加えられている。Here, when the IC chip 2 comes into contact with the electrode pattern 3 of the base 1 and the flip chip bonding apparatus detects the load, a load of about 100 gr per bump is applied. In addition, appropriate heat is required for this bonding, and heat of about 150 ° C. to 200 ° C. is applied to the base 1 in advance.
【００３０】又、フリップチップボンディング装置には
ＩＣチップ２の高さ方向を検出するセンサーが設けられ
ており、その高さ方向のデータを管理しながらバンプ４
の高さを均一な状態で加工することが可能である。The flip chip bonding apparatus is provided with a sensor for detecting the height direction of the IC chip 2, and manages the bumps 4 while managing the data in the height direction.
Can be processed in a uniform state.
【００３１】次に、ＡＴカット水晶振動子６をベース１
にマウントするプロセスについて説明する。Next, the AT-cut quartz resonator 6 is
The process of mounting on the server will be described.
【００３２】図１に示すように、ＡＴカット水晶振動子
６はベース１の第２層に設けられた、マウント部８のマ
ウント用電極に導電性接着剤９により接続固定される。
その時ＡＴカット水晶振動子６の先端部が、縁部１６に
用いた樹脂接着剤１５により保持される。As shown in FIG. 1, the AT-cut quartz resonator 6 is connected and fixed to a mounting electrode of a mount section 8 provided on a second layer of the base 1 by a conductive adhesive 9.
At this time, the tip of the AT-cut quartz resonator 6 is held by the resin adhesive 15 used for the edge 16.
【００３３】そして、導電性接着剤５及び９等の硬化を
含めてＩＣチップ２及びＡＴカット水晶振動子６を内蔵
したパッケージ全体を高温でアニール処理する。これは
導電性接着剤５及び９や樹脂接着剤１５やベース１等か
らのアウトガスを除去する効果もあり、一般的には２０
０℃〜３００℃の高温下で１〜２時間の処理が行われ
る。Then, the entire package including the IC chip 2 and the AT-cut quartz crystal vibrator 6, including the curing of the conductive adhesives 5 and 9, is annealed at a high temperature. This also has the effect of removing outgas from the conductive adhesives 5 and 9, the resin adhesive 15, the base 1, and the like.
The treatment is performed at a high temperature of 0 ° C. to 300 ° C. for 1 to 2 hours.
【００３４】この熱処理により、バンプ４部のＡｕ−Ａ
ｌ共晶反応や、Ａｕ−Ａｕ固相接合の反応が進み、バン
プ４の接合強度等の接合特性が変化する。本実施例で
は、このようなフリップチップボンディング以降の熱履
歴を踏まえて、バンプ４の形成条件やフリップチップボ
ンディング条件等を決定している。By this heat treatment, the Au—A
The 1 eutectic reaction and the reaction of Au-Au solid phase bonding proceed, and the bonding characteristics such as the bonding strength of the bump 4 change. In the present embodiment, the conditions for forming the bumps 4 and the flip chip bonding conditions are determined based on the thermal history after the flip chip bonding.
【００３５】更に、金属製のリッド１１をベース１のＦ
ｅ−Ｎｉ合金等で枠状に型抜きされたシールリング１２
に位置合わせして固定し、シーム溶接により気密に封止
している。Further, the metal lid 11 is connected to the F
Seal ring 12 cut into a frame shape with e-Ni alloy or the like
And is hermetically sealed by seam welding.
【００３６】以上、セラミック及び金属といった信頼性
が高く、かつ安価な構成部品を用いることにより、横２
〜３．２ｍｍ、幅２〜２．５ｍｍ、厚さ０．７〜１．０
ｍｍという小型薄型の高信頼性の圧電発振器が安価に提
供できる。As described above, by using highly reliable and inexpensive components such as ceramics and metals, horizontal
~ 3.2mm, width 2 ~ 2.5mm, thickness 0.7 ~ 1.0
mm and a highly reliable piezoelectric oscillator having a small thickness and a small thickness can be provided at low cost.
【００３７】以上、発振回路を有するワンチップの半導
体集積回路と、圧電振動子にＡＴカット水晶振動子とを
用いた、水晶発振器を例に述べてきたが、本発明はそれ
に限定されることなく、例えば電圧制御水晶発振器（Ｖ
ＣＸＯ）や温度補償水晶発振器（ＴＣＸＯ）やＳＡＷ発
振器、あるいはリアルタイムクロックモジュール等の半
導体集積回路を内蔵した圧電デバイス全てに適用でき
る。更に、水晶振動子チップやＳＡＷチップをパッケー
ジにフリップチップボンディングにより実装する圧電デ
バイスにも同様に適用できる。As described above, a one-chip semiconductor integrated circuit having an oscillation circuit and a quartz oscillator using an AT-cut quartz oscillator as a piezoelectric oscillator have been described as examples. However, the present invention is not limited to this. For example, a voltage-controlled crystal oscillator (V
The present invention can be applied to all piezoelectric devices including a semiconductor integrated circuit such as a CXO), a temperature compensated crystal oscillator (TCXO), a SAW oscillator, and a real-time clock module. Furthermore, the present invention can be similarly applied to a piezoelectric device in which a crystal resonator chip or a SAW chip is mounted on a package by flip chip bonding.
【００３８】[0038]
【発明の効果】請求項１、２、３、５記載の発明によれ
ば、半導体集積回路は樹脂接着剤で配線基板に接合さ
れ、電極パターンとバンプの接合部に応力緩和作用を有
するシリコン系の導電性接着剤を用いた構造をとること
により、接合部に加わる応力が非常に少なくなり、また
半導体集積回路の特定のバンプへ応力が集中することが
なくなり、バンプと電極パターンとの接合部が熱応力等
によりオープンしてしまうというような、接合不良のな
い構造的に優れた圧電発振器を提供できるという効果を
有する。According to the first, second, third, and fifth aspects of the present invention, a semiconductor integrated circuit is bonded to a wiring board with a resin adhesive, and a silicon-based material having a stress relaxing action at a bonding portion between an electrode pattern and a bump. By using a structure using a conductive adhesive, the stress applied to the joint is extremely reduced, and the stress is not concentrated on a specific bump of the semiconductor integrated circuit. However, there is an effect that it is possible to provide a structurally excellent piezoelectric oscillator free from bonding defects, such as that the piezoelectric oscillator is opened due to thermal stress or the like.
【００３９】請求項４記載の発明によれば、樹脂接着剤
が半導体集積回路の裏面に塗布されており、この樹脂接
着剤で圧電振動子の先端を保持することにより、圧電振
動子と半導体集積回路との電気的、物理的な接触を避け
ることができる。これにより安定した発振特性が得られ
という効果を有する。また樹脂接着剤で圧電振動子の先
端部を保持することにより、圧電振動子に加わる振動、
落下等による衝撃等を緩和する作用も働き、更に安定し
た発振特性が得られという効果を有する。According to the fourth aspect of the invention, the resin adhesive is applied to the back surface of the semiconductor integrated circuit, and the front end of the piezoelectric vibrator is held by the resin adhesive, whereby the piezoelectric vibrator and the semiconductor integrated circuit are integrated. Electrical and physical contact with the circuit can be avoided. This has an effect that stable oscillation characteristics can be obtained. Also, by holding the tip of the piezoelectric vibrator with resin adhesive, vibration applied to the piezoelectric vibrator,
The effect of alleviating the impact or the like due to a drop or the like also works, and has an effect that more stable oscillation characteristics can be obtained.
【図１】本発明の圧電デバイスの構造図。（ａ）は、平
面図。（ｂ）は、正面図。FIG. 1 is a structural view of a piezoelectric device of the present invention. (A) is a top view. (B) is a front view.
【図２】本発明の圧電デバイスのバンプ形成図。FIG. 2 is a bump formation diagram of the piezoelectric device of the present invention.
【図３】本発明の圧電デバイスのバンプ形状図。FIG. 3 is a bump shape diagram of the piezoelectric device of the present invention.
【図４】本発明の圧電デバイスの他のバンプ形状図。FIG. 4 is another bump shape diagram of the piezoelectric device of the present invention.
【図５】本発明の圧電デバイスの半導体集積回路と電極
パターンの接合部拡大図。FIG. 5 is an enlarged view of a joint between a semiconductor integrated circuit and an electrode pattern of the piezoelectric device of the present invention.
【図６】従来の圧電デバイスの構造図。（ａ）は、平面
図。（ｂ）は、正面図。FIG. 6 is a structural view of a conventional piezoelectric device. (A) is a top view. (B) is a front view.
１ ベース ２ ＩＣチップ ３ 電極パターン ４ バンプ ５ 導電性接着剤 ６ ＡＴカット水晶振動子 ７ 支持部 ８ マウント部 ９ 導電性接着剤 １１ リッド １２ シールリング １３ 水晶発振器 １４ パッド １５ 樹脂接着剤 １６ 縁部 １０１ ＩＣチップ １０２ ベース １０３ Ａｕワイヤーボンディング線 １０４ 入出力用電極 １０５ ＡＴカット水晶振動子 １０６ マウント部 １０７ シールリング １０８ リッド DESCRIPTION OF SYMBOLS 1 Base 2 IC chip 3 Electrode pattern 4 Bump 5 Conductive adhesive 6 AT cut crystal oscillator 7 Support part 8 Mount part 9 Conductive adhesive 11 Lid 12 Seal ring 13 Crystal oscillator 14 Pad 15 Resin adhesive 16 Edge 101 IC chip 102 Base 103 Au wire bonding wire 104 Input / output electrode 105 AT-cut quartz oscillator 106 Mount 107 Seal ring 108 Lid
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０３Ｈ 9/02 Ｈ０３Ｈ 9/02 Ｌ Ｈ０１Ｌ 41/08 Ｃ Ｕ ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H03H 9/02 H03H 9/02 L H01L 41/08 CU
Claims (5)
で形成されたパッケージに内蔵した圧電デバイスにおい
て、前記半導体集積回路は前記パッケージの電極パター
ンと複数のバンプにより接合されてなり、前記電極パタ
ーンと前記バンプの接合部に応力緩和作用を有する導電
性接着剤を用いたことを特徴とする圧電デバイス。1. A piezoelectric device in which a semiconductor integrated circuit and a piezoelectric vibrator are built in a package formed of a wiring board, wherein the semiconductor integrated circuit is joined to an electrode pattern of the package by a plurality of bumps, A piezoelectric device, wherein a conductive adhesive having a stress relaxing action is used at a joint between a pattern and the bump.
で形成されたパッケージに内蔵した圧電デバイスにおい
て、前記半導体集積回路は樹脂接着剤で前記パッケージ
に接合されてなり、電極パターンとバンプの接合部に応
力緩和作用を有する導電性接着剤を用いたことを特徴と
する請求項1記載の圧電デバイス。2. A piezoelectric device in which a semiconductor integrated circuit and a piezoelectric vibrator are built in a package formed of a wiring board, wherein the semiconductor integrated circuit is bonded to the package with a resin adhesive, and an electrode pattern and bumps are formed. 2. The piezoelectric device according to claim 1, wherein a conductive adhesive having a stress relaxing action is used for the joint.
で形成されたパッケージに内蔵した圧電デバイスにおい
て、導電性接着剤がシリコン系の導電性接着剤であるこ
とを特徴とする請求項1記載の圧電デバイス。3. A piezoelectric device in which a semiconductor integrated circuit and a piezoelectric vibrator are incorporated in a package formed of a wiring board, wherein the conductive adhesive is a silicon-based conductive adhesive. The piezoelectric device as described.
で形成されたパッケージに内蔵した圧電デバイスにおい
て、樹脂接着剤が前記半導体集積回路の裏面に塗布され
ており、前記樹脂接着剤が前記圧電振動子の先端を保持
していることを特徴とする請求項２記載の圧電デバイ
ス。4. A piezoelectric device in which a semiconductor integrated circuit and a piezoelectric vibrator are built in a package formed of a wiring board, wherein a resin adhesive is applied to a back surface of the semiconductor integrated circuit, and the resin adhesive is 3. The piezoelectric device according to claim 2, wherein a tip of the piezoelectric vibrator is held.
で形成されたパッケージに内蔵した圧電デバイスにおい
て、前記パッケージに樹脂接着剤を塗布する工程と、 バンプの接合部に応力緩和作用を有する導電性接着剤を
付着させる工程と、 前記パッケージに前記半導体集積回路を接合する工程
と、 前記半導体集積回路の裏面に前記樹脂接着剤を塗布する
工程と、 前記圧電振動子をマウントする工程と、 前記パッケージに金属製のリッドを気密封止する工程と
からなることを特徴とする圧電デバイスの製造方法。5. A piezoelectric device in which a semiconductor integrated circuit and a piezoelectric vibrator are built in a package formed of a wiring substrate, wherein a step of applying a resin adhesive to the package and a stress-relieving action at a junction of the bumps are provided. Attaching a conductive adhesive, joining the semiconductor integrated circuit to the package, applying the resin adhesive to the back surface of the semiconductor integrated circuit, and mounting the piezoelectric vibrator; And a step of hermetically sealing a metal lid in the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000070668A JP3678106B2 (en) | 2000-03-14 | 2000-03-14 | Piezoelectric device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000070668A JP3678106B2 (en) | 2000-03-14 | 2000-03-14 | Piezoelectric device and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| JP2001267363A true JP2001267363A (en) | 2001-09-28 |
| JP3678106B2 JP3678106B2 (en) | 2005-08-03 |
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ID=18589370
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| Country | Link |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016086324A (en) * | 2014-10-28 | 2016-05-19 | 京セラクリスタルデバイス株式会社 | Crystal oscillator |
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2000
- 2000-03-14 JP JP2000070668A patent/JP3678106B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016086324A (en) * | 2014-10-28 | 2016-05-19 | 京セラクリスタルデバイス株式会社 | Crystal oscillator |
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|---|---|
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