JP4085549B2 - Piezoelectric device and manufacturing method thereof - Google Patents

Piezoelectric device and manufacturing method thereof Download PDF

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JP4085549B2
JP4085549B2 JP2000070664A JP2000070664A JP4085549B2 JP 4085549 B2 JP4085549 B2 JP 4085549B2 JP 2000070664 A JP2000070664 A JP 2000070664A JP 2000070664 A JP2000070664 A JP 2000070664A JP 4085549 B2 JP4085549 B2 JP 4085549B2
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layer
piezoelectric vibrator
integrated circuit
semiconductor integrated
piezoelectric
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JP2001257533A (en
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正幸 菊島
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Seiko Epson Corp
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    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/732—Location after the connecting process
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    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

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  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体集積回路と圧電振動子とをパッケージに内蔵した圧電デバイス及びその製造方法に関する。
【０００２】
【従来の技術】
近年、ＨＤＤ（ハード・ディスク・ドライブ）、モバイルコンピュータ、あるいはＩＣカード等の小型の情報機器や、携帯電話や自動車電話等の移動体通信機器において装置の小型薄型化がめざましく、それらに用いられる圧電発振器や電圧制御発振器（ＶＣＸＯ）や温度補償発振器（ＴＣＸＯ）やＳＡＷ発振器、あるいはリアルタイムクロックモジュール等の圧電デバイスも小型薄型化が要求されている。又、それとともに、装置の回路基板に両面実装が可能な表面実装タイプの圧電デバイスが求められている。
【０００３】
そこで、従来の圧電デバイスの一例を、発振回路を有するワンチップの半導体集積回路と、圧電振動子にＡＴカット水晶振動子とを用いた図７（ａ）、７（ｂ）の構造図で示される水晶発振器を用いて説明する。
【０００４】
図７（ａ）、７（ｂ）の従来の水晶発振器の構成において、発振回路を有するＩＣチップ１０１は、セラミック絶縁基板で形成されたベース１０２の底面に導電性接着剤等により接着固定され、Ａｕワイヤーボンディング線１０３により、ベース１０２の底面外周部にＷ（タングステン）あるいはＭｏ（モリブデン）等の金属でメタライズされ、Ｎｉ＋Ａｕメッキされた入出力用電極１０４等に電気的に接続されている。
【０００５】
又、矩形タイプのＡＴカット水晶振動子１０５が、ベース１０２のマウント部１０６に導電性接着剤等で電気的に接続され固定されている。そして、Ｎ2（窒素）雰囲気あるいは真空雰囲気に内部を保ち、ベース１０２の最上部のシールリング１０７と、金属製のリッド１０８とをシーム溶接により接合し気密に封止している。
【０００６】
【発明が解決しようとする課題】
以上に示す従来の水晶発振器は、ＩＣチップ１０１の周囲にＡｕワイヤーボンディング線１０３を配線するエリアが必要であること。又、パッケージの厚み方向でも、Ａｕワイヤーボンディング線１０３のループ高さの確保や、Ａｕワイヤーボンディング線１０３とＡＴカット水晶振動子１０５との隙間の確保が必要であること等、この構成が水晶発振器を小型薄型にするための制約となっている。
【０００７】
本発明の目的は、以上の従来技術の課題を解決するためになされたものであり、その目的とするところは小型薄型サイズで厚み１ｍｍ以下の水晶発振器等の圧電デバイスを安価に提供することである。
【０００８】
【課題を解決するための手段】
請求項１記載の発明は、半導体集積回路と圧電振動子とを同一のパッケージに内蔵した圧電デバイスにおいて、前記パッケージは、絶縁基板からなる第１層と、前記第１層上に位置し絶縁基板からなる第２層とを有し、前記第１層の一方の面は、前記第２層の一方の面に相対しており、前記第１層の前記一方の面に前記圧電振動子が導電性接着剤で接合されてなり、前記第２層は、前記圧電振動子を収容する孔が形成され、前記圧電振動子を囲う形状を有しており、前記第２層の他方の面上であって前記孔を挟んだ両側の領域に、前記半導体集積回路と接続するための複数の電極パターンが形成されており、前記半導体集積回路は、前記第２層の前記複数の電極パターンと複数のバンプにより接合されて前記圧電振動子の上方に配置されていることを特徴とする。
【０００９】
請求項２記載の発明は、半導体集積回路と圧電振動子とを同一のパッケージに内蔵した圧電デバイスにおいて、前記パッケージは、絶縁基板からなる第１層と、前記第１層上に位置し絶縁基板からなる第２層とを有し、前記第１層の一方の面は、前記第２層の一方の面に相対しており、前記第１層の前記一方の面に前記圧電振動子が複数のバンプで接合されてなり、前記第２層は、前記圧電振動子を収容する孔が形成され、前記圧電振動子を囲う形状を有しており、前記第２層の他方の面上であって前記孔を挟んだ両側の領域に、前記半導体集積回路と接続するための複数の電極パターンが形成されており、前記半導体集積回路は、前記第２層の前記複数の電極パターンと複数のバンプにより接合されて前記圧電振動子の上方に配置されていることを特徴とする。
【００１０】
請求項３記載の発明は、請求項１または２において、半導体集積回路と圧電振動子とを配線基板で形成されたパッケージに内蔵した圧電デバイスにおいて、半導体集積回路は圧電振動子の上方かつ圧電振動子の接合部付近に配置されてなることを特徴とする。
【００１１】
請求項４記載の発明は、請求項１または２において、半導体集積回路と圧電振動子とを配線基板で形成されたパッケージに内蔵した圧電デバイスにおいて、少なくとも圧電振動子の一部は半導体集積回路の外部に露出してなることを特徴とする。
【００１２】
請求項５記載の発明は、半導体集積回路と圧電振動子とを同一のパッケージに内蔵し、前記パッケージは、絶縁基板からなる第１層と、前記第１層上に位置し絶縁基板からなる第２層とを有し、前記第１層の一方の面は、前記第２層の一方の面に相対しており、前記第１層の前記一方の面にマウント部が形成され、前記第２層は前記圧電振動子を収容する孔が形成され、前記圧電振動子を囲う形状を有しており、前記第２層の他方の面上であって前記孔を挟んだ両側の領域に、前記半導体集積回路と接続するための複数の電極パターンが形成されている圧電デバイスの製造方法であって、前記マウント部に前記圧電振動子を接合する工程と、前記半導体集積回路を前記複数の電極パターンにバンプにより接合し、前記圧電振動子の一部を露出した位置で且つ前記圧電振動子の上方に前記半導体回路を配置する工程と、前記半導体集積回路から露出した前記圧電振動子の前記一部を用いて周波数調整する工程と、を順に行うことを特徴とする。請求項６記載の発明は、半導体集積回路と圧電振動子とを同一のパッケージに内蔵し、前記パッケージは、絶縁基板からなる第１層と、前記第１層上に位置し絶縁基板からなる第２層とを有し、前記第１層の一方の面は、前記第２層の一方の面に相対しており、前記第１層の前記一方の面にマウント部が形成され、前記第２層は前記圧電振動子を収容する孔が形成され、前記圧電振動子を囲う形状を有しており、前記第２層の他方の面上であって前記孔を挟んだ両側の領域に、前記半導体集積回路と接続するための複数の電極パターンが形成されている圧電デバイスの製造方法であって、前記マウント部に前記圧電振動子を導電性接着剤により接合する工程と、前記パッケージ全体を高温でアニール処理する工程と、前記半導体集積回路を、前記複数の電極パターンにバンプにより接合し前記圧電振動子の上方に配置する工程と、を順に行うことを特徴とする。
【００１３】
【発明の実施の形態】
本発明の圧電デバイスの実施の一形態を、発振回路を有するワンチップの半導体集積回路と、圧電振動子にＡＴカット水晶振動子とを用いた、水晶発振器を例として図面に基づいて説明する。
【００１４】
（実施例１）
図１は、請求項１、３、４、５記載の発明に係わる表面実装タイプの水晶発振器の構造図である。
【００１５】
図１（ａ）の平面図及び図１（ｂ）の正面図に示すように、少なくとも３層からなるセラミック絶縁基板と、Ｆｅ−Ｎｉ合金等で枠状に型抜きされたシールリングとで形成されたベース１の第１層に設けられたマウント部２に、ＡＴカット水晶振動子３がその支持部４を導電性接着剤５で接続固定されている。
【００１６】
また、ベース１の第２層には半導体集積回路（ＩＣチップ：以下ＩＣチップと記す）６と接続するための電極パターン７が、Ｗ（タングステン）あるいはＭｏ（モリブデン）等の金属配線材料で印刷等によりメタライズされている。そしてその上にＮｉメッキ及びＡｕメッキ等が施されている。
【００１７】
又、ＩＣチップ６の電極パッドにはＡｕ等の金属のバンプ８が形成され、フリップチップボンディング工法によりベース１に形成された電極パターン７と接続されている。このフリップチップボンディング工法には、種々の加工法があるが、本実施例で用いている工法は接続部に導電性の接着剤を用いた加工方法である。
【００１８】
更に、金属製のリッド（蓋）１０をベース１のＦｅ−Ｎｉ合金等で枠状に型抜きされたシールリング９に位置合わせして固定し、シーム溶接により気密に封止している。
【００１９】
以上により、小型薄型の表面実装パッケージの水晶発振器１１が完成する。
【００２０】
次に、ＡＴカット水晶振動子３及びＩＣチップ６の各マウントプロセスについて詳細に説明する。
【００２１】
図２に示すように、ベース１の第１層に設けられたマウント部２に導電性接着剤５がディスペンス装置等で適量塗布される。そして、水晶振動子をマウントする装置によりＡＴカット水晶振動子３が画像認識され、その支持部４がマウント部２の導電性接着剤５に接合される。
【００２２】
次に、導電性接着剤５の硬化をするためにＡＴカット水晶振動子３を内蔵したパッケージ全体を高温で処理する。これは導電性接着剤５やベース１あるいはＡＴカット水晶振動子３等からのアウトガスを除去するアニール効果もあり、一般的には２００℃〜３５０℃の高温下で１〜２時間の処理が行われる。
【００２３】
特に、高精度水晶発振器や電圧制御水晶発振器（ＶＣＸＯ）や温度補償水晶発振器（ＴＣＸＯ）やＳＡＷ発振器等の高精度、あるいは高周波が要求される圧電デバイス等では、このアニール処理が非常に重要である。このような圧電デバイスには、ＡＴカット水晶振動子３の内蔵されたパッケージの雰囲気に、微量のガス等が存在することにより、周波数精度が悪くなり安定した発振特性が得られないという課題がある。
【００２４】
しかし、本実施例によれば、ＩＣチップ６を内蔵する前にパッケージ全体を高温で処理することが可能であり、ＩＣチップ６の耐熱性の問題に拘わらずアニール処理に必要充分な高温処理が行える。
【００２５】
次に、ＩＣチップ６にＡｕ等で形成されたバンプ８を形成するバンプ形成プロセスと、ＩＣチップ６をベース１に形成された電極パターン７に接続する、フリップチップボンディングのプロセスについて詳細に説明する。
【００２６】
例えば、図３に示すように４インチ〜６インチのウェハー状態のＩＣチップ６の各パッド１２に、その線径がΦ２５〜３５μｍ程度のＡｕボンディング細線を用いて超音波バンプボンディングにより、複数のバンプ８を形成する。
【００２７】
又、ウェハー状態で複数個（数千個程度）のＩＣチップ６にバンプ形成加工を行うため、このバンプ形成加工の温度は低いことが望ましく、本実施例では１８０℃前後の温度でバンプ加工を行っている。この温度については、接合強度及びＡｕ−Ａｌ共晶の程度の評価実験により１８０℃〜２３０℃程度の範囲が適当である。
【００２８】
次に、以上のプロセスでバンプ８が形成されたＩＣチップ６を、ベース１にフリップチップボンディングするプロセスについて詳細に説明する。
【００２９】
図４のフリップチップボンディングの接合拡大図に示すように、ウェハー上のＩＣチップ６が角錐コレット等のノズルによりピックアップされ、反転して、接合用のノズルに受け渡しされる。そして、バンプ８の先端に応力緩和作用の高い導電性接着剤１２を適量付着させて、フリップチップボンディング装置に設けられた画像認識等のシステムにより、ＩＣチップ６がアライメントされて精度良くベース１のマウントエリアにチップマウントされる。
【００３０】
そしてＩＣチップ６はＡＴカット水晶振動子３の一部を露出した位置で、かつＡＴカット水晶振動子３の上方に配置される。
【００３１】
ここで本実施例で用いている導電性接着剤１２は、シリコン系の銀ペーストである。シリコン系の導電性接着剤１２は、耐熱性が良く高温に放置しても特性の劣化が少なく非常に安定している。またバンプ８の接合界面に働く応力を緩和する作用が高く、エポキシ系等の他の導電性接着剤に比較して信頼性の高い接合を得ることができる。
【００３２】
又、フリップチップボンディング装置にはＩＣチップ６の高さ方向を検出するセンサーが設けられており、その高さ方向のデータを管理しながらバンプ８の高さを均一な状態で加工することが可能である。
【００３３】
ここで、本実施例で用いている加工条件は、１バンプ当たり百グラム前後の荷重を印加している。
【００３４】
そして、導電性接着剤１２の硬化を含めてＩＣチップ６及びＡＴカット水晶振動子３を内蔵したパッケージ全体を１５０℃〜１８０℃の高温で熱処理する。
【００３５】
ここでバンプ８をベース１に接合する方法には種々の方法があり、本実施例以外の方法、例えば超音波あるいは高温と圧力等によるＡｕ−Ａｕ接合や、ＡＣＦ等のフィルム状の接着剤を用いた加工方法でもよい。
【００３６】
次に、ＡＴカット水晶振動子３の周波数調整を行うプロセスについて詳細に説明する。
【００３７】
図５に示すように、ＩＣチップ６から露出したＡＴカット水晶振動子３のＡ部１３に、真空蒸着方法あるいはプラズマエッチング方法等によりＡＴカット水晶振動子３の周波数を調整する加工を行う。このようにＩＣチップ６に電源電圧を印加して、ＡＴカット水晶振動子３を発振させた状態で、ＡＴカット水晶振動子３のＡ部１３に周波数調整することにより、ＩＣチップ６の回路定数等とマッチングのとれた精度の良い周波数調整が行える。
【００３８】
更に、金属製のリッド１０をベース１のＦｅ−Ｎｉ合金等で枠状に型抜きされたシールリング９に位置合わせして固定し、シーム溶接により気密に封止している。
【００３９】
（実施例２）
図６は、請求項２記載の本発明の他の実施例の水晶発振器の構造を示す構造図である。
【００４０】
図６に示すように、ベース２１の第１層に設けられたマウント部２２に、支持部２３に複数のバンプ２４が形成されたＡＴカット水晶振動子２５が画像認識され、バンプ２４の先端に付着した導電性接着剤２６により接合されている。
【００４１】
ここでバンプ２４をベース２１に接合する方法には種々の方法があり、本実施例以外の方法、例えば超音波あるいは高温と圧力等によるＡｕ−Ａｕ接合や、ＡＣＦ等のフィルム状の接着剤を用いた加工方法でもよい。
【００４２】
以上、セラミック及び金属といった信頼性が高く、かつ安価な構成部品を用いることにより、横２〜３．２ｍｍ、幅２〜２．５ｍｍ、厚さ０．７〜１．０ｍｍという小型薄型の高信頼性の圧電発振器が安価に提供できる。
【００４３】
以上、発振回路を有するワンチップの半導体集積回路と、圧電振動子にＡＴカット水晶振動子とを用いた、水晶発振器を例に述べてきたが、本発明はそれに限定されることなく、例えば電圧制御水晶発振器（ＶＣＸＯ）や温度補償水晶発振器（ＴＣＸＯ）やＳＡＷ発振器、あるいはリアルタイムクロックモジュール等の半導体集積回路を内蔵した圧電デバイス全てに適用できる。更に、水晶振動子チップやＳＡＷチップをパッケージにフリップチップボンディングにより実装する圧電デバイスにも同様に適用できる。
【００４４】
【発明の効果】
請求項１、２、３、４、５記載の発明によれば、パッケージに圧電振動子が導電性接着剤で接合されてなり、半導体集積回路は圧電振動子の上方に配置され、パッケージの電極パターンと複数のバンプにより接合されてなるという構造により、半導体集積回路を内蔵する前にパッケージ全体を高温で処理することが可能であり、半導体集積回路の耐熱性に拘わらず、パッケージ内のガス抜き等のアニール処理に必要充分な高温での処理が行えるという効果を有する。
【００４５】
また、半導体集積回路を実装した後、半導体集積回路から露出した圧電振動子の一部を用いて周波数調整する構造により、高精度の圧電デバイスを安価に提供できるという効果を有する。
【００４６】
【図面の簡単な説明】
【図１】本発明の圧電デバイスの構造図。
（ａ）は、平面図。
（ｂ）は、正面図。
【図２】本発明の圧電デバイスの水晶振動子のマウント図。
【図３】本発明の圧電デバイスのバンプ形成図。
【図４】本発明の圧電デバイスの半導体集積回路と電極パターンとの接合部拡大図。
【図５】本発明の圧電デバイスへの周波数調整方法を示す図。
【図６】本発明の他の実施例を示す構造図。
【図７】従来の圧電デバイスの構造図。
（ａ）は、平面図。
（ｂ）は、正面図。
【符号の説明】
１ ベース
２ マウント部
３ ＡＴカット水晶振動子
４ 支持部
５ 導電性接着剤
６ ＩＣチップ
７ 電極パターン
８ バンプ
９ シールリング
１０ リッド
１１ 水晶発振器
１２ パッド
１３ Ａ部
２１ ベース
２２ マウント部
２３ 支持部
２４ バンプ
２５ ＡＴカット水晶振動子
２６ 導電性接着剤
１０１ ＩＣチップ
１０２ ベース
１０３ Ａｕワイヤーボンディング線
１０４ 入出力用電極
１０５ ＡＴカット水晶振動子
１０６ マウント部
１０７ シールリング
１０８ リッド[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a piezoelectric device in which a semiconductor integrated circuit and a piezoelectric vibrator are built in a package, and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, miniaturization and thinning of devices have been remarkable in small information devices such as HDDs (hard disk drives), mobile computers, and IC cards, and mobile communication devices such as mobile phones and automobile phones. Piezoelectric devices such as oscillators, voltage controlled oscillators (VCXO), temperature compensated oscillators (TCXO), SAW oscillators, and real-time clock modules are also required to be small and thin. In addition, there is a need for a surface-mount type piezoelectric device that can be mounted on both sides of the circuit board of the apparatus.
[0003]
Therefore, an example of a conventional piezoelectric device is shown in the structural diagrams of FIGS. 7A and 7B using a one-chip semiconductor integrated circuit having an oscillation circuit and an AT-cut crystal resonator as a piezoelectric resonator. This will be described using a crystal oscillator.
[0004]
7 (a) and 7 (b), the IC chip 101 having the oscillation circuit is bonded and fixed to the bottom surface of the base 102 formed of a ceramic insulating substrate with a conductive adhesive or the like. An Au wire bonding wire 103 is electrically connected to an input / output electrode 104 or the like that is metallized with a metal such as W (tungsten) or Mo (molybdenum) on the bottom peripheral portion of the base 102 and plated with Ni + Au.
[0005]
A rectangular AT-cut crystal resonator 105 is electrically connected and fixed to the mount portion 106 of the base 102 with a conductive adhesive or the like. The inside of the base 102 is kept in an N 2 (nitrogen) atmosphere or a vacuum atmosphere, and the uppermost seal ring 107 of the base 102 and the metal lid 108 are joined by seam welding and hermetically sealed.
[0006]
[Problems to be solved by the invention]
The conventional crystal oscillator described above requires an area for wiring the Au wire bonding line 103 around the IC chip 101. In addition, it is necessary to secure the loop height of the Au wire bonding wire 103 and the clearance between the Au wire bonding wire 103 and the AT cut crystal resonator 105 in the thickness direction of the package. This is a limitation for making the device small and thin.
[0007]
An object of the present invention is to solve the above-described problems of the prior art, and the object is to provide a piezoelectric device such as a crystal oscillator having a small and thin size and a thickness of 1 mm or less at a low cost. is there.
[0008]
[Means for Solving the Problems]
According to a first aspect of the present invention, in the piezoelectric device in which the semiconductor integrated circuit and the piezoelectric vibrator are built in the same package, the package is located on the first layer and the insulating substrate. A second layer of the first layer , wherein one surface of the first layer is opposed to one surface of the second layer, and the piezoelectric vibrator is electrically connected to the one surface of the first layer. The second layer is formed with a hole for accommodating the piezoelectric vibrator, and has a shape surrounding the piezoelectric vibrator, on the other surface of the second layer. A plurality of electrode patterns for connecting to the semiconductor integrated circuit are formed on both sides of the hole, and the semiconductor integrated circuit includes the plurality of electrode patterns and the plurality of electrode patterns on the second layer. Bonded by bumps and placed above the piezoelectric vibrator It is characterized in.
[0009]
According to a second aspect of the present invention, in the piezoelectric device in which the semiconductor integrated circuit and the piezoelectric vibrator are built in the same package, the package is located on the first layer and the insulating substrate. The first layer has one surface facing the one surface of the second layer, and a plurality of the piezoelectric vibrators on the one surface of the first layer. The second layer is formed with a hole for accommodating the piezoelectric vibrator and has a shape surrounding the piezoelectric vibrator, and is formed on the other surface of the second layer. A plurality of electrode patterns for connecting to the semiconductor integrated circuit are formed on both sides of the hole, and the semiconductor integrated circuit includes the plurality of electrode patterns and the plurality of bumps of the second layer. And is arranged above the piezoelectric vibrator. It is characterized in.
[0010]
According to a third aspect of the present invention, in the piezoelectric device according to the first or second aspect, the semiconductor integrated circuit and the piezoelectric vibrator are embedded in a package formed of a wiring board. It is arranged near the joint part of the child.
[0011]
According to a fourth aspect of the present invention, in the piezoelectric device in which the semiconductor integrated circuit and the piezoelectric vibrator are housed in a package formed of a wiring board in the first or second aspect, at least a part of the piezoelectric vibrator is a part of the semiconductor integrated circuit. It is characterized by being exposed to the outside.
[0012]
According to a fifth aspect of the present invention, the semiconductor integrated circuit and the piezoelectric vibrator are built in the same package, and the package includes a first layer made of an insulating substrate, and a first layer made of the insulating substrate located on the first layer. Two surfaces, and one surface of the first layer is opposed to one surface of the second layer, a mount portion is formed on the one surface of the first layer, and the second layer The layer is formed with a hole for accommodating the piezoelectric vibrator, has a shape surrounding the piezoelectric vibrator, and is formed on the other surface of the second layer on both sides of the hole. A method of manufacturing a piezoelectric device in which a plurality of electrode patterns for connecting to a semiconductor integrated circuit are formed, the step of bonding the piezoelectric vibrator to the mount portion, and the semiconductor integrated circuit to the plurality of electrode patterns Bonded with bumps to expose part of the piezoelectric vibrator A step of arranging the semiconductor circuit at a position above the piezoelectric vibrator and a step of adjusting the frequency using the part of the piezoelectric vibrator exposed from the semiconductor integrated circuit. And According to a sixth aspect of the present invention, the semiconductor integrated circuit and the piezoelectric vibrator are built in the same package, and the package includes a first layer made of an insulating substrate, and a first layer made of the insulating substrate located on the first layer. Two surfaces, and one surface of the first layer is opposed to one surface of the second layer, a mount portion is formed on the one surface of the first layer, and the second layer The layer is formed with a hole for accommodating the piezoelectric vibrator, has a shape surrounding the piezoelectric vibrator, and is formed on the other surface of the second layer on both sides of the hole. A method of manufacturing a piezoelectric device in which a plurality of electrode patterns for connection to a semiconductor integrated circuit are formed, the step of joining the piezoelectric vibrator to the mount portion with a conductive adhesive, and the entire package at a high temperature in the annealing process, the semiconductor integrated circuit, A step of joining the bumps serial plurality of electrode patterns arranged above the piezoelectric vibrator, and performs in sequence.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
One embodiment of a piezoelectric device of the present invention will be described with reference to the drawings, taking as an example a crystal oscillator using a one-chip semiconductor integrated circuit having an oscillation circuit and an AT-cut crystal resonator as a piezoelectric resonator.
[0014]
Example 1
FIG. 1 is a structural diagram of a surface-mount type crystal oscillator according to the first, third, fourth, and fifth aspects of the present invention.
[0015]
As shown in the plan view of FIG. 1 (a) and the front view of FIG. 1 (b), it is formed of a ceramic insulating substrate composed of at least three layers and a seal ring die-cut in a frame shape with an Fe—Ni alloy or the like. The AT cut quartz crystal resonator 3 is connected and fixed to the mount portion 2 provided on the first layer of the base 1 by the conductive adhesive 5.
[0016]
On the second layer of the base 1, an electrode pattern 7 for connecting to a semiconductor integrated circuit (IC chip: hereinafter referred to as IC chip) 6 is printed with a metal wiring material such as W (tungsten) or Mo (molybdenum). It is metallized by etc. And Ni plating, Au plating, etc. are given on it.
[0017]
Further, bumps 8 made of metal such as Au are formed on the electrode pads of the IC chip 6 and connected to the electrode pattern 7 formed on the base 1 by a flip chip bonding method. There are various processing methods for this flip chip bonding method, but the method used in this example is a processing method using a conductive adhesive in the connection portion.
[0018]
Further, a metal lid (lid) 10 is positioned and fixed to a seal ring 9 die-cut in a frame shape with an Fe—Ni alloy or the like of the base 1 and hermetically sealed by seam welding.
[0019]
As described above, the crystal oscillator 11 of a small and thin surface mount package is completed.
[0020]
Next, each mounting process of the AT cut crystal resonator 3 and the IC chip 6 will be described in detail.
[0021]
As shown in FIG. 2, an appropriate amount of conductive adhesive 5 is applied to the mount portion 2 provided on the first layer of the base 1 with a dispensing device or the like. Then, the AT cut crystal resonator 3 is image-recognized by a device for mounting the crystal resonator, and the support portion 4 is bonded to the conductive adhesive 5 of the mount portion 2.
[0022]
Next, in order to cure the conductive adhesive 5, the entire package including the AT-cut crystal resonator 3 is processed at a high temperature. This also has an annealing effect for removing outgas from the conductive adhesive 5, the base 1, or the AT-cut quartz crystal resonator 3, and is generally processed at a high temperature of 200 ° C. to 350 ° C. for 1 to 2 hours. Is called.
[0023]
In particular, this annealing process is very important for piezoelectric devices that require high precision or high frequency such as high precision crystal oscillators, voltage controlled crystal oscillators (VCXO), temperature compensated crystal oscillators (TCXO), and SAW oscillators. . Such a piezoelectric device has a problem in that the presence of a small amount of gas or the like in the atmosphere of the package in which the AT-cut quartz crystal resonator 3 is built, the frequency accuracy deteriorates and stable oscillation characteristics cannot be obtained. .
[0024]
However, according to the present embodiment, the entire package can be processed at a high temperature before the IC chip 6 is built in, and sufficient high-temperature processing necessary for the annealing process can be performed regardless of the heat resistance problem of the IC chip 6. Yes.
[0025]
Next, a bump forming process for forming the bump 8 formed of Au or the like on the IC chip 6 and a flip chip bonding process for connecting the IC chip 6 to the electrode pattern 7 formed on the base 1 will be described in detail. .
[0026]
For example, as shown in FIG. 3, a plurality of bumps are formed on each pad 12 of an IC chip 6 in a wafer state of 4 inches to 6 inches by ultrasonic bump bonding using Au bonding fine wires having a wire diameter of about Φ25 to 35 μm. 8 is formed.
[0027]
Further, since bump formation is performed on a plurality (several thousands) of IC chips 6 in a wafer state, it is desirable that the temperature of the bump formation is low. In this embodiment, bump formation is performed at a temperature of about 180 ° C. Is going. About this temperature, the range of about 180 ° C. to 230 ° C. is appropriate according to the evaluation test of the bonding strength and the degree of Au—Al eutectic.
[0028]
Next, the process of flip chip bonding the IC chip 6 on which the bumps 8 are formed by the above process to the base 1 will be described in detail.
[0029]
As shown in the enlarged view of the flip chip bonding in FIG. 4, the IC chip 6 on the wafer is picked up by a nozzle such as a pyramid collet, inverted, and transferred to the bonding nozzle. Then, an appropriate amount of a conductive adhesive 12 having a high stress relaxation action is attached to the tip of the bump 8, and the IC chip 6 is aligned with high accuracy by the system such as image recognition provided in the flip chip bonding apparatus. Chip mounted in the mount area.
[0030]
The IC chip 6 is disposed at a position where a part of the AT cut crystal resonator 3 is exposed and above the AT cut crystal resonator 3.
[0031]
Here, the conductive adhesive 12 used in this embodiment is a silicon-based silver paste. The silicon-based conductive adhesive 12 has good heat resistance and is very stable even when left at high temperatures with little deterioration in properties. Moreover, the action which relieves the stress which acts on the joining interface of the bump 8 is high, and it is possible to obtain a highly reliable joint as compared with other conductive adhesives such as epoxy.
[0032]
Further, the flip chip bonding apparatus is provided with a sensor for detecting the height direction of the IC chip 6, and it is possible to process the height of the bump 8 in a uniform state while managing the data in the height direction. It is.
[0033]
Here, the processing conditions used in the present embodiment apply a load of around 100 grams per bump.
[0034]
Then, the entire package including the IC chip 6 and the AT-cut quartz crystal resonator 3 including the curing of the conductive adhesive 12 is heat-treated at a high temperature of 150 ° C. to 180 ° C.
[0035]
Here, there are various methods for bonding the bumps 8 to the base 1, and methods other than this example, such as Au-Au bonding by ultrasonic waves or high temperature and pressure, or film-like adhesives such as ACF are used. The processing method used may be used.
[0036]
Next, a process for adjusting the frequency of the AT-cut crystal resonator 3 will be described in detail.
[0037]
As shown in FIG. 5, processing for adjusting the frequency of the AT-cut quartz crystal resonator 3 is performed on the A portion 13 of the AT-cut quartz crystal resonator 3 exposed from the IC chip 6 by a vacuum vapor deposition method or a plasma etching method. The circuit constants of the IC chip 6 are adjusted by adjusting the frequency to the A portion 13 of the AT cut crystal resonator 3 in a state where the power supply voltage is applied to the IC chip 6 and the AT cut crystal resonator 3 is oscillated. The frequency can be adjusted with high accuracy and matching.
[0038]
Further, a metal lid 10 is positioned and fixed to a seal ring 9 die-cut in a frame shape with an Fe—Ni alloy or the like of the base 1 and hermetically sealed by seam welding.
[0039]
(Example 2)
FIG. 6 is a structural view showing the structure of a crystal oscillator according to another embodiment of the present invention.
[0040]
As shown in FIG. 6, an AT-cut quartz crystal resonator 25 in which a plurality of bumps 24 are formed on a support portion 23 is image-recognized on the mount portion 22 provided in the first layer of the base 21, and the tip of the bump 24 is recognized. Bonded by the attached conductive adhesive 26.
[0041]
Here, there are various methods for bonding the bumps 24 to the base 21. Methods other than the present embodiment, such as Au-Au bonding by ultrasonic waves or high temperature and pressure, or a film-like adhesive such as ACF are used. The processing method used may be used.
[0042]
As described above, by using high-reliability and inexpensive components such as ceramic and metal, a small and thin high reliability of 2 to 3.2 mm in width, 2 to 2.5 mm in width, and 0.7 to 1.0 mm in thickness. Can be provided at low cost.
[0043]
As described above, the crystal oscillator using the one-chip semiconductor integrated circuit having the oscillation circuit and the AT-cut crystal resonator as the piezoelectric resonator has been described as an example. However, the present invention is not limited thereto, and for example, the voltage The present invention can be applied to all piezoelectric devices incorporating a semiconductor integrated circuit such as a controlled crystal oscillator (VCXO), a temperature compensated crystal oscillator (TCXO), a SAW oscillator, or a real-time clock module. Furthermore, the present invention can be similarly applied to a piezoelectric device in which a crystal resonator chip or a SAW chip is mounted on a package by flip chip bonding.
[0044]
【The invention's effect】
According to the first, second, third, fourth, and fifth inventions, the piezoelectric vibrator is joined to the package with the conductive adhesive, the semiconductor integrated circuit is disposed above the piezoelectric vibrator, and the electrode of the package The structure in which the pattern and multiple bumps are joined allows the entire package to be processed at a high temperature before the semiconductor integrated circuit is built in, and the package can be degassed regardless of the heat resistance of the semiconductor integrated circuit. For example, it has an effect that it can be processed at a high temperature necessary and sufficient for the annealing process.
[0045]
In addition, after mounting the semiconductor integrated circuit, a structure in which the frequency is adjusted using a part of the piezoelectric vibrator exposed from the semiconductor integrated circuit has an effect that a highly accurate piezoelectric device can be provided at low cost.
[0046]
[Brief description of the drawings]
FIG. 1 is a structural diagram of a piezoelectric device of the present invention.
(A) is a top view.
(B) is a front view.
FIG. 2 is a mount diagram of a crystal resonator of the piezoelectric device of the present invention.
FIG. 3 is a bump formation diagram of the piezoelectric device of the present invention.
FIG. 4 is an enlarged view of a joint portion between a semiconductor integrated circuit and an electrode pattern of the piezoelectric device of the present invention.
FIG. 5 is a diagram showing a frequency adjustment method for a piezoelectric device according to the present invention.
FIG. 6 is a structural diagram showing another embodiment of the present invention.
FIG. 7 is a structural diagram of a conventional piezoelectric device.
(A) is a top view.
(B) is a front view.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Base 2 Mount part 3 AT cut crystal oscillator 4 Support part 5 Conductive adhesive 6 IC chip 7 Electrode pattern 8 Bump 9 Seal ring 10 Lid 11 Crystal oscillator 12 Pad 13 A part 21 Base 22 Mount part 23 Support part 24 Bump 25 AT cut crystal resonator 26 Conductive adhesive 101 IC chip 102 Base 103 Au wire bonding line 104 Input / output electrode 105 AT cut crystal resonator 106 Mount portion 107 Seal ring 108 Lid

Claims (6)

半導体集積回路と圧電振動子とを同一のパッケージに内蔵した圧電デバイスにおいて、
前記パッケージは、絶縁基板からなる第１層と、前記第１層上に位置し絶縁基板からなる第２層とを有し、
前記第１層の一方の面は、前記第２層の一方の面に相対しており、
前記第１層の前記一方の面に前記圧電振動子が導電性接着剤で接合されてなり、
前記第２層は、前記圧電振動子を収容する孔が形成され、前記圧電振動子を囲う形状を有しており、
前記第２層の他方の面上であって前記孔を挟んだ両側の領域に、前記半導体集積回路と接続するための複数の電極パターンが形成されており、
前記半導体集積回路は、前記第２層の前記複数の電極パターンと複数のバンプにより接合されて前記圧電振動子の上方に配置されていることを特徴とする圧電デバイス。In a piezoelectric device in which a semiconductor integrated circuit and a piezoelectric vibrator are built in the same package,
The package has a first layer made of an insulating substrate, and a second layer made of an insulating substrate and located on the first layer,
One surface of the first layer is opposite to one surface of the second layer;
The piezoelectric vibrator is bonded to the one surface of the first layer with a conductive adhesive,
The second layer is formed with a hole for accommodating the piezoelectric vibrator, and has a shape surrounding the piezoelectric vibrator,
A plurality of electrode patterns for connecting to the semiconductor integrated circuit are formed on the other side of the second layer and on both sides of the hole ,
2. The piezoelectric device according to claim 1, wherein the semiconductor integrated circuit is bonded to the plurality of electrode patterns of the second layer by a plurality of bumps and disposed above the piezoelectric vibrator. 半導体集積回路と圧電振動子とを同一のパッケージに内蔵した圧電デバイスにおいて、
前記パッケージは、絶縁基板からなる第１層と、前記第１層上に位置し絶縁基板からなる第２層とを有し、
前記第１層の一方の面は、前記第２層の一方の面に相対しており、
前記第１層の前記一方の面に前記圧電振動子が複数のバンプで接合されてなり、
前記第２層は、前記圧電振動子を収容する孔が形成され、前記圧電振動子を囲う形状を有しており、
前記第２層の他方の面上であって前記孔を挟んだ両側の領域に、前記半導体集積回路と接続するための複数の電極パターンが形成されており、
前記半導体集積回路は、前記第２層の前記複数の電極パターンと複数のバンプにより接合されて前記圧電振動子の上方に配置されていることを特徴とする圧電デバイス。In a piezoelectric device in which a semiconductor integrated circuit and a piezoelectric vibrator are built in the same package,
The package has a first layer made of an insulating substrate, and a second layer made of an insulating substrate and located on the first layer,
One surface of the first layer is opposite to one surface of the second layer;
The piezoelectric vibrator is bonded to the one surface of the first layer with a plurality of bumps,
The second layer is formed with a hole for accommodating the piezoelectric vibrator, and has a shape surrounding the piezoelectric vibrator,
A plurality of electrode patterns for connecting to the semiconductor integrated circuit are formed on the other side of the second layer and on both sides of the hole .
2. The piezoelectric device according to claim 1, wherein the semiconductor integrated circuit is bonded to the plurality of electrode patterns of the second layer by a plurality of bumps and disposed above the piezoelectric vibrator. 前記半導体集積回路は前記圧電振動子の上方かつ前記圧電振動子の接合部付近に配置されてなることを特徴とする請求項１または２に記載の圧電デバイス。  3. The piezoelectric device according to claim 1, wherein the semiconductor integrated circuit is disposed above the piezoelectric vibrator and in the vicinity of a joint portion of the piezoelectric vibrator. 少なくとも前記圧電振動子の一部は前記半導体集積回路の外部に露出してなることを特徴とする請求項１または２に記載の圧電デバイス。  3. The piezoelectric device according to claim 1, wherein at least a part of the piezoelectric vibrator is exposed to the outside of the semiconductor integrated circuit. 半導体集積回路と圧電振動子とを同一のパッケージに内蔵し、
前記パッケージは、絶縁基板からなる第１層と、前記第１層上に位置し絶縁基板からなる第２層とを有し、
前記第１層の一方の面は、前記第２層の一方の面に相対しており、
前記第１層の前記一方の面にマウント部が形成され、
前記第２層は前記圧電振動子を収容する孔が形成され、前記圧電振動子を囲う形状を有しており、
前記第２層の他方の面上であって前記孔を挟んだ両側の領域に、前記半導体集積回路と接続するための複数の電極パターンが形成されている圧電デバイスの製造方法であって、
前記マウント部に前記圧電振動子を接合する工程と、
前記半導体集積回路を前記複数の電極パターンにバンプにより接合し、前記圧電振動子の一部を露出した位置で且つ前記圧電振動子の上方に前記半導体回路を配置する工程と、
前記半導体集積回路から露出した前記圧電振動子の前記一部を用いて周波数調整する工程と、
を順に行うことを特徴とする圧電デバイスの製造方法。Built- in semiconductor integrated circuit and piezoelectric vibrator in the same package ,
The package has a first layer made of an insulating substrate, and a second layer made of an insulating substrate and located on the first layer,
One surface of the first layer is opposite to one surface of the second layer;
A mount portion is formed on the one surface of the first layer;
The second layer is formed with a hole for accommodating the piezoelectric vibrator, and has a shape surrounding the piezoelectric vibrator,
A method of manufacturing a piezoelectric device in which a plurality of electrode patterns for connecting to the semiconductor integrated circuit are formed on both sides of the second layer and on both sides of the hole,
Bonding the piezoelectric vibrator to the mount portion;
Bonding the semiconductor integrated circuit to the plurality of electrode patterns by bumps, and disposing the semiconductor circuit at a position where a part of the piezoelectric vibrator is exposed and above the piezoelectric vibrator;
Adjusting the frequency using the part of the piezoelectric vibrator exposed from the semiconductor integrated circuit;
A method for manufacturing a piezoelectric device, wherein the steps are performed in order. 半導体集積回路と圧電振動子とを同一のパッケージに内蔵し、
前記パッケージは、絶縁基板からなる第１層と、前記第１層上に位置し絶縁基板からなる第２層とを有し、
前記第１層の一方の面は、前記第２層の一方の面に相対しており、
前記第１層の前記一方の面にマウント部が形成され、
前記第２層は前記圧電振動子を収容する孔が形成され、前記圧電振動子を囲う形状を有しており、
前記第２層の他方の面上であって前記孔を挟んだ両側の領域に、前記半導体集積回路と接続するための複数の電極パターンが形成されている圧電デバイスの製造方法であって、
前記マウント部に前記圧電振動子を導電性接着剤により接合する工程と、
前記パッケージ全体を高温でアニール処理する工程と、
前記半導体集積回路を、前記複数の電極パターンにバンプにより接合し前記圧電振動子の上方に配置する工程と、
を順に行うことを特徴とする圧電デバイスの製造方法。Built- in semiconductor integrated circuit and piezoelectric vibrator in the same package ,
The package has a first layer made of an insulating substrate, and a second layer made of an insulating substrate and located on the first layer,
One surface of the first layer is opposite to one surface of the second layer;
A mount portion is formed on the one surface of the first layer;
The second layer is formed with a hole for accommodating the piezoelectric vibrator, and has a shape surrounding the piezoelectric vibrator,
A method of manufacturing a piezoelectric device in which a plurality of electrode patterns for connecting to the semiconductor integrated circuit are formed on both sides of the second layer and on both sides of the hole,
And bonding with a conductive adhesive said piezoelectric vibrator to the mounting portion,
Annealing the entire package at a high temperature;
Bonding the semiconductor integrated circuit to the plurality of electrode patterns by a bump and disposing the semiconductor integrated circuit above the piezoelectric vibrator;
A method for manufacturing a piezoelectric device, wherein the steps are performed in order.
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