JP2001237317A5 - - Google Patents

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Publication number
JP2001237317A5
JP2001237317A5 JP2000044014A JP2000044014A JP2001237317A5 JP 2001237317 A5 JP2001237317 A5 JP 2001237317A5 JP 2000044014 A JP2000044014 A JP 2000044014A JP 2000044014 A JP2000044014 A JP 2000044014A JP 2001237317 A5 JP2001237317 A5 JP 2001237317A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000044014A
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JP2001237317A (ja
JP4629826B2 (ja
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Publication date
Application filed filed Critical
Priority to JP2000044014A priority Critical patent/JP4629826B2/ja
Priority claimed from JP2000044014A external-priority patent/JP4629826B2/ja
Priority to US09/781,233 priority patent/US6560759B2/en
Publication of JP2001237317A publication Critical patent/JP2001237317A/ja
Publication of JP2001237317A5 publication Critical patent/JP2001237317A5/ja
Application granted granted Critical
Publication of JP4629826B2 publication Critical patent/JP4629826B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000044014A 2000-02-22 2000-02-22 半導体集積回路装置 Expired - Fee Related JP4629826B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000044014A JP4629826B2 (ja) 2000-02-22 2000-02-22 半導体集積回路装置
US09/781,233 US6560759B2 (en) 2000-02-22 2001-02-13 Semiconductor integrated circuit device, design method for the same and computer-readable recording where medium I/O cell library is recorded

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000044014A JP4629826B2 (ja) 2000-02-22 2000-02-22 半導体集積回路装置

Publications (3)

Publication Number Publication Date
JP2001237317A JP2001237317A (ja) 2001-08-31
JP2001237317A5 true JP2001237317A5 (ja) 2007-04-05
JP4629826B2 JP4629826B2 (ja) 2011-02-09

Family

ID=18566845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000044014A Expired - Fee Related JP4629826B2 (ja) 2000-02-22 2000-02-22 半導体集積回路装置

Country Status (2)

Country Link
US (1) US6560759B2 (ja)
JP (1) JP4629826B2 (ja)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003031710A (ja) * 2001-07-12 2003-01-31 Mitsumi Electric Co Ltd モノリシックｉｃパッケージ
US7332817B2 (en) * 2004-07-20 2008-02-19 Intel Corporation Die and die-package interface metallization and bump design and arrangement
US7291930B2 (en) * 2005-02-23 2007-11-06 Faraday Technology Corp. Input and output circuit of an integrated circuit chip
JP5000130B2 (ja) * 2005-12-16 2012-08-15 ローム株式会社 半導体チップ
US20070187808A1 (en) * 2006-02-16 2007-08-16 Easic Corporation Customizable power and ground pins
US8247845B2 (en) * 2008-01-28 2012-08-21 Infineon Technologies Ag Electrostatic discharge (ESD) protection circuit placement in semiconductor devices
US7838959B2 (en) * 2008-01-29 2010-11-23 Infineon Technologies Ag Radio frequency (RF) circuit placement in semiconductor devices
US20100148218A1 (en) * 2008-12-10 2010-06-17 Panasonic Corporation Semiconductor integrated circuit device and method for designing the same
KR20120041237A (ko) 2009-08-04 2012-04-30 갠 시스템즈 인크. 아일랜드 매트릭스 갈륨 나이트라이드 마이크로파 및 전력 트랜지스터
US9029866B2 (en) * 2009-08-04 2015-05-12 Gan Systems Inc. Gallium nitride power devices using island topography
US9818857B2 (en) 2009-08-04 2017-11-14 Gan Systems Inc. Fault tolerant design for large area nitride semiconductor devices
JP2011171680A (ja) 2010-02-22 2011-09-01 Panasonic Corp 半導体集積回路装置
US8791508B2 (en) * 2010-04-13 2014-07-29 Gan Systems Inc. High density gallium nitride devices using island topology
JP6401842B2 (ja) * 2012-11-28 2018-10-10 ルネサスエレクトロニクス株式会社 半導体集積回路
JP6215645B2 (ja) * 2012-11-28 2017-10-18 ルネサスエレクトロニクス株式会社 半導体集積回路

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2742052B2 (ja) * 1987-06-12 1998-04-22 日本電信電話株式会社 相補型ｍｉｓマスタスライス論理集積回路
JPH01123433A (ja) * 1987-11-07 1989-05-16 Mitsubishi Electric Corp バス信号配線構造ゲートアレイ
US4988636A (en) * 1990-01-29 1991-01-29 International Business Machines Corporation Method of making bit stack compatible input/output circuits
JP3111533B2 (ja) * 1991-09-20 2000-11-27 富士通株式会社 半導体集積回路
JPH05218204A (ja) 1992-02-05 1993-08-27 Fujitsu Ltd 半導体集積回路
US5535084A (en) * 1992-07-24 1996-07-09 Kawasaki Steel Corporation Semiconductor integrated circuit having protection circuits
JP2830783B2 (ja) 1995-07-18 1998-12-02 日本電気株式会社 半導体装置
US5760428A (en) * 1996-01-25 1998-06-02 Lsi Logic Corporation Variable width low profile gate array input/output architecture
US6169329B1 (en) * 1996-04-02 2001-01-02 Micron Technology, Inc. Semiconductor devices having interconnections using standardized bonding locations and methods of designing
JP3610259B2 (ja) * 1998-05-13 2005-01-12 セイコーエプソン株式会社 回路基板の配線経路決定方法、装置及び情報記憶媒体
KR100471695B1 (ko) * 1998-05-13 2005-03-08 세이코 엡슨 가부시키가이샤 회로 기판의 배선 경로 결정 방법, 장치 및 정보 기억 매체
JP2000012697A (ja) * 1998-06-23 2000-01-14 Mitsubishi Electric Corp 半導体チップ構造およびその設計方法
US6104588A (en) * 1998-07-31 2000-08-15 National Semiconductor Corporation Low noise electrostatic discharge protection circuit for mixed signal CMOS integrated circuits
US6140682A (en) * 1999-07-09 2000-10-31 Macronix International Co., Ltd. Self protected stacked NMOS with non-silicided region to protect mixed-voltage I/O pad from ESD damage

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