JP2001228191A - Lsi soldered joint structure, and lsi soldered part abnormal joint detecting method used for it - Google Patents

Lsi soldered joint structure, and lsi soldered part abnormal joint detecting method used for it

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Publication number
JP2001228191A
JP2001228191A JP2000037338A JP2000037338A JP2001228191A JP 2001228191 A JP2001228191 A JP 2001228191A JP 2000037338 A JP2000037338 A JP 2000037338A JP 2000037338 A JP2000037338 A JP 2000037338A JP 2001228191 A JP2001228191 A JP 2001228191A
Authority
JP
Japan
Prior art keywords
connection
lsi
solder
joint
abnormality
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000037338A
Other languages
Japanese (ja)
Inventor
Hisatsugu Harada
久嗣 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2000037338A priority Critical patent/JP2001228191A/en
Publication of JP2001228191A publication Critical patent/JP2001228191A/en
Pending legal-status Critical Current

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an LSI soldered part abnormal joint detecting method allowing a soldered joint condition to be monitored in any time during operation of LSI and an abnormal joint to be detected in its early stages. SOLUTION: Joint checking solder balls 3, 4 are arranged in optional positions in the outermost circumference part of BGA 1, which is considered to have a short soldered joint lifetime theoretically because of application of the highest mechanical stress, and electrically connected to PWB 8 by means of solder. The joint checking solder ball 3 is electrically connected to the GND, and connected to the joint checking solder ball 4 via LSI internal wiring 2. The joint checking solder ball 4 is pulled up by means of a resistor 9 so as to be connected to one end (+) of a comparator 10. A reference power source Vref is connected to the other end (-) of the comparator 10. The output of the comparator 10 is connected to a soldered joint part monitoring part 11 detecting abnormal joint between the soldered joint parts 7a, 7b, and an output of the joint part monitoring part 11 is connected to a device control unit 12.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はLSIはんだ接続構
造及びそれに用いるLSIはんだ付け部接続異常検出方
法に関し、特にBGA(Ball Grid Arra
y)等をはんだ付けでPWB(Printed Wir
ing Board)と接続する場合の接続異常を検出
する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI solder connection structure and a method of detecting an abnormal connection of an LSI soldering portion used in the structure, and more particularly to a BGA (Ball Grid Array).
y) etc. by soldering to PWB (Printed Wir
The present invention relates to a method of detecting a connection abnormality when connecting to an Internet connection (ing Board).

【0002】[0002]

【従来の技術】従来、はんだ付けの良否の判定は、はん
だ盛付け状態を外観によって判定するか、必要に応じて
低電圧を流し、その電圧降下によって判定している。ま
た、はんだ盛付け状態の検査は管能検査の一つである外
観検査によって行われ、盛付け状態を示す限度見本等を
使用して行われており、そのために使用する特別な検査
装置はない。
2. Description of the Related Art Conventionally, the quality of soldering is determined by the appearance of a soldering state based on its appearance or by applying a low voltage as required, and the voltage drop. In addition, the inspection of the soldering condition is performed by visual inspection, which is one of the functional tests, and is performed using a limit sample or the like that indicates the soldering condition, and there is no special inspection device used for that purpose. .

【0003】さらに、接続良否を検査する検査装置は、
乾電池と電圧計もしくは電流計を組合せた簡単な装置が
使用されている。これらはんだ付け接続欠陥の検査方法
については、特開平6−18463号公報等に開示され
ているが、これらはいずれも製造直後の検査方法であ
る。
Further, an inspection device for inspecting connection quality is
A simple device combining a dry cell and a voltmeter or ammeter is used. Methods for inspecting these soldering connection defects are disclosed in Japanese Patent Application Laid-Open No. 6-18463, etc., but these are all inspection methods immediately after production.

【0004】一般的に、BGA等をはんだ付けでPWB
と接続する場合、はんだ付け寿命がBGAを実装したパ
ッケージの寿命決定の一要因になっている。しかしなが
ら、はんだ付け寿命は機械的、構造的な寿命であるた
め、動作中に継続的に接続状態をモニタしていない。
Generally, BGA or the like is soldered to PWB.
When connecting to a BGA, the soldering life is a factor in determining the life of the package on which the BGA is mounted. However, since the soldering life is a mechanical and structural life, the connection state is not continuously monitored during operation.

【0005】[0005]

【発明が解決しようとする課題】上述した従来のはんだ
付け部接続異常検出方法では、動作中に継続的に接続状
態をモニタしていないので、高信頼性を求められる装置
において、運用中のはんだ接続寿命(劣化)による装置
故障を極力避ける必要がある場合に、その故障発生前に
対応することができない。
In the above-described conventional method for detecting a connection abnormality of a soldered portion, the connection state is not continuously monitored during operation. When it is necessary to avoid device failure due to connection life (deterioration) as much as possible, it is not possible to respond before the failure occurs.

【0006】そこで、本発明の目的は上記の問題点を解
消し、LSI動作中の随時においてはんだ接続状態をモ
ニタすることができ、接続異常を早期に発見することが
できるLSIはんだ接続構造及びそれに用いるLSIは
んだ付け部接続異常検出方法を提供することにある。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problems, to monitor a solder connection state at any time during LSI operation, and to detect an abnormal connection at an early stage. An object of the present invention is to provide an LSI soldering portion connection abnormality detection method to be used.

【0007】[0007]

【課題を解決するための手段】本発明によるLSIはん
だ接続構造は、大規模集積回路の基板への電気的接続を
行うためのLSIはんだ接続構造であって、前記大規模
集積回路と前記基板との熱膨張差によって機械的応力が
一番大きい前記大規模集積回路の最外周部に配置されか
つその最外周部における接続異常を検出するためのはん
だ接続部材を備え、前記はんだ接続部材の接続異常を検
出するようにしている。
An LSI solder connection structure according to the present invention is an LSI solder connection structure for electrically connecting a large-scale integrated circuit to a substrate, wherein the large-scale integrated circuit is connected to the substrate. A solder connecting member disposed at the outermost peripheral portion of the large-scale integrated circuit having the largest mechanical stress due to a difference in thermal expansion and detecting a connection abnormality at the outermost peripheral portion, and a connection abnormality of the solder connecting member. Is to be detected.

【0008】本発明によるLSIはんだ付け部接続異常
検出方法は、大規模集積回路の基板への電気的接続を行
うためのLSIはんだ接続構造におけるLSIはんだ付
け部接続異常検出方法であって、前記大規模集積回路と
前記基板との熱膨張差によって機械的応力が一番大きい
前記大規模集積回路の最外周部における接続異常を検出
するためのはんだ接続部材を当該最外周部に配置し、前
記はんだ接続部材の接続異常を検出するようにしてい
る。
The method for detecting an abnormal connection of an LSI soldering portion according to the present invention is a method for detecting an abnormal connection of an LSI soldering portion in an LSI solder connection structure for electrically connecting a large-scale integrated circuit to a substrate. A solder connection member for detecting a connection abnormality at an outermost peripheral portion of the large-scale integrated circuit having the largest mechanical stress due to a difference in thermal expansion between the large-scale integrated circuit and the substrate is arranged at the outermost peripheral portion, and the solder The connection abnormality of the connection member is detected.

【0009】すなわち、本発明のLSIはんだ付け部接
続異常検出方法は、LSI(大規模集積回路)の電気的
接続を行うためのはんだ接続構造において、接続異常を
検出するはんだ接続ピン(ボール)を有し、接続異常を
検出時、異常を装置の上位制御部に連絡し、接続寿命を
把握して装置故障を防ぐことを特徴とする。
That is, the method for detecting an abnormal connection of an LSI soldering portion according to the present invention uses a solder connection pin (ball) for detecting an abnormal connection in a solder connection structure for electrically connecting an LSI (large-scale integrated circuit). When a connection abnormality is detected, the abnormality is reported to a higher-level control unit of the apparatus, the connection life is grasped, and the apparatus is prevented from malfunctioning.

【0010】より具体的に、本発明のLSIはんだ付け
部接続異常検出方法は、BGAとPWBとの熱膨張差に
よって機械的応力が一番大きく、そのため、理論的には
んだ接続寿命の低いとされる最外周部の接続異常を電気
的にインピダンス変化としてとらえ、LSI動作中の随
時において、はんだ接続状態をモニタすることを可能と
し、接続異常の早期発見を可能としている。
More specifically, in the method for detecting an abnormality in connection of an LSI soldering portion of the present invention, the mechanical stress is the largest due to the difference in thermal expansion between the BGA and the PWB. The connection abnormality at the outermost peripheral portion is electrically regarded as a change in impedance, so that the solder connection state can be monitored at any time during the operation of the LSI, thereby enabling early detection of the connection abnormality.

【0011】つまり、接続異常の検出ポイントを接続寿
命の短い最外周としているため、信号用ボール部分が接
続寿命の限界に到達する前に、はんだ付け異常の発生を
予測可能となり、信号用接続断線によるシステム動作断
の前に対策を実施することが可能となる。
In other words, since the connection failure detection point is located at the outermost periphery where the connection life is short, it is possible to predict the occurrence of soldering failure before the signal ball portion reaches the limit of the connection life. It is possible to take countermeasures before the interruption of the system operation due to.

【0012】[0012]

【発明の実施の形態】次に、本発明の一実施例について
図面を参照して説明する。図1は本発明の一実施例によ
るLSIはんだ付け部接続異常検出方法を示す概念図で
ある。図1において、接続確認用はんだボール3,4は
BGA1とPWB8との熱膨張差によって機械的応力が
一番大きく、そのため、理論的にはんだ接続寿命の低い
とされるBGA1の最外周部の任意の場所に配置され、
PWB8にはんだを用いて電気的に接続されている(は
んだ接続部7a,7b)。
Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a conceptual diagram showing a method for detecting an abnormal connection of an LSI soldering portion according to an embodiment of the present invention. In FIG. 1, the solder balls 3 and 4 for confirming connection have the largest mechanical stress due to the difference in thermal expansion between the BGA 1 and the PWB 8, and therefore, any part of the outermost periphery of the BGA 1 which is theoretically considered to have a short solder connection life. Is located at
It is electrically connected to the PWB 8 using solder (solder connection portions 7a and 7b).

【0013】接続確認用はんだボール3は電気的にGN
D(グランド)に接続され、LSI内配線2を通して接
続確認用はんだボール4に接続されている。接続確認用
はんだボール4は抵抗9によってプルアップされ、コン
パレータ10の一端(+)に接続されている。コンパレ
ータ10の他端(−)には基準電源(Vref)が接続
されている。
The connection confirmation solder balls 3 are electrically GN
D (ground), and connected to the connection confirming solder ball 4 through the wiring 2 in the LSI. The connection confirmation solder ball 4 is pulled up by a resistor 9 and connected to one end (+) of a comparator 10. The other end (−) of the comparator 10 is connected to a reference power supply (Vref).

【0014】コンパレータ10の出力にはその出力をモ
ニタし、はんだ接続部7a,7bの接続異常(高インピ
ダンス、開放)を検出するはんだ接続部監視部11が接
続され、接続部監視部11の出力はその検出した接続異
常情報から、接続確認用はんだボール3,4と比較して
接続寿命の長い信号用はんだボール5,6の接続寿命を
保持できる間に、部品交換依頼を要求する装置制御部1
2へ接続されている。
The output of the comparator 10 is connected to a solder connection monitor 11 for monitoring the output and detecting connection abnormalities (high impedance, open) of the solder connections 7a and 7b. Is a device control unit for requesting a component replacement request while maintaining the connection life of the signal solder balls 5, 6 having a longer connection life than the connection confirmation solder balls 3, 4 based on the detected connection abnormality information. 1
2 is connected.

【0015】図2は図1のコンパレータ10の異常発生
時における信号波形を示す信号波形図である。これら図
1及び図2を参照して本発明の一実施例によるLSIは
んだ付け部接続異常検出方法の動作について説明する。
FIG. 2 is a signal waveform diagram showing a signal waveform when an abnormality occurs in the comparator 10 of FIG. The operation of the LSI soldering portion connection abnormality detecting method according to one embodiment of the present invention will be described with reference to FIGS.

【0016】はんだ付け不良が未発生の場合、コンパレ
ータ10の(+)側入力端子は接続確認用はんだボール
4、はんだ接続部7b、LSI内配線2、接続確認用は
んだボール3、はんだ接続部7aを介してGNDに接続
されており、電位は0Vである。
When no soldering failure has occurred, the (+) side input terminal of the comparator 10 is a connection confirmation solder ball 4, a solder connection portion 7b, an LSI wiring 2, a connection confirmation solder ball 3, and a solder connection portion 7a. , And the potential is 0V.

【0017】また、コンパレータ10の(−)端子側は
Vref電圧(Vcc>Vref)に設定されている。
これによって、コンパレータ10の出力は“L”レベル
になっている。
The (-) terminal side of the comparator 10 is set to a Vref voltage (Vcc> Vref).
As a result, the output of the comparator 10 is at the “L” level.

【0018】はんだ接続異常がはんだ接続部7a,7b
で発生すると、はんだ接続部7a,7bのインピダンス
が徐々に上昇するため、コンパレータ10の(+)側端
子の電位も徐々に上昇する。
The solder connection abnormality is caused by the solder connection portions 7a and 7b.
, The impedance of the solder connection portions 7a and 7b gradually increases, so that the potential of the (+) side terminal of the comparator 10 also gradually increases.

【0019】このコンパレータ10の(+)側端子の電
位がコンパレータ10の(−)端子のVref値を上回
った時、コンパレータ10の出力は反転し、出力レベル
は“H”になる。この信号レベル反転をはんだ接続部監
視部11が検出し、その検出結果を装置制御部12へ報
告する。
When the potential of the (+) terminal of the comparator 10 exceeds the Vref value of the (-) terminal of the comparator 10, the output of the comparator 10 is inverted and the output level becomes "H". This signal level inversion is detected by the solder connection monitoring section 11, and the detection result is reported to the apparatus control section 12.

【0020】装置制御部12は接続部監視部11にて検
出された接続異常情報から、接続確認用はんだボール
3,4と比較して接続寿命の長い信号用はんだボール
5,6の接続寿命を保持できる間に部品交換を要求す
る。
The device control unit 12 determines the connection life of the signal solder balls 5 and 6 having a longer connection life than the connection confirmation solder balls 3 and 4 based on the connection abnormality information detected by the connection monitoring unit 11. Request replacement of parts while they can be held.

【0021】このように、BGA1とPWB8との熱膨
張差によって機械的応力が一番大きく、そのため、理論
的にはんだ接続寿命の低いとされる最外周部の接続異常
を電気的にインピダンス変化としてとらえ、LSI動作
中の随時において、はんだ接続状態をモニタすることが
でき、接続異常を早期に発見することができる。
As described above, the mechanical stress is the largest due to the difference in thermal expansion between the BGA 1 and the PWB 8, and the connection abnormality at the outermost peripheral portion, which is theoretically considered to have a short solder connection life, is regarded as an electrical impedance change. At any time during the operation of the LSI, the state of the solder connection can be monitored, and a connection abnormality can be found at an early stage.

【0022】また、接続異常の検出ポイントを接続寿命
の短い最外周としているため、信号用はんだボール5,
6の部分が接続寿命の限界に到達する前に、はんだ付け
異常の発生を予測することができ、信号用接続断線によ
るシステム動作断の前に対策を実施することができる。
Further, since the connection abnormality detection point is located at the outermost periphery where the connection life is short, the signal solder balls 5 and 5 are used.
Before the part 6 reaches the limit of the connection life, occurrence of soldering abnormality can be predicted, and measures can be taken before disconnection of the system operation due to disconnection of the signal connection.

【0023】図3は本発明の他の実施例によるLSIは
んだ付け部接続異常検出方法を示す概念図である。図3
において、接続確認用ピン15,16はPGA(Pin
Grid Array)13とPWB8との熱膨張差
によって機械的応力が一番大きく、そのため、理論的に
はんだ接続寿命の低いとされるPGA13の最外周部の
任意の場所に配置され、PWB8にはんだを用いて電気
的に接続されている(はんだ接続部7a,7b)。
FIG. 3 is a conceptual diagram showing a method for detecting an abnormal connection of an LSI soldering portion according to another embodiment of the present invention. FIG.
, The connection confirmation pins 15 and 16 are connected to PGA (Pin
The mechanical stress is the largest due to the difference in thermal expansion between the grid array (Grid Array) 13 and the PWB 8. Therefore, the PGA 8 is disposed at an arbitrary position on the outermost periphery of the PGA 13, which is theoretically considered to have a short solder connection life. And are electrically connected to each other (solder connection portions 7a and 7b).

【0024】接続確認用ピン15は電気的にGND(グ
ランド)に接続され、LSI内配線14を通して接続確
認用ピン16に接続されている。接続確認用ピン16は
抵抗9によってプルアップされ、コンパレータ10の一
端(+)に接続されている。コンパレータ10の他端
(−)には基準電源(Vref)が接続されている。
The connection confirming pin 15 is electrically connected to GND (ground), and is connected to the connection confirming pin 16 through the LSI internal wiring 14. The connection check pin 16 is pulled up by the resistor 9 and is connected to one end (+) of the comparator 10. The other end (−) of the comparator 10 is connected to a reference power supply (Vref).

【0025】コンパレータ10の出力にはその出力をモ
ニタし、はんだ接続部7a,7bの接続異常(高インピ
ダンス、開放)を検出するはんだ接続部監視部11が接
続され、接続部監視部11の出力はその検出した接続異
常情報から、接続確認用ピン15,16と比較して接続
寿命の長い信号用ピン17,18の接続寿命を保持でき
る間に、部品交換依頼を要求する装置制御部12へ接続
されている。
The output of the comparator 10 is connected to a solder connection monitor 11 for monitoring the output and detecting a connection abnormality (high impedance, open) of the solder connection 7a, 7b. From the detected connection abnormality information to the device control unit 12 that requests a component replacement while the connection life of the signal pins 17 and 18 having a longer connection life than the connection confirmation pins 15 and 16 can be maintained. It is connected.

【0026】図1に示す本発明の一実施例によるはんだ
付け構造ではBGA1の接続確認用はんだボール3,4
をBGA1の最外周部の任意の場所に配置しているが、
図3に示すように、BGA1でなくPGA13でも、本
発明の一実施例と同様なモニタ方式が可能である。
In the soldering structure according to the embodiment of the present invention shown in FIG. 1, the solder balls 3 and 4 for confirming the connection of the BGA 1 are formed.
Is arranged at an arbitrary position on the outermost periphery of the BGA 1,
As shown in FIG. 3, a monitoring method similar to that of the embodiment of the present invention can be applied to the PGA 13 instead of the BGA 1.

【0027】図4は本発明の別の実施例によるLSIは
んだ付け部接続異常検出方法を示す概念図である。図4
において、接続確認用はんだボール3,4はBGA1と
PWB8との熱膨張差によって機械的応力が一番大き
く、そのため、理論的にはんだ接続寿命の低いとされる
BGA1の最外周部の任意の場所に配置され、PWB8
にはんだを用いて電気的に接続されている(はんだ接続
部7a,7b)。
FIG. 4 is a conceptual diagram showing a method for detecting an abnormal connection of an LSI soldering portion according to another embodiment of the present invention. FIG.
In the above, the solder balls 3 and 4 for connection confirmation have the largest mechanical stress due to the difference in thermal expansion between the BGA1 and the PWB8, and therefore, the solder balls 3 and 4 have an arbitrary location on the outermost periphery of the BGA1 which is theoretically considered to have a short solder connection life PWB8
Are electrically connected using solder (solder connection portions 7a and 7b).

【0028】接続確認用はんだボール3は電気的にGN
D(グランド)に接続され、LSI内配線2を通して接
続確認用はんだボール4に接続されている。接続確認用
はんだボール4は抵抗21によってプルアップされ、コ
ンパレータ22の一端(−)に接続されている。コンパ
レータ22の他端(+)には基準電源(Vref)が接
続されている。
The connection confirmation solder balls 3 are electrically GN
D (ground), and connected to the connection confirming solder ball 4 through the wiring 2 in the LSI. The connection confirmation solder ball 4 is pulled up by the resistor 21 and is connected to one end (−) of the comparator 22. The other end (+) of the comparator 22 is connected to a reference power supply (Vref).

【0029】コンパレータ22の出力にはその出力をモ
ニタし、はんだ接続部7a,7bの接続異常を検出する
はんだ接続部監視部23が接続され、接続部監視部23
の出力はその検出した接続異常情報から、接続確認用は
んだボール3,4と比較して接続寿命の長い信号用はん
だボール5,6の接続寿命を保持できる間に、部品交換
依頼を要求する装置制御部24へ接続されている。
The output of the comparator 22 is connected to a solder connection monitor 23 for monitoring the output and detecting an abnormal connection between the solder connections 7a and 7b.
Is an apparatus for requesting a component replacement request while maintaining the connection life of the signal solder balls 5 and 6 having a longer connection life than the connection confirmation solder balls 3 and 4 based on the detected connection abnormality information. It is connected to the control unit 24.

【0030】図5は図4のコンパレータ22の異常発生
時における信号波形を示す信号波形図である。これら図
4及び図5を参照して本発明の別の実施例によるLSI
はんだ付け部接続異常検出方法の動作について説明す
る。
FIG. 5 is a signal waveform diagram showing a signal waveform when an abnormality occurs in the comparator 22 of FIG. Referring to FIGS. 4 and 5, an LSI according to another embodiment of the present invention will be described.
The operation of the soldering part connection abnormality detection method will be described.

【0031】はんだ付け不良が未発生の場合、コンパレ
ータ22の(−)側入力端子は接続確認用はんだボール
4、はんだ接続部7b、LSI内配線2、接続確認用は
んだボール3、はんだ接続部7aを介してGNDに接続
されており、電位は0Vである。
If no soldering failure has occurred, the (-) side input terminal of the comparator 22 is a connection confirmation solder ball 4, a solder connection portion 7b, an LSI wiring 2, a connection confirmation solder ball 3, and a solder connection portion 7a. , And the potential is 0V.

【0032】また、コンパレータ22の(+)端子側
は、Vref電圧(Vcc>Vref)に設定されてい
る。これによって、コンパレータ22の出力は“H”レ
ベルになっている。
The (+) terminal side of the comparator 22 is set to a Vref voltage (Vcc> Vref). As a result, the output of the comparator 22 is at the “H” level.

【0033】はんだ接続異常がはんだ接続部7a,7b
で発生すると、はんだ接続部7a,7bのインピダンス
が徐々に上昇するため、コンパレータ22の(−)側端
子の電位も徐々に上昇する。
The solder connection abnormality is caused by the solder connection portions 7a and 7b.
Occurs, the impedance of the solder connection portions 7a and 7b gradually increases, so that the potential of the (-) side terminal of the comparator 22 also gradually increases.

【0034】コンパレータ22の(−)側端子の電位が
コンパレータ22の(+)端子のVref値を上回った
時、コンパレータ22の出力は反転し、出力レベルは
“L”になる。この信号レベル反転をはんだ接続部監視
部23が検出し、その検出結果を部品交換依頼を要求す
る装置制御部24へ報告する。
When the potential of the (-) terminal of the comparator 22 exceeds the Vref value of the (+) terminal of the comparator 22, the output of the comparator 22 is inverted and the output level becomes "L". This signal level inversion is detected by the solder connection monitoring unit 23, and the detection result is reported to the device control unit 24 requesting a component replacement request.

【0035】装置制御部24は接続部監視部23にて検
出された接続異常情報によって、接続確認用はんだボー
ル3,4と比較して接続寿命の長い信号用はんだボール
5,6の接続寿命を保持できる間に、部品交換を要求す
る。
Based on the connection abnormality information detected by the connection monitoring section 23, the device control section 24 determines the connection life of the signal solder balls 5, 6 having a longer connection life than the connection confirmation solder balls 3, 4. Request replacement of parts while they can be held.

【0036】このように、本発明の別の実施例によるL
SIはんだ付け部接続異常検出方法の如く、コンパレー
タ22の入力端子の(+)と(−)とを交換しても、本
発明の一実施例によるLSIはんだ付け部接続異常検出
方法と同様な効果を得ることができる。
Thus, L according to another embodiment of the present invention
Even when the (+) and (-) input terminals of the comparator 22 are exchanged as in the SI soldering part connection abnormality detecting method, the same effect as the LSI soldering part connection abnormality detecting method according to the embodiment of the present invention is obtained. Can be obtained.

【0037】[0037]

【発明の効果】以上説明したように本発明によれば、大
規模集積回路の基板への電気的接続を行うためのLSI
はんだ接続構造において、大規模集積回路と基板との熱
膨張差によって機械的応力が一番大きい大規模集積回路
の最外周部における接続異常を検出するためのはんだ接
続部材を当該最外周部に配置し、はんだ接続部材の接続
異常を検出することによって、大規模集積回路動作中の
随時においてはんだ接続状態をモニタすることができ、
接続異常を早期に発見することができるという効果があ
る。
As described above, according to the present invention, an LSI for electrically connecting a large-scale integrated circuit to a substrate is provided.
In the solder connection structure, a solder connection member for detecting a connection abnormality at the outermost periphery of the large-scale integrated circuit having the largest mechanical stress due to a difference in thermal expansion between the large-scale integrated circuit and the substrate is arranged at the outermost periphery. Then, by detecting the connection abnormality of the solder connection member, it is possible to monitor the solder connection state at any time during the operation of the large-scale integrated circuit,
There is an effect that a connection abnormality can be detected at an early stage.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例によるLSIはんだ付け部接
続異常検出方法を示す概念図である。
FIG. 1 is a conceptual diagram showing an LSI soldering portion connection abnormality detection method according to one embodiment of the present invention.

【図2】図1のコンパレータの異常発生時における信号
波形を示す信号波形図である。
FIG. 2 is a signal waveform diagram showing a signal waveform when an abnormality occurs in the comparator of FIG. 1;

【図3】本発明の他の実施例によるLSIはんだ付け部
接続異常検出方法を示す概念図である。
FIG. 3 is a conceptual diagram showing an LSI soldering portion connection abnormality detecting method according to another embodiment of the present invention.

【図4】本発明の別の実施例によるLSIはんだ付け部
接続異常検出方法を示す概念図である。
FIG. 4 is a conceptual diagram showing an LSI soldering portion connection abnormality detecting method according to another embodiment of the present invention.

【図5】図4のコンパレータの異常発生時における信号
波形を示す信号波形図である。
FIG. 5 is a signal waveform diagram showing a signal waveform when an abnormality occurs in the comparator of FIG. 4;

【符号の説明】[Explanation of symbols]

1 BGA 2,14 LSI内配線 3,4 接続確認用はんだボール 5,6 信号用はんだボール 7a,7b はんだ接続部 8 PWB 9,21 抵抗 10,22 コンパレータ 11,23 接続部監視部 12,24 装置制御部 13 PGA 15,16 接続確認用ピン 17,18 信号用ピン DESCRIPTION OF SYMBOLS 1 BGA 2,14 Wiring in LSI 3,4 Solder ball for connection check 5,6 Solder ball for signal 7a, 7b Solder connection part 8 PWB 9,21 Resistance 10,22 Comparator 11,23 Connection part monitoring part 12,24 Device Control unit 13 PGA 15, 16 Connection confirmation pin 17, 18 Signal pin

Claims (12)

【特許請求の範囲】[Claims] 【請求項1】 大規模集積回路の基板への電気的接続を
行うためのLSIはんだ接続構造であって、前記大規模
集積回路と前記基板との熱膨張差によって機械的応力が
一番大きい前記大規模集積回路の最外周部に配置されか
つその最外周部における接続異常を検出するためのはん
だ接続部材を有し、前記はんだ接続部材の接続異常を検
出するようにしたことを特徴とするLSIはんだ接続構
造。
1. An LSI solder connection structure for electrically connecting a large-scale integrated circuit to a substrate, wherein the mechanical stress is largest due to a difference in thermal expansion between the large-scale integrated circuit and the substrate. An LSI arranged at the outermost periphery of a large-scale integrated circuit and having a solder connection member for detecting a connection abnormality at the outermost periphery thereof, wherein the connection abnormality of the solder connection member is detected. Solder connection structure.
【請求項2】 前記はんだ接続部材は、接続確認用のは
んだボールからなることを特徴とする請求項1記載のL
SIはんだ接続構造。
2. The L according to claim 1, wherein the solder connection member is formed of a solder ball for confirming connection.
SI solder connection structure.
【請求項3】 前記大規模集積回路は、BGA(Bal
l Grid Array)からなることを特徴とする
請求項2記載のLSIはんだ接続構造。
3. The large-scale integrated circuit includes a BGA (Bal
3. The LSI solder connection structure according to claim 2, wherein the connection structure is formed of (1 Grid Array).
【請求項4】 前記はんだ接続部材は、接続確認用のピ
ン部材からなることを特徴とする請求項1記載のLSI
はんだ接続構造。
4. The LSI according to claim 1, wherein said solder connection member comprises a pin member for confirming connection.
Solder connection structure.
【請求項5】 前記大規模集積回路は、PGA(Pin
Grid Array)からなることを特徴とする請
求項4記載のLSIはんだ接続構造。
5. The large-scale integrated circuit includes a PGA (Pin)
5. The LSI solder connection structure according to claim 4, wherein the connection structure is formed of a grid array.
【請求項6】 前記はんだ接続部材の接続異常を電気的
にインピダンス変化としてとらえるようにしたことを特
徴とする請求項1から請求項5のいずれか記載のLSI
はんだ接続構造。
6. The LSI according to claim 1, wherein the connection abnormality of the solder connection member is electrically regarded as an impedance change.
Solder connection structure.
【請求項7】 大規模集積回路の基板への電気的接続を
行うためのLSIはんだ接続構造におけるLSIはんだ
付け部接続異常検出方法であって、前記大規模集積回路
と前記基板との熱膨張差によって機械的応力が一番大き
い前記大規模集積回路の最外周部における接続異常を検
出するためのはんだ接続部材を当該最外周部に配置し、
前記はんだ接続部材の接続異常を検出するようにしたこ
とを特徴とするLSIはんだ付け部接続異常検出方法。
7. A method for detecting an abnormal connection of an LSI soldering portion in an LSI solder connection structure for electrically connecting a large-scale integrated circuit to a substrate, the method comprising detecting a thermal expansion difference between the large-scale integrated circuit and the substrate. The mechanical stress is the largest, the solder connection member for detecting a connection abnormality in the outermost peripheral portion of the large-scale integrated circuit is arranged in the outermost peripheral portion,
An abnormal connection detection method for an LSI soldering portion, wherein an abnormal connection of the solder connection member is detected.
【請求項8】 前記はんだ接続部材は、接続確認用のは
んだボールからなることを特徴とする請求項7記載のL
SIはんだ付け部接続異常検出方法。
8. The light emitting diode according to claim 7, wherein the solder connection member is formed of a solder ball for confirming connection.
SI soldering part connection abnormality detection method.
【請求項9】 前記大規模集積回路は、BGA(Bal
l Grid Array)からなることを特徴とする
請求項8記載のLSIはんだ付け部接続異常検出方法。
9. The large-scale integrated circuit includes a BGA (Bal
9. The method for detecting an abnormality in connection of an LSI soldering part according to claim 8, wherein the method comprises: (1 Grid Array).
【請求項10】 前記はんだ接続部材は、接続確認用の
ピン部材からなることを特徴とする請求項7記載のLS
Iはんだ付け部接続異常検出方法。
10. The LS according to claim 7, wherein the solder connection member is formed of a pin member for confirming connection.
I Solder connection error detection method.
【請求項11】 前記大規模集積回路は、PGA(Pi
n Grid Array)からなることを特徴とする
請求項10記載のLSIはんだ付け部接続異常検出方
法。
11. The large-scale integrated circuit includes a PGA (Pi
11. The method for detecting an abnormality in connection of an LSI soldering part according to claim 10, wherein the method comprises: n grid array).
【請求項12】 前記はんだ接続部材の接続異常を電気
的にインピダンス変化としてとらえるようにしたことを
特徴とする請求項7から請求項11のいずれか記載のL
SIはんだ付け部接続異常検出方法。
12. The L according to claim 7, wherein the connection abnormality of the solder connection member is electrically regarded as a change in impedance.
SI soldering part connection abnormality detection method.
JP2000037338A 2000-02-16 2000-02-16 Lsi soldered joint structure, and lsi soldered part abnormal joint detecting method used for it Pending JP2001228191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000037338A JP2001228191A (en) 2000-02-16 2000-02-16 Lsi soldered joint structure, and lsi soldered part abnormal joint detecting method used for it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000037338A JP2001228191A (en) 2000-02-16 2000-02-16 Lsi soldered joint structure, and lsi soldered part abnormal joint detecting method used for it

Publications (1)

Publication Number Publication Date
JP2001228191A true JP2001228191A (en) 2001-08-24

Family

ID=18561237

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100652416B1 (en) 2005-07-07 2006-12-01 삼성전자주식회사 Apparatus and method for testing multi-stack integrated circuit package
JP2007113983A (en) * 2005-10-19 2007-05-10 Fuji Electric Device Technology Co Ltd Abnormality detecting apparatus for power semiconductor device
JP2008309528A (en) * 2007-06-12 2008-12-25 Toshiba Corp Electronic device
JP2010251519A (en) * 2009-04-15 2010-11-04 Denso Corp Electronic device
JP2010271182A (en) * 2009-05-21 2010-12-02 Mitsubishi Electric Corp Connection abnormality detecting device, and on-vehicle electronic apparatus using the same
WO2023209856A1 (en) * 2022-04-27 2023-11-02 日立Astemo株式会社 Onboard control device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100652416B1 (en) 2005-07-07 2006-12-01 삼성전자주식회사 Apparatus and method for testing multi-stack integrated circuit package
JP2007113983A (en) * 2005-10-19 2007-05-10 Fuji Electric Device Technology Co Ltd Abnormality detecting apparatus for power semiconductor device
JP2008309528A (en) * 2007-06-12 2008-12-25 Toshiba Corp Electronic device
JP2010251519A (en) * 2009-04-15 2010-11-04 Denso Corp Electronic device
US8395404B2 (en) 2009-04-15 2013-03-12 Denso Corporation Electronic device including electronic part and wiring substrate
JP2010271182A (en) * 2009-05-21 2010-12-02 Mitsubishi Electric Corp Connection abnormality detecting device, and on-vehicle electronic apparatus using the same
WO2023209856A1 (en) * 2022-04-27 2023-11-02 日立Astemo株式会社 Onboard control device

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