JP2001210671A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2001210671A
JP2001210671A JP2000024677A JP2000024677A JP2001210671A JP 2001210671 A JP2001210671 A JP 2001210671A JP 2000024677 A JP2000024677 A JP 2000024677A JP 2000024677 A JP2000024677 A JP 2000024677A JP 2001210671 A JP2001210671 A JP 2001210671A
Authority
JP
Japan
Prior art keywords
electrode
conductive foil
semiconductor device
conductive
protrusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000024677A
Other languages
English (en)
Other versions
JP4222703B2 (ja
Inventor
Norihiro Uchiyama
徳弘 内山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP2000024677A priority Critical patent/JP4222703B2/ja
Publication of JP2001210671A publication Critical patent/JP2001210671A/ja
Application granted granted Critical
Publication of JP4222703B2 publication Critical patent/JP4222703B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

(57)【要約】 【課題】 電極表面が酸化しているとリードや導電箔と
の接続面積を拡大してもオン抵抗を下げることができな
かった。 【解決手段】両面に主電流が流入または流出する第１、
第２の電極を形成した半導体ペレットの第１の電極をア
イランドに電気的に接続してマウントし、第２の電極と
リードとを導電箔を介して電気的に接続した半導体装置
において、上記導電箔の第２の電極と対向する面に、加
圧により塑性変形可能な導電部材よりなる突起を形成
し、この突起の周面を膨出させて第２の電極と導電箔と
を電気的に接続したことを特徴とする半導体装置。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明はパワーＭＯＳＦＥＴ
やパワートランジスタなどの大電流を取り扱う半導体装
置に関し、特に導通時の電気抵抗（オン抵抗）が小さい
半導体ペレットを備えた半導体装置に関する。
【０００２】
【従来の技術】電力制御装置など大きな電力を取り扱う
電子回路装置では電力効率差がわずかでも消費電力が大
きく異なるため、これに用いられる電力制御素子はオン
抵抗の小さいものが必要とされている。そのため一般的
に電力制御素子として用いられる半導体装置は半導体装
置本体である半導体ペレットの耐電圧を高めると同時に
オン抵抗を低減しさらには電極間容量を低減するなど多
くの提案がなされ、電力用ＭＯＳＦＥＴでは、１０ｍΩ
以下の低オン抵抗を実現している。一方、オン抵抗が小
さな半導体装置は電力用だけでなくスイッチング素子一
般に用いられ、小電力分野では小型化も要求されてい
る。図８及び図９は低オン抵抗の半導体装置の一例を示
す。図において、１は半導体ペレットで、内部に半導体
素子（図示せず）が形成されている。半導体素子が主電
流を制御する電極を有するサイリスタやトランジスタ、
ＭＯＳＦＥＴの場合、両面のほぼ全面に主電流が流入ま
たは流出するアノードまたはドレインなどの第１、第２
の電極２、３が形成され、一方の主面の微小面積領域に
制御用のゲート電極（第３の電極）４が形成されてい
る。５は半導体ペレット１をマウントしたアイランド
で、半導体ペレット１とアイランド５の接続には電気抵
抗が小さい半田６が一般的に用いられる。７は図示例で
は３本一組のリードで、中間部乃至外端部が平行配置さ
れ、中央のリード７ａがアイランド５に電気的、機械的
に接続され、他のリード７ｂ、７ｃはリード７ａの両側
に配置され、それぞれの内端部がアイランド５の近傍に
配置されている。８は第２の電極３とリード７ｂを電気
的に接続する第１のワイヤ、９は第３の電極４とリード
７ｃを電気的に接続する第２のワイヤを示す。１０はア
イランドの全面と半導体ペレット１を含む主要部分を被
覆した樹脂で、リード７はこの樹脂１０の側壁から導出
され、必要に応じて折り曲げ成形される。この半導体装
置の第１電極２は半導体ペレット１内部のオン抵抗より
格段に小さい電気抵抗値の半田６、アイランド５を経由
してリード７ａに直列接続されている。また、第３電極
４に接続された第２のワイヤ９を通過する電流は主電流
に比較して格段に小さく電圧降下を無視できるため細い
ものを用いることができる。一方、第２の電極３からリ
ード７ｂへは、第１の電極２に流入した電流とほぼ等し
い電流が流出するため、この電流値に応じてワイヤ８の
径が決定される。ワイヤ８、９は一般的に金、銅、アル
ミニウムの金属や合金が用いられる。金は導電性が良好
であるが、高価であるため太いものを用いることが困難
で径小のワイヤを図１０に示すように複数本、図示例で
は３本並列接続している。またアルミニウムは安価では
あるが導電性が金や銅に比して劣るため径大のワイヤを
複数本並列接続している。ところで、ワイヤ８とリード
７ｂとを比較すると、ワイヤ８の全断面積はリード７ｂ
の断面積に比して格段に小さいため、逆に電気抵抗は格
段に大きい。また第１の電極２から流入し半導体ペレッ
ト１内を移動した主電流は薄い第２の電極３に到達した
後、その表面を移動してワイヤ８に到達するため、第２
の電極３自体の抵抗値も無視できない。そのためリード
７ａ、７ｂ間の抵抗値はワイヤ８の径だけでなく、その
長さや第２の電極３との接続状態、接続位置によっても
影響を受けるため、低オン抵抗の半導体ペレット１の場
合、上記影響を無視することができず改善が望まれてい
た。また、ワイヤ８を多数本並列接続すれば抵抗値は低
減できるが、接続作業に時間を要し、製造コストが上昇
するという問題もあった。このような問題を解決する方
法として、図１１に示すようにワイヤ８の代わりに導電
箔１１を用いることが知られている。例えば直径４００
μｍのアルミニウムワイヤを３本並列接続するもので
は、厚さ２００μｍのアルミニウム箔では、巾６２８μ
ｍ以上のものに置き換えることができる。アルミニウム
箔の場合、熱圧着、超音波ボンディングにより電極３に
直接接続でき、金や銀の薄い膜を形成することにより半
田付け接続も可能である。またアルミニウムに比較して
やや高価であるが導電性が良好な銅を用いることもでき
る。
【０００３】
【発明が解決しようとする課題】ところで半導体ペレッ
ト１は半田６を用いてアイランド５にマウントする際に
半田溶融温度に曝されるため、第２、第３の電極３、４
の表面が酸化する。電極材料として一般的にアルミニウ
ムが用いられるが、この酸化物である酸化アルミニウム
は硬く、ワイヤ８や導電箔１１を超音波接続しても接続
部に酸化膜の微細片が残留し、完全に電気的接続される
面積が減少し、抵抗値を最小にすることができず、半導
体ペレット１としてオン抵抗が小さなものを用いても半
導体装置としてオン抵抗を最小にすることができなかっ
た。また、ワイヤ８に比して大面積の導電箔を第２の電
極３に接続するのに、大面積領域を均等に接続しようと
すると熱圧着では荷重が過大となり、半導体ペレット１
が傾斜していると荷重が一部に集中して損傷する虞があ
り、超音波ボンデイングでは導電箔上の複数個所を順次
ボンディングしなければならないため作業に時間を要す
るという問題があった。
【０００４】
【課題を解決するための手段】本発明は上記課題の解決
を目的として提案されたもので、両面に主電流が流入ま
たは流出する第１、第２の電極を形成した半導体ペレッ
トの第１の電極をアイランドに電気的に接続してマウン
トし、第２の電極とリードとを導電箔を介して電気的に
接続した半導体装置において、上記導電箔の第２の電極
と対向する面に、加圧により塑性変形可能な導電部材よ
りなる突起を形成し、この突起の周面を膨出させて第２
の電極と導電箔とを電気的に接続したことを特徴とする
半導体装置を提供する。
【０００５】
【発明の実施の形態】本発明による半導体装置は、主電
流が流れる第２の電極に接続される導電箔の第２の電極
と対向する面に、加圧により塑性変形可能な導電部材よ
りなる突起を形成し、この突起の周面を膨出させて第２
の電極と導電箔とを電気的に接続したことを特徴とする
が、突起は加圧により周面が膨出する形状であればどの
ような形状でも良いが、先端部の断面形状を半円形、楕
円形または放物形とすることにより、加圧による圧縮長
さに比して膨出量を大きくできる。また導電箔の第２の
電極と対向する面に、多数の突起を第２の電極領域内に
分散させて形成することにより、第２の電極から導電箔
へ電流を分散させて供給することができ、第２の電極内
での抵抗上昇を抑えることができる。この場合、突起を
島状に形成したり、連続した突起を多列形成することが
でき、突起を多列形成するものでは第２の電極と導電箔
とを、突起の配列方向と交差する方向の超音波振動を付
与して接続することができる。導電箔の突起は、導電箔
の表面をプレスして微小突起を形成しこの突起表面に、
加圧により塑性変形可能な導電部材をめっきすることに
より形成することができる。またこの突起は、導電箔に
塑性変形可能な導電部材の層を形成し、この層をプレス
して形成することができる。さらには突起表面を、加圧
に先立ってプラズマクリーニングなどの清浄化処理をす
ることにより、電気的接続を一層良好にできる。
【０００６】
【実施例】以下に本発明の実施例を図１および図２から
説明する。図において、図８および図９と同一物には同
一符号を付し重複する説明を省略する。本発明による半
導体装置は、両面のほぼ全面に主電流が流入または流出
する第１、第２の電極２、３が形成され一方の主面の微
小面積領域に制御用の第３の電極４を形成した半導体ペ
レット１を、アイランド５と図示例では３本一組のリー
ド７とを一体化したリードフレームのアイランド５に半
田６を介してマウントし、半導体ペレット１上の電極
３、４とリード７ｂ、７ｃの一端部とを電気的に接続
し、アイランドの全面と半導体ペレット１を含む主要部
分を樹脂１０にて被覆し、樹脂１０から露呈したリード
連結部などのリードフレームの不要部分を切断除去して
製造されたもので、半導体ペレット１上の第３の電極４
と第３リード７ｃとをワイヤ９で接続していることでは
図８装置と同じであるが、主電流が流れる第２の電極３
と第２リード７ｂとを導電箔１２で接続した点で、図８
装置とは異なる。また本発明装置に用いられる導電箔１
２は、第２の電極３と対向する面に、加圧により塑性変
形可能な導電部材よりなる突起１３を形成し、この突起
１３の周面を膨出させて第２の電極３と導電箔１２とを
電気的に接続した点で図１１装置とも異なる。上記第２
の電極３と導電箔１２の接続作業を図３〜図７から説明
する。先ず図３に示すように導電箔１２の第２の電極３
と対向する面をプレスして平坦な面に多数の微小突起１
２ａを形成する。導電箔１２は安価なアルミニウムや電
気的導電性が良好な銅などの金属やこれらの金属を主成
分とする合金を用いることができ、微小突起１２ａは高
さ１０μｍ〜１００μｍ、配列ピッチ２０μｍ〜２００
μで、多数整列して形成する。そしてこの微小突起１２
ａの表面に図４に示すように加圧により塑性変形可能な
導電部材、例えば金のめっき層１４を形成する。このめ
っき層１４の厚みは０．５μｍ以上で微小突起１２ａが
埋没しない程度の厚さに設定される。この導電箔１２
は、図５に示すように微小突起１２ａ部分を電極３と対
向させ、めっき層１４を電極３に当接させる。この状態
から導電箔１２に超音波振動を付与したり加熱した状態
で加圧すると、図６に示すように電極３に点接触または
線接触しためっき層１４が微小突起１２ａにより押し広
げられ、図７に示すように電極３とめっき層１４即ち導
電箔１２の接触面積が増大する。導電箔１２にめっき層
がない場合、微小突起１２ａが電極３に強固に押し付け
られて接触部が超音波接続または熱圧着されるが、その
面積は図７における符号ａを付した領域に限られる。こ
れに対して本発明によれば、めっき層１４が膨出するた
め電気的接続部は図示符号ｂを付した領域に拡大し、領
域ａに対して面積比は（ｂ／ａ）の自乗倍に拡大する。
この微小突起１２ａにめっき層１４を形成した突起１３
は、導電箔１２に多数形成され、導電箔１２と電極３と
は微小突起１２ａによって分散して接続されるため、第
１の電極２から半導体ペレット１内に流入した電流は半
導体ペレット１内の局部に集中することはない。また半
導体ペレット１を加熱した状態で導電箔１２を接続する
場合でも、微小突起１２ａの頂部にあるめっき層１４は
加圧されて膨出する際に第２の電極３の表面を摺動して
酸化膜を除去し、めっき層１４と電極３の素地同士が互
いに接触し、接続抵抗を最小にでき、オン抵抗が小さな
半導体ペレット１を用いることによってオン抵抗が最小
の半導体装置を実現できる。また、導電箔１２の微小突
起１２ａが第２の電極３をカバーできるように大面積に
分散形成されていても微小突起１２ａの電極３に対する
当接面積は小さいため、小さな荷重で熱圧着でき、この
とき半導体ペレット１が傾斜していても荷重の局部集中
が防止でき、超音波ボンデイングでは複数の微小突起１
２ａを一括ボンディングできるため作業時間を大幅に短
縮することができる。微小突起１２ａの先端部の側断面
形状は図示例のように半円形とするだけでなく、楕円形
または放物形とすることができる。これにより、微小突
起１２ａを被覆しためっき層１４の膨出量を十分大きく
でき、膨出による接続面積を拡大できる。また微小突起
１２ａは導電箔１２の第２の電極３と対向する面に、少
なくとも一つ形成すれば良いが、図示例のように多数の
突起１２ａを第２の電極３と対向する領域内に分散させ
て形成することが好ましい。この場合、微小突起１２ａ
を図示例のように島状に形成するだけでなく、微小突起
１２ａを連続させ多列形成することもできる。そして導
電箔１２と第２の電極３とを超音波振動により接続する
場合には、第２の電極３と導電箔１２とを、突起１２ａ
の配列方向と交差する方向に超音波振動を付与すると、
加圧により膨出しためっき層１４と電極３の接続を良好
にできる。また本発明による半導体装置は、上記実施例
のように導電箔１２の第２の電極３と対向する面に形成
された突起１３が、導電箔１２をプレスして形成した微
小突起１２ａの表面に加圧により塑性変形可能な導電部
材でめっきしたものだけでなく、導電箔１２を塑性変形
可能な導電部材で被覆し、この被覆層をプレスして微小
突起を形成したものでもよく、さらには個別の金属ボー
ルあるいはワイヤの先端を溶融させて形成した金属ボー
ルを圧着して微小突起をけいせいすることもできる。ま
た本発明による半導体装置は、導電箔１２の第２の電極
３と対向する面に形成された突起１３の表面を加圧に先
立って清浄化処理することにより、電極３と導電箔１２
の電気的接続を一層良好にできる。
【０００７】
【発明の効果】以上のように本発明によれば、製造過程
で高温にさらされ酸化し易い半導体ペレットの主電流が
流れる電極上の広い領域に導電箔を低抵抗で接続するこ
とができ、オン抵抗を低減することのできる半導体装置
を実現できる。
【図面の簡単な説明】
【図１】 本発明の実施例を示す半導体装置の側断面図
【図２】 図１半導体装置の要部拡大側断面図
【図３】 図１半導体装置に用いられる導電箔の製造方
法を示す側断面図
【図４】 図１半導体装置に用いられる導電箔の製造方
法を示す側断面図
【図５】 図１半導体装置の第２の電極と導電箔の接続
作業を示す側断面図
【図６】 図５の要部拡大側断面図
【図７】 第２の電極に導電箔が加圧接続された状態を
示す側断面図
【図８】 電力用半導体装置の一例を示す要部断面平面
図
【図９】 図９半導体装置の側断面図
【図１０】 改良された電力用半導体装置の一例を示す
要部断面平面図
【図１１】 改良された電力用半導体装置の一例を示す
要部断面平面図
【符号の説明】
１ 半導体ペレット ２ 第１の電極 ３ 第２の電極 ５ アイランド ７ リード １２ 導電箔 １４ 塑性変形可能な導電部材 １３ 突起

Claims (9)

    【特許請求の範囲】
  1. 【請求項１】両面に主電流が流入または流出する第１、
    第２の電極を形成した半導体ペレットの第１の電極をア
    イランドに電気的に接続してマウントし、第２の電極と
    リードとを導電箔を介して電気的に接続した半導体装置
    において、 上記導電箔の第２の電極と対向する面に、加圧により塑
    性変形可能な導電部材よりなる突起を形成し、この突起
    の周面を膨出させて第２の電極と導電箔とを電気的に接
    続したことを特徴とする半導体装置。
  2. 【請求項２】突起先端部の断面形状が半円形、楕円形ま
    たは放物形であることを特徴とする請求項１に記載の半
    導体装置。
  3. 【請求項３】導電箔の第２の電極と対向する面に、多数
    の突起を第２の電極領域内に分散させて形成したことを
    特徴とする請求項１に記載の半導体装置。
  4. 【請求項４】突起が島状に形成されたことを特徴とする
    請求項３に記載の半導体装置。
  5. 【請求項５】連続する突起が多列形成されたことを特徴
    とする請求項３に記載の半導体装置。
  6. 【請求項６】第２の電極と導電箔とを、突起の配列方向
    と交差する方向の超音波振動を付与して接続したことを
    特徴とする請求項５に記載の半導体装置。
  7. 【請求項７】導電箔の第２の電極と対向する面に形成さ
    れた突起が、導電箔をプレスして形成した微小突起表面
    を加圧により塑性変形可能な導電部材でめっきしたもの
    であることを特徴とする請求項１に記載の半導体装置。
  8. 【請求項８】導電箔の第２の電極と対向する面に形成さ
    れた突起が、導電箔を被覆した塑性変形可能な導電部材
    層をプレスして形成したものであることを特徴とする請
    求項１に記載の半導体装置。
  9. 【請求項９】上記導電箔の第２の電極と対向する面に形
    成された突起表面が、加圧に先立って清浄化処理された
    ことを特徴とする請求項１に記載の半導体装置。
JP2000024677A 2000-01-28 2000-01-28 半導体装置 Expired - Fee Related JP4222703B2 (ja)

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JP4222703B2 JP4222703B2 (ja) 2009-02-12

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018237199A1 (en) * 2017-06-22 2018-12-27 Renesas Electronics America Inc. SOLID TOP TERMINAL FOR DISCRETE FEED DEVICES

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS447543Y1 (ja) * 1966-04-04 1969-03-22
JPS62200738A (ja) * 1986-02-28 1987-09-04 Seiko Epson Corp 回路基板構造
JPH11121684A (ja) * 1997-10-16 1999-04-30 Nissan Motor Co Ltd 電力用トランジスタの実装構造
JP2000277557A (ja) * 1999-03-26 2000-10-06 Fujitsu Ten Ltd 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS447543Y1 (ja) * 1966-04-04 1969-03-22
JPS62200738A (ja) * 1986-02-28 1987-09-04 Seiko Epson Corp 回路基板構造
JPH11121684A (ja) * 1997-10-16 1999-04-30 Nissan Motor Co Ltd 電力用トランジスタの実装構造
JP2000277557A (ja) * 1999-03-26 2000-10-06 Fujitsu Ten Ltd 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018237199A1 (en) * 2017-06-22 2018-12-27 Renesas Electronics America Inc. SOLID TOP TERMINAL FOR DISCRETE FEED DEVICES

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