JP2001156218A - Producing method for electronic device - Google Patents

Producing method for electronic device

Info

Publication number
JP2001156218A
JP2001156218A JP33874599A JP33874599A JP2001156218A JP 2001156218 A JP2001156218 A JP 2001156218A JP 33874599 A JP33874599 A JP 33874599A JP 33874599 A JP33874599 A JP 33874599A JP 2001156218 A JP2001156218 A JP 2001156218A
Authority
JP
Japan
Prior art keywords
wiring board
wiring
electronic device
resin sealing
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33874599A
Other languages
Japanese (ja)
Inventor
Kazuhito Kanezashi
一仁 金指
Yuichi Furumoto
雄一 古本
Shuichi Fukutome
修一 福留
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP33874599A priority Critical patent/JP2001156218A/en
Publication of JP2001156218A publication Critical patent/JP2001156218A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve a problem that an obtained electronic device can not be securely mounted on an external electric circuit board and that sealing of electronic components is complicated. SOLUTION: A mother board 10, which is constituted by laminating upper and lower insulating layers 10a and 10b, has a plurality of wiring board areas 11 located and formed at a central part being partitioned by dividing lines 12, is provided with a hole 13 for notch on each of dividing lines 12 and is provided with a wiring conductor 5 derived from the upper surface of each wiring board area 11 through the inside and the inner wall of the hole 13 for notch to the lower surface, is prepared. Next, electronic components 2 are mounted on the upper surfaces of the respective wiring board areas 11 and respective electrodes thereof are connected to the wiring conductor 5. Next, a resin sealing member 3 is applied in the state of liquid and hardened so as to cover the respective wiring board areas 11 and the respective electronic components 2 and finally, the mother board 10 and the resin sealing member 3 are divided along the dividing line 12. Concerning such a producing method for electronic device, when applying the resin sealing member 3 in the state of liquid, that member does not flow into the hole 13 for notch, where the wiring conductor 5 is attached.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、小型の配線基板上
に半導体素子や圧電振動子等の電子部品を搭載するとと
もに、この電子部品を樹脂製封止材で被覆することによ
り気密に封止してなる樹脂封止型の電子装置の製造方法
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting an electronic component such as a semiconductor element and a piezoelectric vibrator on a small-sized wiring board, and sealing the electronic component with a resin sealing material. And a method for manufacturing a resin-sealed electronic device.

【0002】[0002]

【従来の技術】従来、コンピュータ等の情報処理装置や
携帯電話機等の通信端末装置等に実装される樹脂封止型
の小型電子装置として、例えば図5に断面図で図6に斜
視図で示すように、酸化アルミニウム質焼結体等の電気
絶縁材料から成り、その側面に上下に貫通する複数の切
り欠き部22を有するとともにその上面から切り欠き部22
を介して下面にかけて導出する複数の配線導体23を被着
させて成る大きさが数mm角程度の略四角平板状の小型
の配線基板21上に、半導体素子等の電子部品24をその各
電極が配線導体23に電気的に接続されるようにして搭載
するとともに、この配線基板21の上面中央部に電子部品
24を覆うようにして例えばエポキシ樹脂等の樹脂から成
る樹脂製封止材25を固着させることにより電子部品24を
気密に封止して成る電子装置が知られている。
2. Description of the Related Art Conventionally, as a resin-sealed small electronic device mounted on an information processing device such as a computer or a communication terminal device such as a portable telephone, for example, a sectional view in FIG. 5 and a perspective view in FIG. As described above, it is made of an electrically insulating material such as an aluminum oxide sintered body, and has a plurality of cutouts 22 penetrating vertically on the side surface thereof, and a cutout 22
An electronic component 24 such as a semiconductor element is mounted on a small wiring board 21 having a size of about several mm square, which is formed by attaching a plurality of wiring conductors 23 led out to the lower surface through Is mounted so as to be electrically connected to the wiring conductor 23, and the electronic component is mounted on the center of the upper surface of the wiring board 21.
There is known an electronic device in which an electronic component 24 is hermetically sealed by fixing a resin sealing material 25 made of a resin such as an epoxy resin so as to cover the electronic component 24.

【0003】この従来の電子装置は、配線導体23で配線
基板21の下面に導出した部位を外部電気回路基板の接続
用導体に当接させ、配線導体23と外部電気回路基板の接
続用導体とを半田を介して接合させることにより外部電
気回路基板上に実装され、同時に搭載する電子部品24の
各電極が配線導体23を介して外部電気回路に電気的に接
続されるようになっている。この電子装置は半田を介し
て外部電気回路基板に実装すると、配線基板21の側面に
形成された切り欠き部22内に被着された配線導体23と外
部電気回路基板の接続用導体との間に半田の溜まりが立
体的に良好に形成されて外部電気回路基板に極めて強固
に実装されるようになっている。
In this conventional electronic device, a portion of the wiring conductor 23 led out to the lower surface of the wiring board 21 is brought into contact with a connection conductor of an external electric circuit board, and the wiring conductor 23 is connected to the connection conductor of the external electric circuit board. Are mounted on an external electric circuit board by soldering, and each electrode of the electronic component 24 to be mounted at the same time is electrically connected to the external electric circuit via the wiring conductor 23. When this electronic device is mounted on an external electric circuit board via solder, a gap between a wiring conductor 23 attached in a notch 22 formed on a side surface of the wiring board 21 and a connection conductor of the external electric circuit board is obtained. The solder pool is formed three-dimensionally and well, and is extremely firmly mounted on the external electric circuit board.

【0004】なお、このような従来の電子装置は、その
製造時における取り扱いを容易とするとともに製造効率
を高いものとするために、多数個の電子装置を縦横に一
体的に配列形成して製造するようになした多数個取りの
製造方法により製造される。
[0004] Such a conventional electronic device is manufactured by integrally arranging a large number of electronic devices vertically and horizontally in order to facilitate handling at the time of manufacturing and to increase manufacturing efficiency. It is manufactured by a multi-cavity manufacturing method.

【0005】具体的には図7に断面図で示すように、先
ず中央部に各々が配線基板21となる多数の配線基板領域
31を仮想線である分割線32で区切って縦横に一体的に配
列形成するとともに各配線基板領域31を区切る分割線32
上に貫通孔33を形成し、各配線基板領域31の上面から貫
通孔33内壁を介して下面に導出する複数の配線導体23を
設けて成る母基板30を準備し、次いでこの母基板30の各
配線基板領域31上に電子部品24をその各電極が対応する
配線導体23に電気的に接続されるようにして搭載すると
ともに各配線基板領域31毎にその上面中央部に電子部品
24を覆うようにして樹脂製封止材25を液状で滴下させた
後、これを硬化させて固着させ、最後に母基板30を分割
線32に沿って分割することによって多数個が同時集約的
に製造される。
More specifically, as shown in the cross-sectional view of FIG.
31 is divided by a dividing line 32 which is an imaginary line so as to be integrally arrayed vertically and horizontally and a dividing line 32 dividing each wiring board region 31
A through-hole 33 is formed on the upper surface, and a mother board 30 is prepared by providing a plurality of wiring conductors 23 extending from the upper surface of each wiring board region 31 to the lower surface via the inner wall of the through-hole 33. An electronic component 24 is mounted on each wiring board region 31 such that each electrode thereof is electrically connected to a corresponding wiring conductor 23, and an electronic component is mounted on a central portion of the upper surface of each wiring board region 31.
After a resin sealing material 25 is dropped in a liquid state so as to cover 24, the resin sealing material 25 is cured and fixed, and finally, the mother substrate 30 is divided along the dividing line 32, whereby a large number of pieces are simultaneously intensively integrated. It is manufactured in.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、従来の
電子装置の製造方法では、母基板30の各配線基板領域31
の上面に電子部品24を覆うようにして樹脂製封止材25を
液状で滴下する際に、液状の樹脂製封止材25の一部がそ
の流動性により貫通孔33内に流れ込んでしまいやすい。
そして、貫通孔33内に樹脂製封止材25が流れ込むと、得
れらる電子装置において配線基板21の切り欠き部22に被
着された配線導体23を樹脂製封止材25が覆ってしまい、
その結果、その電子装置を外部電気回路基板に実装する
と、切り欠き部22内の配線導体23と外部電気回路基板の
接続用導体との間に立体的な半田の溜まりが良好に形成
されずに電子装置を外部電気回路基板に強固に実装する
ことができなくなってしまうこととなるという問題点が
あった。
However, in the conventional method of manufacturing an electronic device, each wiring board region 31 of the mother board 30 is not used.
When the resin sealing material 25 is dropped in a liquid state so as to cover the electronic component 24 on the upper surface, a part of the liquid resin sealing material 25 is likely to flow into the through hole 33 due to its fluidity. .
When the resin encapsulant 25 flows into the through-hole 33, the resin encapsulant 25 covers the wiring conductor 23 attached to the notch 22 of the wiring board 21 in the obtained electronic device. Sisters,
As a result, when the electronic device is mounted on the external electric circuit board, a three-dimensional solder pool is not formed well between the wiring conductor 23 in the notch 22 and the connection conductor of the external electric circuit board. There has been a problem that the electronic device cannot be firmly mounted on the external electric circuit board.

【0007】また、この従来の電子装置の製造方法で
は、母基板30の各配線基板領域31の上面に電子部品24を
覆うようにして樹脂製封止材25を液状で滴下する際に、
貫通孔33内に樹脂製封止材25が流れ込むのを防止するた
めに樹脂製封止材25を各配線基板領域31の中央部にそれ
ぞれ個別に滴下する必要があり、このため封止の作業が
極めて煩雑であるという問題点があった。
In this conventional method of manufacturing an electronic device, when a resin sealing material 25 is dropped in a liquid state on the upper surface of each wiring board region 31 of the mother board 30 so as to cover the electronic component 24,
In order to prevent the resin encapsulant 25 from flowing into the through holes 33, it is necessary to individually drop the resin encapsulant 25 at the center of each wiring board region 31. Is extremely complicated.

【0008】本発明はかかる従来の問題点に鑑み案出さ
れたものであり、その目的は、得られる電子装置におい
て、配線基板の側面に形成した切り欠き部内の配線導体
が樹脂製封止材で覆われることがなく、外部電気回路に
強固に実装することが可能な電子装置の製造方法を提供
することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide an obtained electronic device in which a wiring conductor in a cutout formed in a side surface of a wiring board is made of a resin sealing material. It is an object of the present invention to provide a method of manufacturing an electronic device which can be firmly mounted on an external electric circuit without being covered by a device.

【0009】また、本発明の別の目的は、母基板の各配
線基板領域の上面に電子部品を覆うようにして樹脂製封
止材を液状で滴下する際に、その作業が簡便な電子装置
の製造方法を提供することにある。
Another object of the present invention is to provide an electronic device which is simple in that a resin sealing material is dropped in a liquid state on the upper surface of each wiring board region of a mother board so as to cover the electronic component. It is to provide a manufacturing method of.

【0010】[0010]

【課題を解決するための手段】本発明の電子装置の製造
方法は、上層の絶縁層と下層の絶縁層とを積層して成
り、中央部に各々が分割線で区切られて縦横に配列形成
された複数の配線基板領域を有し、各配線基板領域を区
切る分割線上に下層の絶縁層を貫通して上端が上層の絶
縁層で塞がれた切欠き用穴を設けるとともに各配線基板
領域の上面から内部および切欠き用穴の内壁を介して下
面に導出する配線導体を設けて成る母基板を準備する工
程と、この母基板の各配線基板領域の上面に電子部品を
搭載するとともにその各電極を配線導体に電気的に接続
する工程と、母基板上の全配線基板領域にわたり各配線
基板領域および各電子部品を覆うようにして樹脂製封止
材を液状で塗布するとともに硬化させる工程と、母基板
および樹脂製封止材を分割線に沿って分割する工程とを
具備することを特徴とするものである。
A method of manufacturing an electronic device according to the present invention comprises laminating an upper insulating layer and a lower insulating layer, and forming a vertical and horizontal array, each of which is separated by a dividing line at the center. A plurality of wiring board areas, and a notch hole whose upper end is closed by an upper insulating layer through a lower insulating layer on a dividing line separating each wiring board area, and each wiring board area Preparing a mother board provided with a wiring conductor leading out from the upper surface to the lower surface through the inside and the inner wall of the notch hole, mounting electronic components on the upper surface of each wiring board region of the mother board, and A step of electrically connecting each electrode to a wiring conductor, and a step of applying and curing a resin sealing material in a liquid form so as to cover each wiring board area and each electronic component over the entire wiring board area on the mother board. And mother board and resin sealing material It is characterized in that it comprises a step of dividing along the dividing line.

【0011】本発明の電子装置の製造方法によれば、母
基板が上層の絶縁層と下層の絶縁層とを積層して形成し
て成り、各配線基板領域を区切る分割線上に下層の絶縁
層を貫通して上端が上層の絶縁層で塞がれた切欠き用穴
を設けるとともに各配線基板領域の上面から内部および
切欠き用穴の内壁を介して下面に導出する配線導体を設
けて成るので、この母基板上に各配線基板領域および電
子部品を覆うようにして樹脂製封止材を液状で塗布する
際、切欠き用穴内に樹脂製封止材が流れ込むことは一切
ない。
According to the method of manufacturing an electronic device of the present invention, the mother substrate is formed by laminating an upper insulating layer and a lower insulating layer, and the lower insulating layer is formed on a dividing line for dividing each wiring board region. And a wiring conductor extending from the upper surface of each wiring board region to the inside and the lower surface through the inner wall of the notch hole. Therefore, when the resin sealing material is applied in a liquid state on the mother board so as to cover each wiring board area and the electronic component, the resin sealing material does not flow into the notch holes at all.

【0012】また、本発明の電子装置の製造方法によれ
ば、母基板上の全配線基板領域にわたり各配線基板領域
および各電子部品を覆うようにして樹脂製封止材を液状
で塗布することから、樹脂製封止材を各配線基板領域上
にまとめて塗布することができる。
According to the method of manufacturing an electronic device of the present invention, a resin sealing material is applied in a liquid state so as to cover each wiring board area and each electronic component over the entire wiring board area on the mother board. Therefore, the resin sealing material can be applied to each wiring board region collectively.

【0013】[0013]

【発明の実施の形態】次に、本発明の電子装置の製造方
法を添付の図面を基に説明する。
Next, a method for manufacturing an electronic device according to the present invention will be described with reference to the accompanying drawings.

【0014】図2および図3は、それぞれ本発明の製造
方法により製造される電子装置の実施の形態の一例を示
す断面図および斜視図であり、1は配線基板、2は電子
部品、3は樹脂製封止材である。
FIGS. 2 and 3 are a sectional view and a perspective view, respectively, showing an embodiment of an electronic device manufactured by the manufacturing method of the present invention, wherein 1 is a wiring board, 2 is an electronic component, and 3 is It is a resin sealing material.

【0015】配線基板1は、酸化アルミニウム質焼結体
や窒化アルミニウム質焼結体・ムライト質焼結体・窒化
珪素質焼結体・炭化珪素質焼結体・ガラスセラミックス
等の電気絶縁材料から成る上層の絶縁層1aおよび下層
の絶縁層1bが積層された略四角平板状である。そし
て、下層の絶縁層1bの側面には上端が上層の絶縁層1
aで塞がれた複数の切り欠き部4が形成されており、上
層の絶縁層1aの上面から内部および切り欠き部4を介
して下層の絶縁層1bの下面にかけてはタングステンや
モリブデン・銅・銀等の金属粉末メタライズから成る複
数の配線導体5が被着形成されている。
The wiring board 1 is made of an electrically insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon nitride sintered body, a silicon carbide sintered body, and a glass ceramic. The upper insulating layer 1a and the lower insulating layer 1b are laminated in a substantially square plate shape. On the side surface of the lower insulating layer 1b, the upper end has an upper insulating layer 1b.
a plurality of cutouts 4 are formed, which are covered with tungsten, molybdenum, copper, etc. from the upper surface of the upper insulating layer 1a to the inside and the lower surface of the lower insulating layer 1b via the cutouts 4. A plurality of wiring conductors 5 made of a metal powder of silver or the like are adhered and formed.

【0016】配線基板1は、電子部品2を支持するとと
もに配線導体5が電子部品2の各電極を外部電気回路基
板に接続するための導電路として機能し、その上面には
電子部品2が搭載されている。なお、配線導体5は通常
であれば、その表面に1〜10μm程度の厚みのニッケル
めっきおよび0.1 〜3μm程度の厚みの金めっきが順次
被着されている。
The wiring board 1 supports the electronic component 2 and the wiring conductor 5 functions as a conductive path for connecting each electrode of the electronic component 2 to an external electric circuit board, and the electronic component 2 is mounted on the upper surface thereof. Have been. The wiring conductor 5 is usually provided with a nickel plating having a thickness of about 1 to 10 μm and a gold plating having a thickness of about 0.1 to 3 μm on the surface thereof.

【0017】配線基板1に搭載された電子部品2は、例
えば半導体集積回路素子等の半導体素子であり、その下
面に図示しない複数の電極を有している。そして、その
各電極が配線導体5に例えば半田や金等から成るバンプ
6を介して電気的に接続されている。なお、この例では
電子部品3はその下面に電極を有するとともに各電極と
配線導体5とがバンプ6を介して電気的に接続されてい
るが、電子部品3はその上面に電極を有するとともに各
電極がボンディングワイヤ等を介して配線導体5に電気
的に接続されていてもよい。
The electronic component 2 mounted on the wiring board 1 is a semiconductor element such as a semiconductor integrated circuit element, for example, and has a plurality of electrodes (not shown) on the lower surface thereof. Each of the electrodes is electrically connected to the wiring conductor 5 via a bump 6 made of, for example, solder or gold. In this example, the electronic component 3 has an electrode on its lower surface and each electrode and the wiring conductor 5 are electrically connected via a bump 6. However, the electronic component 3 has an electrode on its upper surface and The electrode may be electrically connected to the wiring conductor 5 via a bonding wire or the like.

【0018】また、配線基板1の上面にはその全面およ
び電子部品2を覆うようにしてエポキシ樹脂等の樹脂か
ら成る樹脂製封止材3が固着されている。樹脂製封止材
3は、配線基板1上に電子部品2を覆うようにして固着
されることにより電子部品2を気密に封止して外部環境
から保護する保護部材として機能する。
A resin sealing material 3 made of a resin such as epoxy resin is fixed on the upper surface of the wiring board 1 so as to cover the entire surface and the electronic component 2. The resin sealing material 3 is fixed on the wiring board 1 so as to cover the electronic component 2, thereby functioning as a protection member that hermetically seals the electronic component 2 and protects the electronic component 2 from the external environment.

【0019】この電子装置は、配線導体5で配線基板1
の切り欠き部4内および下面に被着された部位を外部電
気回路基板の接続用導体に半田を介して接続することに
より外部電気回路基板に実装され、これにより電子部品
2の各電極が配線導体5を介して外部電気回路に電気的
に接続されることとなる。このとき、配線基板1の側面
に形成された切り欠き部4内に被着された配線導体5と
外部電気回路基板の接続用導体との間に半田の溜まりが
立体的に良好に形成されて電子装置が外部電気回路基板
に極めて強固に実装される。
In this electronic device, the wiring substrate 5 is
Are mounted on the external electric circuit board by connecting the portions adhered to the inside and the lower surface of the notch 4 to the connection conductors of the external electric circuit board via solder, whereby each electrode of the electronic component 2 is connected to the wiring. It is electrically connected to an external electric circuit via the conductor 5. At this time, the solder pool is well formed three-dimensionally between the wiring conductor 5 attached in the notch 4 formed on the side surface of the wiring board 1 and the connection conductor of the external electric circuit board. The electronic device is very firmly mounted on the external electric circuit board.

【0020】次に、本発明の製造方法を適用して上述の
電子装置を製造する方法を工程順に説明する。
Next, a method of manufacturing the above electronic device by applying the manufacturing method of the present invention will be described in the order of steps.

【0021】まず、図1(a)に断面図で示すように、
主として酸化アルミニウム質焼結体や窒化アルミニウム
質焼結体・ムライト質焼結体・窒化珪素質焼結体・炭化
珪素質焼結体・ガラスセラミックス等の電気絶縁材料か
ら成る上層の絶縁層10aおよび下層の絶縁層10bを積層
して成り、中央部に各々が前記配線基板1となる多数の
配線基板領域11を仮想線である分割線12で区切って縦横
に配列形成するとともに各配線基板領域11を区切る分割
線12上に下層の絶縁層10bを貫通して上端が上層の絶縁
層10aで塞がれた切欠き用穴13を形成し、各配線基板領
域11の上面から内部および貫通孔13の内壁を介して下面
に導出するタングステンやモリブデン・銅・銀等の金属
粉末メタライズから成る配線導体5を被着形成して成る
母基板10を準備する。
First, as shown in the sectional view of FIG.
The upper insulating layer 10a mainly composed of an electrically insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon nitride sintered body, a silicon carbide sintered body, and a glass ceramic. A lower insulating layer 10b is laminated, and a large number of wiring board areas 11 each of which becomes the wiring board 1 are formed in the center by dividing the board by dividing lines 12 which are imaginary lines and arranged vertically and horizontally. A notch hole 13 whose upper end is closed by the upper insulating layer 10a is formed through the lower insulating layer 10b on the dividing line 12 that separates the inner and the through holes 13 from the upper surface of each wiring board region 11. A mother substrate 10 is prepared by depositing and forming a wiring conductor 5 made of metal powder of a metal powder such as tungsten, molybdenum, copper, silver or the like led out to the lower surface through the inner wall of the substrate.

【0022】母基板10は、上層の絶縁層10aおよび下層
の絶縁層10bが酸化アルミニウム質焼結体から成る場合
であれば、酸化アルミニウム・酸化珪素・酸化カルシウ
ム・酸化マグネシウム等の原料粉末に適当な有機バイン
ダおよび溶剤を添加混合して泥漿状となすとともに、こ
れを従来周知のドクタブレード法を採用してシート状に
形成して2枚のセラミックグリーンシートを得て、しか
る後、これらのセラミックグリーンシートに適当な打ち
抜き加工およびタングステンやモリブデン等の金属粉末
を含む金属ペーストの印刷を施すとともに上下に積層
し、これを還元雰囲気中、約1600℃の温度で焼成するこ
とによって製作される。なお、母基板10の配線導体5に
は、その露出表面にニッケルめっき層および金めっき層
等のめっき金属層を電解めっき法や無電解めっき法によ
り適当な厚みに鍍着させておく。
If the upper insulating layer 10a and the lower insulating layer 10b are made of an aluminum oxide sintered body, the mother substrate 10 is suitable for a raw material powder of aluminum oxide, silicon oxide, calcium oxide, magnesium oxide or the like. The mixture is mixed with an organic binder and a solvent to form a slurry, which is formed into a sheet by employing a well-known doctor blade method to obtain two ceramic green sheets. The green sheet is manufactured by performing appropriate punching and printing a metal paste containing a metal powder such as tungsten or molybdenum, stacking the green sheet on top and bottom, and firing this at a temperature of about 1600 ° C. in a reducing atmosphere. The wiring conductor 5 of the mother board 10 is plated with a plating metal layer such as a nickel plating layer and a gold plating layer to an appropriate thickness on the exposed surface by electrolytic plating or electroless plating.

【0023】次に、図1(b)に断面図で示すように、
母基板10の各配線基板領域11上面に半導体集積回路素子
等の電子部品2を搭載するとともにその各電極を例えば
半田や金から成るバンプ6を介して対応する配線導体5
に電気的に接続する。なお、電子部品2の各電極を半田
や金から成るバンプ6を介して配線導体5に電気的に接
続させるには、例えば、電子部品2の各電極に半田や金
から成るバンプ6を予め取着させておくとともに、この
バンプ6を対応する配線導体5に溶着や圧着等により接
合する方法が採用される。
Next, as shown in the sectional view of FIG.
The electronic component 2 such as a semiconductor integrated circuit element is mounted on the upper surface of each wiring board area 11 of the mother board 10 and its electrodes are connected to the corresponding wiring conductors 5 via bumps 6 made of, for example, solder or gold.
Electrically connected to In order to electrically connect the electrodes of the electronic component 2 to the wiring conductor 5 via the bumps 6 made of solder or gold, for example, the bumps 6 made of solder or gold are previously applied to the electrodes of the electronic component 2. In addition, a method is employed in which the bumps 6 are bonded to the corresponding wiring conductors 5 by welding, pressure bonding, or the like.

【0024】次に、図1(c)に断面図で示すように、
母基板10上の全配線基板領域11にわたり各配線基板領域
11およびこれに搭載された各電子部品2を覆うようにし
て例えばエポキシ樹脂やポリイミド樹脂・フェノール樹
脂・ビスマレイミドトリアジン樹脂等の熱硬化性樹脂か
ら成る樹脂製封止材3を液状で塗布するとともに硬化さ
せる。
Next, as shown in the sectional view of FIG.
Each wiring board area over the entire wiring board area 11 on the mother board 10
11 and a resin sealing material 3 made of a thermosetting resin such as an epoxy resin, a polyimide resin, a phenol resin, a bismaleimide triazine resin, or the like, is applied in a liquid state so as to cover the electronic components 2 mounted thereon. Let it cure.

【0025】なお、母基板10上に樹脂製封止材3を液状
で塗布するには、液状樹脂を一定量ずつ吐出可能なノズ
ルを母基板10上に配置するとともに、このノズルを水平
方向に移動させながらノズルから一定量の液状の樹脂製
封止材3を吐出させる方法や液状の樹脂製封止材3をス
クリーン印刷法により母基板10上に塗布する方法等が採
用され得る。このとき、配線導体3が被着された切欠き
用穴13は、その上端が上層の絶縁層10aで塞がれている
ことから、母基板10の上に塗布した樹脂製封止材3が切
欠き用穴13内に流れ込むことは一切ない。同時に、樹脂
製封止材3を母基板10上の全配線基板領域11にわたり塗
布することから、樹脂製被覆材3を各配線基板領域11上
にまとめて塗布することができ、その結果、樹脂製封止
材3の塗布の作業性が極めて簡便となる。また、母基板
10上に塗布した樹脂製封止材3を硬化させるには、例え
ば熱硬化法や紫外線硬化法により硬化させる方法が採用
され得る。
In order to apply the resin sealing material 3 to the mother substrate 10 in a liquid state, a nozzle capable of discharging a predetermined amount of the liquid resin is arranged on the mother substrate 10 and the nozzle is moved horizontally. A method of discharging a fixed amount of the liquid resin sealing material 3 from the nozzle while moving, a method of applying the liquid resin sealing material 3 on the mother substrate 10 by a screen printing method, or the like can be adopted. At this time, since the notch hole 13 to which the wiring conductor 3 is attached is closed at the upper end by the upper insulating layer 10a, the resin sealing material 3 applied on the mother substrate 10 is not used. It does not flow into the notch hole 13 at all. At the same time, since the resin sealing material 3 is applied over the entire wiring board area 11 on the mother board 10, the resin coating material 3 can be applied on each wiring board area 11 at a time. The workability of applying the sealing material 3 becomes extremely simple. Also, mother board
In order to cure the resin sealing material 3 applied on the top 10, a method of curing by, for example, a thermosetting method or an ultraviolet curing method can be adopted.

【0026】そして、最後に図1(d)に断面図で示す
ように、母基板10および樹脂製封止材3をダイアモンド
カッタやレーザカッタを用いて分割線12に沿って分割す
ることにより、図2および図3に示すように、下層の絶
縁層1bの側面に上端が上層の絶縁層1aで塞がれた切
り欠き部4を有するとともに上面から内部および切り欠
き部4の側面を介して下面に導出する配線導体5が被着
された配線基板1の上に電子部品2がその各電極を対応
する配線導体5にバンプ6を介して電気的に接続される
ようにして搭載され、配線基板1の上面に電子部品2を
覆うようにして樹脂製封止材3が固着された電子装置が
多数個同時集約的に製造される。この場合、切り欠き部
4の側面に被着させた配線導体5が樹脂製封止材3で被
覆されることは一切ないので、電子装置を外部電気回路
基板に実装すると、切り欠き部4内の配線導体5と外部
電気回路基板の接続導体との間に半田の溜りが立体的に
良好に形成形成されて電子装置が外部電気回路基板に極
めて強固に実装される。
Finally, as shown in the sectional view of FIG. 1D, the mother board 10 and the resin sealing material 3 are divided along a dividing line 12 using a diamond cutter or a laser cutter. As shown in FIGS. 2 and 3, the lower insulating layer 1 b has a cutout 4 on the side surface thereof, the upper end of which is closed by the upper insulating layer 1 a, and from the upper surface through the inside and the side surface of the cutout 4. The electronic component 2 is mounted on the wiring board 1 on which the wiring conductor 5 extending to the lower surface is attached so that each electrode is electrically connected to the corresponding wiring conductor 5 via the bump 6. A large number of electronic devices in which a resin sealing material 3 is fixed on the upper surface of the substrate 1 so as to cover the electronic components 2 are simultaneously and intensively manufactured. In this case, since the wiring conductor 5 attached to the side surface of the notch 4 is not covered with the resin sealing material 3 at all, when the electronic device is mounted on the external electric circuit board, the inside of the notch 4 A solder pool is formed between the wiring conductor 5 and the connection conductor of the external electric circuit board in a three-dimensionally favorable manner, and the electronic device is extremely firmly mounted on the external electric circuit board.

【0027】かくして、本発明の電子装置の製造方法に
よれば、母基板10の各配線基板領域11の上面に電子部品
2をその各電極が配線導体5に電気的に接続されるよう
にして搭載した後、母基板10上の全配線基板領域11にわ
たり各配線基板領域11およびこれに搭載された各電子部
品2を覆うようにして樹脂製封止材3を液状で塗布する
とともに硬化させ、最後に母基板10および樹脂製封止材
3を分割線12に沿って分割することにより、実装強度に
優れた多数個の電子装置が簡便に同時集約的に製作され
ることとなる。
Thus, according to the method of manufacturing an electronic device of the present invention, the electronic component 2 is placed on the upper surface of each wiring board region 11 of the mother board 10 such that each electrode is electrically connected to the wiring conductor 5. After mounting, the resin sealing material 3 is applied in a liquid state and cured so as to cover each wiring board area 11 and each electronic component 2 mounted thereon over the entire wiring board area 11 on the mother board 10, Finally, by dividing the mother board 10 and the resinous encapsulant 3 along the dividing line 12, a large number of electronic devices having excellent mounting strength can be simply and simultaneously manufactured.

【0028】なお、本発明は上述の実施の形態の一例に
限定されるものではなく、本発明の要旨を逸脱しない範
囲であれば種々の変更は可能である。例えば図4に断面
図で示すように、母基板10の外周部に枠状のダム部14を
設け、このダム部14の内側に樹脂製封止材3を液状で塗
布するようにしてもよい。この場合、ダム部14により樹
脂製封止材3が母基板10の外部に流れ出るのを有効に防
止することができるとともに、全配線基板領域11におい
て樹脂製封止材3の厚みを均一なものとすることがで
き、形状ばらつきの小さい電子装置を提供できる。ま
た、このようなダム部14により母基板10の機械的な強度
を高いものとすることができる。なお、このようなダム
部14は、絶縁層10a・10bと同一材料により絶縁層10a
と一体的に形成すればよい。
The present invention is not limited to the above-described embodiment, and various changes can be made without departing from the scope of the present invention. For example, as shown in the sectional view of FIG. 4, a frame-shaped dam portion 14 may be provided on the outer peripheral portion of the mother substrate 10, and the resin sealing material 3 may be applied in a liquid state inside the dam portion 14. . In this case, it is possible to effectively prevent the resin sealing material 3 from flowing out of the mother board 10 by the dam portion 14, and to make the thickness of the resin sealing material 3 uniform in the entire wiring board region 11. And an electronic device with small shape variation can be provided. Further, the mechanical strength of the mother substrate 10 can be increased by such a dam portion 14. The dam portion 14 is made of the same material as the insulating layers 10a and 10b.
And may be integrally formed.

【0029】[0029]

【発明の効果】本発明の電子装置の製造方法によれば、
母基板を上層の絶縁層と下層の絶縁層とを積層して形成
し、各配線基板領域を区切る分割線上に下層の絶縁層を
貫通して上端が上層の絶縁層で塞がれた切欠き用穴を設
けるとともに各配線基板領域の上面から内部および切欠
き用穴の内壁を介して下面に導出する配線導体を設けた
ことから、この母基板上に各配線基板領域および電子部
品を覆うようにして樹脂製封止材を液状で塗布する際、
切欠き用穴内に樹脂製封止材が流れ込むことは一切な
い。したがって、得られる電子装置において、配線基板
側面の切り欠き部に被着させた配線導体が樹脂製封止材
で被覆されることは一切なく、この電子装置を外部電気
回路基板に実装すると、切り欠き部内の配線導体と外部
電気回路基板の接続導体との間に半田の溜りが立体的に
良好に形成されて電子装置が外部電気回路基板に極めて
強固に実装される また、本発明の電子装置の製造方法によれば、母基板上
の全配線基板領域にわたり各配線基板領域および各電子
部品を覆うようにして樹脂製封止材を液状で塗布するこ
とから、樹脂製封止材を各配線基板領域上にまとめて塗
布することができ、その結果、封止の作業性が極めて簡
便となる。
According to the electronic device manufacturing method of the present invention,
Notch formed by laminating a mother board with an upper insulating layer and a lower insulating layer, penetrating the lower insulating layer on a dividing line that separates each wiring board area, and closing the upper end with the upper insulating layer Since the wiring conductors are provided to extend from the upper surface of each wiring board region to the inside and the lower surface through the inner wall of the notch hole, the wiring board region and the electronic components are covered on the mother board. When applying the resin sealing material in liquid,
The resin sealing material never flows into the notch holes. Therefore, in the obtained electronic device, the wiring conductor adhered to the cutout on the side surface of the wiring board is not covered with the resin sealing material at all, and when this electronic device is mounted on the external electric circuit board, Solder wells are formed three-dimensionally and well between the wiring conductor in the notch and the connection conductor of the external electric circuit board, and the electronic device is extremely firmly mounted on the external electric circuit board. According to the manufacturing method of (1), the resin sealing material is applied in a liquid state so as to cover each wiring board area and each electronic component over the entire wiring board area on the mother board. Coating can be performed collectively on the substrate region, and as a result, the workability of sealing becomes extremely simple.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(d)は、それぞれ本発明の電子装置
の製造方法を説明するための工程毎の断面図である。
FIGS. 1A to 1D are cross-sectional views for explaining steps of a method for manufacturing an electronic device according to the present invention.

【図2】図1に示す本発明の電子装置の製造方法により
製造される電子装置の例を示す断面図である。
FIG. 2 is a cross-sectional view illustrating an example of an electronic device manufactured by the method for manufacturing an electronic device of the present invention illustrated in FIG.

【図3】図2に示す電子装置の斜視図である。FIG. 3 is a perspective view of the electronic device shown in FIG. 2;

【図4】本発明の電子装置の製造方法の他の例を説明す
るための断面図である。
FIG. 4 is a cross-sectional view for explaining another example of the method for manufacturing an electronic device of the present invention.

【図5】従来の製造方法により製造された電子装置の例
を示す断面図である。
FIG. 5 is a cross-sectional view illustrating an example of an electronic device manufactured by a conventional manufacturing method.

【図6】図5に示す電子装置の斜視図である。6 is a perspective view of the electronic device shown in FIG.

【図7】従来の電子装置の製造方法を説明するための断
面図である。
FIG. 7 is a cross-sectional view for explaining a conventional method for manufacturing an electronic device.

【符号の説明】[Explanation of symbols]

2・・・電子部品 3・・・樹脂製封止材 5・・・配線導体 10・・・母基板 10a・・・上層の絶縁層 10b・・・下層の絶縁層 11・・・配線基板領域 12・・・分割線 13・・・切欠き用穴 2 ... electronic parts 3 ... resin sealing material 5 ... wiring conductor 10 ... mother board 10 a ... upper insulating layer 10 b ... lower insulating layer 11 ... wiring board area 12 ・ ・ ・ Parting line 13 ・ ・ ・ Notch hole

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 4M109 AA01 BA03 CA05 CA12 DA06 DA10 DB15 DB16 DB17 EA02 EA07 EA08  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M109 AA01 BA03 CA05 CA12 DA06 DA10 DB15 DB16 DB17 EA02 EA07 EA08

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】上層の絶縁層と下層の絶縁層とを積層して
成り、中央部に各々が分割線で区切られて縦横に配列形
成された複数の配線基板領域を有し、前記各配線基板領
域を区切る分割線上に前記下層の絶縁層を貫通して上端
が前記上層の絶縁層で塞がれた切欠き用穴を設けるとと
もに前記各配線基板領域の上面から内部および前記切欠
き用穴の内壁を介して下面に導出する配線導体を設けて
成る母基板を準備する工程と、 前記母基板の各配線基板領域の上面に電子部品を搭載す
るとともに該電子部品の各電極を前記配線導体に電気的
に接続する工程と、 前記母基板上の全配線基板領域にわたり各配線基板領域
および各電子部品を覆うようにして樹脂製封止材を液状
で塗布するとともに硬化させる工程と、 前記母基板および前記樹脂製封止材を前記分割線に沿っ
て分割する工程とを具備することを特徴とする電子装置
の製造方法。
A plurality of wiring board regions each formed by laminating an upper insulating layer and a lower insulating layer, each of which is divided by a dividing line and arranged vertically and horizontally at a central portion; A notch hole whose upper end is closed by the upper insulating layer is provided on a parting line dividing the substrate region through the lower insulating layer, and the inner and the notch holes are formed from the upper surface of each wiring board region. Preparing a mother board provided with a wiring conductor leading out to the lower surface via the inner wall of the mother board; mounting an electronic component on the upper surface of each wiring board area of the mother board and connecting each electrode of the electronic component to the wiring conductor A step of applying a resin sealing material in a liquid state and curing the same so as to cover each wiring board area and each electronic component over the entire wiring board area on the mother board; and Substrate and the resin sealing material Method of manufacturing an electronic device characterized by comprising a step of dividing along the dividing line.
JP33874599A 1999-11-29 1999-11-29 Producing method for electronic device Pending JP2001156218A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33874599A JP2001156218A (en) 1999-11-29 1999-11-29 Producing method for electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33874599A JP2001156218A (en) 1999-11-29 1999-11-29 Producing method for electronic device

Publications (1)

Publication Number Publication Date
JP2001156218A true JP2001156218A (en) 2001-06-08

Family

ID=18321070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33874599A Pending JP2001156218A (en) 1999-11-29 1999-11-29 Producing method for electronic device

Country Status (1)

Country Link
JP (1) JP2001156218A (en)

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