JP4651686B2 - Electronic component mounting package manufacturing method and electronic device manufacturing method - Google Patents

Electronic component mounting package manufacturing method and electronic device manufacturing method Download PDF

Info

Publication number
JP4651686B2
JP4651686B2 JP2008045176A JP2008045176A JP4651686B2 JP 4651686 B2 JP4651686 B2 JP 4651686B2 JP 2008045176 A JP2008045176 A JP 2008045176A JP 2008045176 A JP2008045176 A JP 2008045176A JP 4651686 B2 JP4651686 B2 JP 4651686B2
Authority
JP
Japan
Prior art keywords
wiring
layer
wiring board
electronic component
sealing material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008045176A
Other languages
Japanese (ja)
Other versions
JP2008147706A (en
Inventor
日出和 田丸
明彦 舟橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2008045176A priority Critical patent/JP4651686B2/en
Publication of JP2008147706A publication Critical patent/JP2008147706A/en
Application granted granted Critical
Publication of JP4651686B2 publication Critical patent/JP4651686B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Description

本発明は、配線基板上に半導体素子や圧電振動子等の電子部品を搭載するための電子部品搭載用パッケージおよび電子部品を樹脂封止材で覆うことにより気密に封止して成る電子装置の製造方法に関するものである。   The present invention relates to an electronic component mounting package for mounting an electronic component such as a semiconductor element or a piezoelectric vibrator on a wiring board, and an electronic device that is hermetically sealed by covering the electronic component with a resin sealing material. It relates to a manufacturing method.

従来、コンピュータ等の情報処理装置や携帯電話機等の通信端末装置等に実装される樹脂封止型の小型の電子装置として、例えば図5に断面図で示すものが知られている。
この電子装置は、酸化アルミニウム質焼結体等の電気絶縁材料から成る絶縁基板の側面に上下面間にわたる切欠き部44を複数有するとともに、上面から切欠き部44を介して下面にかけて導出された、タングステン(W)やモリブデン(Mo)等の金属粉末のメタライズ層から成る複数の配線層45が形成された、大きさが数mm角程度の四角平板状の配線基板41を有する。そして、配線基板41上に半導体素子等の電子部品42を、その各電極が対応する配線層45に導体バンプ46を介して電気的に接続されるようにして搭載するとともに、配線基板41の上面中央部に電子部品42を覆うようにして例えばエポキシ樹脂等の樹脂から成る樹脂封止材43を固着させることにより、電子部品42を気密に封止して成る電子装置が作製される。
2. Description of the Related Art Conventionally, as a resin-sealed small electronic device mounted on an information processing device such as a computer or a communication terminal device such as a mobile phone, for example, a cross-sectional view shown in FIG. 5 is known.
This electronic device has a plurality of notches 44 extending between the upper and lower surfaces on the side surface of an insulating substrate made of an electrically insulating material such as an aluminum oxide sintered body, and is led out from the upper surface to the lower surface via the notches 44. In addition, a wiring board 41 having a square plate shape with a size of several square mm is formed, on which a plurality of wiring layers 45 made of a metallized layer of a metal powder such as tungsten (W) or molybdenum (Mo) are formed. Then, an electronic component 42 such as a semiconductor element is mounted on the wiring board 41 so that each electrode thereof is electrically connected to the corresponding wiring layer 45 via the conductor bump 46, and the upper surface of the wiring board 41. An electronic device in which the electronic component 42 is hermetically sealed is manufactured by fixing a resin sealing material 43 made of a resin such as an epoxy resin so as to cover the electronic component 42 at the center.

しかしながら、この従来の電子装置では、電子部品42を覆うようにして液状の樹脂封止材43を滴下する際に、液状の樹脂封止材43の一部がその流動性により切欠き部44内に流れ込んでしまいやすい。そして、切欠き部44内に樹脂封止材43が流れ込むと、切欠き部44内に被着された配線層45を樹脂封止材43が覆ってしまう。その結果、電子装置を外部電気回路基板に実装する際に、切欠き部44内の配線層45と外部電気回路基板の接続用導体との間に立体的な半田の溜まり(いわゆるメニスカス)が良好に形成されず、電子装置を外部電気回路基板に強固に実装することができなくなるという問題点があった。   However, in this conventional electronic device, when the liquid resin sealing material 43 is dropped so as to cover the electronic component 42, a part of the liquid resin sealing material 43 is in the notch 44 due to its fluidity. It is easy to flow into. When the resin sealing material 43 flows into the notch 44, the resin sealing material 43 covers the wiring layer 45 deposited in the notch 44. As a result, when the electronic device is mounted on the external electric circuit board, a three-dimensional solder pool (so-called meniscus) is good between the wiring layer 45 in the notch 44 and the connection conductor of the external electric circuit board. In other words, the electronic device cannot be firmly mounted on the external electric circuit board.

そこで、本願出願人は、図3に断面図で示すような電子装置を提案した(下記の特許文献1参照)。すなわち、下層の絶縁層21bの側面に上端が上層の絶縁層21aで塞がれた切欠き部24を有するとともに、上面から内部および切欠き部24の内面を介して下面に導出するWやMo等の金属粉末のメタライズ層から成る配線層25が被着された配線基板21を有し、その上面に、電子部品22がその各電極と対応する配線層25に導体バンプ26を介して電気的に接続されるようにして搭載され、電子部品22を覆うように樹脂封止材23が固着された電子装置である。   Therefore, the applicant of the present application has proposed an electronic device as shown in a sectional view in FIG. 3 (see Patent Document 1 below). That is, the side surface of the lower insulating layer 21b has a notch portion 24 whose upper end is closed by the upper insulating layer 21a, and W or Mo led out from the upper surface to the lower surface through the inside and the inner surface of the notch portion 24. A wiring substrate 25 having a metal layer made of a metal powder such as a metal layer is attached, and an electronic component 22 is electrically connected to the wiring layer 25 corresponding to each electrode via conductor bumps 26 on the upper surface thereof. The electronic device is mounted so as to be connected to the resin, and the resin sealing material 23 is fixed so as to cover the electronic component 22.

この電子装置によれば、切欠き部24の上端が上層の絶縁層21aで塞がれるため、樹脂封止材23が切欠き部24内に流れ込んで切欠き部24内に被着させた配線層25が樹脂封止材23で覆われることは一切ない。その結果、電子装置を外部電気回路基板に実装する際に、切欠き部24内の配線層25と外部電気回路基板の接続用導体との間に半田の溜りが立体的に良好に形成されて、電子装置が外部電気回路基板に極めて強固に実装されるというものである。   According to this electronic device, since the upper end of the notch 24 is blocked by the upper insulating layer 21a, the resin sealing material 23 flows into the notch 24 and is deposited in the notch 24. The layer 25 is never covered with the resin sealing material 23. As a result, when the electronic device is mounted on the external electric circuit board, the solder pool is three-dimensionally favorably formed between the wiring layer 25 in the notch 24 and the connection conductor of the external electric circuit board. The electronic device is mounted very firmly on the external electric circuit board.

なお、このような従来の電子装置は、その製造時における取り扱いを容易とするとともに製造効率を高いものとするために、図4に断面図で示すように、多数個の電子装置を縦横に一体的に配列形成して製造するように成した多数個取りの製造方法により製造される。   Such a conventional electronic device has a large number of electronic devices integrated vertically and horizontally as shown in a cross-sectional view in FIG. 4 in order to facilitate handling during manufacture and to increase manufacturing efficiency. It is manufactured by a multi-cavity manufacturing method that is configured to be manufactured in an array.

まず、配線基板21となる多数の配線基板領域31を仮想線で示した分割線32で区切って縦横に一体的に配列形成するとともに、分割線32上に、下層の絶縁層30bを貫通して上端が上層の絶縁層30aで塞がれた切欠き部用の穴33を形成し、各配線基板領域31の上面から内部および穴33の内面を介して下面に導出される複数の配線層25を被着形成して成る母基板30を準備する。次に、母基板30の各配線基板領域31上に電子部品22をその各電極が対応する配線層25に電気的に接続されるようにして搭載するとともに、母基板30上の全ての配線基板領域31の電子部品22を覆うように液状の樹脂封止材34をスクリーン印刷法により塗布する。その後、樹脂封止材34を硬化させて固着させ、最後に母基板30を分割線32に沿って分割することによって多数個の電子装置が同時集約的に製造される。   First, a large number of wiring board regions 31 to be the wiring board 21 are divided by dividing lines 32 indicated by imaginary lines and integrally formed vertically and horizontally, and the lower insulating layer 30b is penetrated on the dividing lines 32. A plurality of wiring layers 25 led out from the upper surface of each wiring board region 31 to the inner surface and the inner surface of the hole 33 to the lower surface are formed by forming a notch hole 33 whose upper end is blocked by the upper insulating layer 30a. A mother substrate 30 formed by depositing is prepared. Next, the electronic component 22 is mounted on each wiring board region 31 of the mother board 30 so that each electrode is electrically connected to the corresponding wiring layer 25, and all the wiring boards on the mother board 30 are mounted. A liquid resin sealing material 34 is applied by screen printing so as to cover the electronic component 22 in the region 31. Thereafter, the resin sealing material 34 is cured and fixed, and finally, the mother board 30 is divided along the dividing lines 32, whereby a large number of electronic devices are manufactured simultaneously and collectively.

また、母基板30の複数の配線層25は、その露出表面にニッケルめっき層および金めっき層等のめっき金属層が電解めっき法や無電解めっき法により被着されており、これにより、配線層25の腐食を有効に防止することができる。   In addition, the plurality of wiring layers 25 of the mother board 30 have plating metal layers such as a nickel plating layer and a gold plating layer deposited on the exposed surfaces thereof by an electrolytic plating method or an electroless plating method. 25 corrosion can be effectively prevented.

そして、分割して得られる電子装置の切欠き部24内の配線層25と外部電気回路基板の接続用導体との間に半田の溜りが立体的に良好に形成されて、電子装置を外部電気回路基板に極めて強固に実装させることができる。
特開2001−356064号公報
A solder pool is formed in a three-dimensionally good manner between the wiring layer 25 in the notch 24 of the electronic device obtained by the division and the connection conductor of the external electric circuit board, and the electronic device is connected to the external electric device. It can be mounted very firmly on the circuit board.
JP 2001-356064 A

しかしながら、上述の特許文献1の電子装置においては、母基板30をめっき液中に浸漬して配線層25の露出表面にニッケルめっき層および金めっき層等のめっき金属層を電解めっき法や無電解めっき法により被着させているが、その際、切欠き部用の穴33は各配線基板領域31を区切る分割線32上にあるとともに上端が上層の絶縁層30aで塞がれていることから、穴33の内面に被着形成された配線層25の上端部では空気が抜けきれずに空気溜りが生じ易くなっており、そのため空気溜りの発生している配線層25の上端部はめっき液中に浸れなくなる。その結果、電子装置の切欠き部24内の配線層25の腐食を防ぐことができなくなり、腐食により半田の流れ性が低下するとともに半田の接合力も低下するため、切欠き部24内の配線層25と外部電気回路基板の接続用導体との間に半田のメニスカスを良好に形成することができなくなる。すると、電子装置を外部電気回路基板に強固に実装させることができないという問題点が生じていた。   However, in the electronic device disclosed in Patent Document 1 described above, the base substrate 30 is immersed in a plating solution, and a plating metal layer such as a nickel plating layer and a gold plating layer is applied to the exposed surface of the wiring layer 25 by an electrolytic plating method or electroless method. In this case, the hole 33 for the notch is on the dividing line 32 that divides each wiring board region 31 and the upper end is blocked by the upper insulating layer 30a. In the upper end portion of the wiring layer 25 deposited on the inner surface of the hole 33, air cannot escape and air is easily trapped. Therefore, the upper end portion of the wiring layer 25 where the air pool is generated is the plating solution. Cannot soak inside. As a result, the corrosion of the wiring layer 25 in the cutout 24 of the electronic device cannot be prevented, and the flowability of the solder and the bonding strength of the solder are also reduced due to the corrosion. It becomes impossible to satisfactorily form a solder meniscus between 25 and the connecting conductor of the external electric circuit board. As a result, the electronic device cannot be firmly mounted on the external electric circuit board.

したがって、本発明はかかる従来の問題点に鑑み完成されたものであり、その目的は、配線基板の切欠き部内の配線層にめっき金属層を良好に被着させることにより配線層を外部電気回路に確実かつ強固に接続させることができる電子部品搭載用パッケージおよび電子装置を提供することにある。   Accordingly, the present invention has been completed in view of such conventional problems, and the object thereof is to satisfactorily attach a plated metal layer to a wiring layer in a notch portion of a wiring board so that the wiring layer is connected to an external electric circuit. Another object of the present invention is to provide an electronic component mounting package and an electronic device that can be securely and firmly connected to each other.

本発明の電子部品搭載用パッケージの製造方法は、電子部品が搭載される搭載部および前記電子部品の電極が接続される配線層が形成された配線基板領域が多数配列されているとともに、下面且つ隣接しあう前記配線基板領域の分割線上に切欠き部用の非貫通の穴を有し、前記配線層と電気的に接続されるとともに前記穴の内面の下端から上側に向けて途中まで形成された側面導体層を有し、前記分割線に沿って分割することにより前記配線基板領域および前記切欠き部を有する多数の電子部品搭載用パッケージを得るための母基板を準備する工程と、前記側面導体層の表面にめっき金属層を形成する工程とを具備することを特徴とする。   The method for manufacturing an electronic component mounting package according to the present invention includes a mounting portion on which an electronic component is mounted and a plurality of wiring board regions on which wiring layers to which electrodes of the electronic component are connected are arranged, and a lower surface and A non-through hole for a notch is formed on a parting line of the wiring board region adjacent to each other, is electrically connected to the wiring layer, and is formed partway from the lower end of the inner surface of the hole toward the upper side. Preparing a mother board for obtaining a package for mounting a large number of electronic components having the wiring board region and the notch by dividing along the dividing line, And a step of forming a plated metal layer on the surface of the conductor layer.

本発明の電子装置の製造方法は、電子部品が搭載される搭載部および前記電子部品の電極が接続される配線層が形成された配線基板領域が多数配列されているとともに、下面且つ隣接しあう前記配線基板領域の分割線上に切欠き部用の非貫通の穴を有し、前記配線層と電気的に接続されるとともに前記穴の内面の下端から上側に向けて途中まで形成された側面導体層を有する母基板を準備する工程と、前記側面導体層の表面にめっき金属層を形成する工程と、前記母基板の上面における前記多数の配線基板領域の前記搭載部にそれぞれ電子部品を搭載する工程と前記母基板の上面における前記多数の配線基板領域および前記電子部品を覆うように樹脂封止材を塗布する工程と、前記分割線に沿って前記母基板および前記樹脂封止材を分割することにより前記切欠き部を有する多数の電子装置を得る工程とを順次具備することを特徴とする。   In the method for manufacturing an electronic device according to the present invention, a plurality of wiring board regions in which a mounting portion on which an electronic component is mounted and a wiring layer to which an electrode of the electronic component is connected are formed are arranged, and the lower surface and adjacent to each other. A side conductor that has a non-through hole for a notch on the dividing line of the wiring board region, is electrically connected to the wiring layer, and is formed partway from the lower end of the inner surface of the hole toward the upper side. A step of preparing a mother board having a layer, a step of forming a plated metal layer on the surface of the side conductor layer, and mounting electronic components on the mounting portions of the multiple wiring board regions on the upper surface of the mother board, respectively. A step of applying a resin sealing material so as to cover the plurality of wiring substrate regions and the electronic component on the upper surface of the mother substrate, and dividing the mother substrate and the resin sealing material along the dividing line. Characterized by sequentially and a step of obtaining a large number of electronic devices having the notch by the.

本発明の電子装置の製造方法において好ましくは、上記本発明の電子装置の製造方法において、前記樹脂封止材は前記母基板の上面の前記非貫通の穴に対応する部位を覆っていることを特徴とする。   Preferably, in the electronic device manufacturing method of the present invention, in the electronic device manufacturing method of the present invention, the resin sealing material covers a portion corresponding to the non-through hole on the upper surface of the mother board. Features.

本発明は、多数個の電子部品搭載用パッケージまたは電子装置を作製するために母基板の状態での切欠き部用の穴の内面にめっき金属層を被着させても、空気溜りが発生しやすい切欠き部用の穴の上端部には側面導体層が被着されていないため、側面導体層の上端部にめっき金属層が形成されずに腐食されるのを有効に防止できる。   In the present invention, even when a plated metal layer is deposited on the inner surface of a hole for a notch in the state of a mother board in order to produce a large number of electronic component mounting packages or electronic devices, an air pocket is generated. Since the side conductor layer is not attached to the upper end portion of the hole for the notch which is easy to be formed, it is possible to effectively prevent corrosion without forming the plated metal layer on the upper end portion of the side conductor layer.

本発明の電子部品搭載用パッケージ(以下、パッケージともいう)および電子装置の製造方法を以下に詳細に説明する。図1は本発明により製造したパッケージについて実施の形態の一例を示す断面図であり、図1において、1は配線基板、2はIC,LSI等の半導体素子などから成る電子部品、3は樹脂封止材である。   An electronic component mounting package (hereinafter also referred to as a package) and an electronic device manufacturing method of the present invention will be described in detail below. FIG. 1 is a cross-sectional view showing an embodiment of a package manufactured according to the present invention. In FIG. 1, 1 is a wiring board, 2 is an electronic component made of a semiconductor element such as an IC or LSI, and 3 is a resin seal. Stop material.

パッケージは、配線基板1の主面に電子部品2が搭載される搭載部7および電子部品2の電極が接続される配線層5が形成されているとともに、配線基板1の角部および側面の少なくとも一方に、配線基板1の下面から上面に向けて形成された切欠き部4に配線層5と電気的に接続された側面導体層5aが形成されているものであって、切欠き部4は、配線基板1の下面から上面に向けて途中まで形成されているとともに、側面導体層5aは、切欠き部4の下端から上側に向けて途中まで形成されている。   The package includes a mounting portion 7 on which the electronic component 2 is mounted on the main surface of the wiring substrate 1 and a wiring layer 5 to which the electrodes of the electronic component 2 are connected, and at least corners and side surfaces of the wiring substrate 1. On the other hand, a side conductor layer 5a electrically connected to the wiring layer 5 is formed in a notch 4 formed from the lower surface to the upper surface of the wiring board 1, and the notch 4 The wiring board 1 is formed halfway from the lower surface toward the upper surface, and the side conductor layer 5a is formed halfway from the lower end of the cutout portion 4 toward the upper side.

配線基板1は、酸化アルミニウム質焼結体や窒化アルミニウム質焼結体,ムライト質焼結体,窒化珪素質焼結体,炭化珪素質焼結体,ガラスセラミックス等の電気絶縁材料から成り、例えば上層の絶縁層1a,中間層の絶縁層1bおよび下層の絶縁層1cが積層された四角平板状である。そして、絶縁層1b,1cの側面には、上端が絶縁層1aで塞がれた複数の切欠き部4が形成されている。   The wiring board 1 is made of an electrically insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon nitride sintered body, a silicon carbide sintered body, or a glass ceramic. The upper insulating layer 1a, the intermediate insulating layer 1b, and the lower insulating layer 1c are in the form of a square plate. A plurality of notches 4 whose upper ends are closed by the insulating layer 1a are formed on the side surfaces of the insulating layers 1b and 1c.

この配線基板1は、例えば酸化アルミニウム質焼結体から成る場合、酸化アルミニウム,酸化珪素,酸化マグネシウム,酸化カルシウム等の原料粉末に適当な有機バインダー,溶剤等を添加混合して泥漿状となし、これを従来周知のドクターブレード法やカレンダーロール法等によりシート状に成形してセラミックグリーンシート(セラミック生シートで、以下、グリーンシートともいう)を得、しかる後、グリーンシートに切欠き部4となる貫通孔を打ち抜き加工で形成するとともに、電子部品2を搭載するための絶縁層1a〜1c用の各グリーンシートを積層し、高温(約1600℃)で焼成し一体化することで形成される。   When this wiring board 1 is made of, for example, an aluminum oxide sintered body, a suitable organic binder, solvent, etc. are added to and mixed with raw material powders such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide to form a slurry. This is formed into a sheet shape by a conventionally known doctor blade method, calendar roll method or the like to obtain a ceramic green sheet (ceramic raw sheet, hereinafter also referred to as a green sheet), and then the notch 4 is formed on the green sheet. The through-holes to be formed are formed by punching, and the green sheets for the insulating layers 1a to 1c for mounting the electronic component 2 are laminated, fired at a high temperature (about 1600 ° C.), and integrated. .

また、配線基板1は、電子部品2を支持するものであるとともに、絶縁層1aの上面から内部および切欠き部4内に被着された側面導体層5aを介して絶縁層1cの下面にかけて被着された複数の配線層5が形成されている。この配線層5は、電子部品2の各電極を外部電気回路に接続するための導電路として機能し、配線基板1の上面の配線層5には電子部品2の各電極が例えば半田や金等から成る導体バンプ6を介して電気的に接続される。   The wiring board 1 supports the electronic component 2 and covers the insulating layer 1a from the upper surface to the lower surface of the insulating layer 1c via the side conductor layer 5a attached to the inside and the notch 4. A plurality of attached wiring layers 5 are formed. The wiring layer 5 functions as a conductive path for connecting each electrode of the electronic component 2 to an external electric circuit, and each electrode of the electronic component 2 is, for example, solder, gold or the like on the wiring layer 5 on the upper surface of the wiring substrate 1. It is electrically connected through a conductor bump 6 made of

なお、図1の例では、電子部品2はその下面に電極を有するとともに各電極と配線層5とが導体バンプ6を介して電気的に接続されているが、電子部品2はその上面に電極を有するとともに各電極がボンディングワイヤ等を介して配線層5に電気的に接続されていてもよい。   In the example of FIG. 1, the electronic component 2 has electrodes on its lower surface and each electrode and the wiring layer 5 are electrically connected via the conductor bumps 6, but the electronic component 2 has electrodes on its upper surface. Each electrode may be electrically connected to the wiring layer 5 through a bonding wire or the like.

配線層5および側面導体5aは、例えばWやMo等の金属粉末に適当な有機溶剤,溶媒を添加混合して得た金属ペーストを、配線基板1となるグリーンシートに予めスクリーン印刷法により所定パターンに印刷塗布しておくことによって、絶縁層1a〜1cのそれぞれの所定位置に被着形成されている。   For the wiring layer 5 and the side conductor 5a, for example, a metal paste obtained by adding and mixing a suitable organic solvent and solvent to a metal powder such as W or Mo is preliminarily patterned in a green sheet to be the wiring substrate 1 by screen printing. In this way, the insulating layers 1a to 1c are deposited on the respective predetermined positions by printing.

なお、配線層5および側面導体5aの露出する表面に、ニッケル(Ni),金(Au)等の耐蝕性に優れる金属を1〜20μm程度の厚みで被着させておくのがよく、配線層5および側面導体層5aが酸化腐蝕するのを有効に防止できるとともに、配線層5と電子部品2との固着、側面導体層5aと外部電気回路基板の接続用導体との接続を強固にすることができる。従って、配線層5および側面導体層5aの露出表面には、厚さ1〜10μm程度のNiめっき層と厚さ0.1〜3μm程度のAuめっき層が、電解めっき法や無電解めっき法により順次被着されていることが好ましい。   It should be noted that a metal having excellent corrosion resistance, such as nickel (Ni), gold (Au), or the like is preferably deposited on the exposed surfaces of the wiring layer 5 and the side conductor 5a in a thickness of about 1 to 20 μm. 5 and the side conductor layer 5a can be effectively prevented from being oxidized and corroded, and the connection between the wiring layer 5 and the electronic component 2 and the connection between the side conductor layer 5a and the connection conductor of the external electric circuit board can be strengthened. Can do. Therefore, on the exposed surfaces of the wiring layer 5 and the side conductor layer 5a, an Ni plating layer having a thickness of about 1 to 10 μm and an Au plating layer having a thickness of about 0.1 to 3 μm are formed by an electrolytic plating method or an electroless plating method. It is preferred that they are deposited sequentially.

また、配線基板1の上面には、電子部品2を覆うようにして配線基板1の上面の全面に、エポキシ樹脂等の樹脂から成る樹脂封止材3が固着される。樹脂封止材3は、配線基板1上に電子部品2を覆うようにして固着されることにより電子部品2を気密に封止して外部環境から保護する保護部材として機能する。   A resin sealing material 3 made of a resin such as an epoxy resin is fixed to the upper surface of the wiring board 1 so as to cover the electronic component 2 over the entire upper surface of the wiring board 1. The resin sealing material 3 functions as a protective member that hermetically seals the electronic component 2 and protects it from the external environment by being fixed on the wiring board 1 so as to cover the electronic component 2.

パッケージは、図2の断面図に示すように、その製造時における取り扱いを容易とするとともに製造効率を高いものとするために、多数個のパッケージを縦横に一体的に配列形成した多数個取り配線基板として製作される。   As shown in the cross-sectional view of FIG. 2, the package is a multi-piece wiring in which a large number of packages are integrally arranged vertically and horizontally in order to facilitate handling during manufacturing and to increase manufacturing efficiency. Manufactured as a substrate.

多数個取り用の母基板10は、酸化アルミニウム質焼結体や窒化アルミニウム質焼結体,ムライト質焼結体,窒化珪素質焼結体,炭化珪素質焼結体,ガラスセラミックス等の電気絶縁材料から成る、上層の絶縁層10a,中間層の絶縁層10bおよび下層の絶縁層10cを積層して成る。また母基板10は、その中央部に各々が配線基板1となる多数の配線基板領域11が仮想線である分割線12で区切って縦横に配列形成されるとともに、分割線12上に絶縁層10b,10cを貫通して上端が絶縁層10aで塞がれた切欠き部用の穴13が形成されている。また、各配線基板領域11の上面から内部および穴13の内面に被着された側面導体層5aを介して下面に導出されるメタライズ層から成る配線層5が被着形成されている。   A large number of mother substrates 10 are used for electrical insulation of aluminum oxide sintered bodies, aluminum nitride sintered bodies, mullite sintered bodies, silicon nitride sintered bodies, silicon carbide sintered bodies, glass ceramics, and the like. The upper insulating layer 10a, the intermediate insulating layer 10b, and the lower insulating layer 10c made of materials are laminated. In addition, the mother board 10 has a plurality of wiring board regions 11, each of which becomes the wiring board 1, at the central portion thereof, which are divided by vertical dividing lines 12 and arranged vertically and horizontally, and an insulating layer 10 b on the dividing lines 12. , 10c and a hole 13 for a notch whose upper end is blocked by an insulating layer 10a is formed. In addition, a wiring layer 5 made of a metallized layer led out from the upper surface of each wiring board region 11 to the lower surface through a side conductor layer 5a attached to the inside and the inner surface of the hole 13 is deposited.

この母基板10は、絶縁層10a〜10cが酸化アルミニウム質焼結体から成る場合、酸化アルミニウム,酸化珪素,酸化カルシウム,酸化マグネシウム等の原料粉末に適当な有機バインダおよび溶剤を添加混合して泥漿状と成し、これを従来周知のドクタブレード法によりシート状に形成して3枚のグリーンシートを得て、しかる後、これらのグリーンシートに適当な打ち抜き加工および配線層5,側面導体層5a用のWやMo等の金属粉末を含む金属ペーストの塗布印刷を施すとともに上下に積層し、これを還元雰囲気中で約1600℃の温度で焼成することによって製作される。   When the insulating layers 10a to 10c are made of an aluminum oxide sintered body, the mother substrate 10 is prepared by adding a suitable organic binder and solvent to a raw material powder such as aluminum oxide, silicon oxide, calcium oxide, magnesium oxide and the like. This is formed into a sheet shape by a conventionally known doctor blade method to obtain three green sheets. Thereafter, these green sheets are appropriately punched and wiring layers 5, side conductor layers 5a. It is manufactured by applying and printing a metal paste containing a metal powder such as W or Mo for use and laminating it up and down and firing it at a temperature of about 1600 ° C. in a reducing atmosphere.

なお、母基板10の配線層5および側面導体層5aには、その露出表面にニッケルめっき層および金めっき層等のめっき金属層を電解めっき法や無電解めっき法により被着させておく。   It should be noted that a plating metal layer such as a nickel plating layer and a gold plating layer is applied to the exposed surface of the wiring layer 5 and the side conductor layer 5a of the mother substrate 10 by an electrolytic plating method or an electroless plating method.

そして、母基板10の各配線基板領域11上面に電子部品2を搭載するとともにその各電極を例えば半田や金から成る導体バンプ6を介して対応する配線層5に電気的に接続する。電子部品2の各電極を導体バンプ6を介して配線層5に電気的に接続させるには、例えば、電子部品2の各電極に導体バンプ6を予め取着させておき、この導体バンプ6を対応する配線層5に溶着や圧着等により接合する方法が採用される。   Then, the electronic component 2 is mounted on the upper surface of each wiring board region 11 of the mother board 10 and each electrode thereof is electrically connected to the corresponding wiring layer 5 through a conductor bump 6 made of, for example, solder or gold. In order to electrically connect each electrode of the electronic component 2 to the wiring layer 5 via the conductor bump 6, for example, the conductor bump 6 is attached in advance to each electrode of the electronic component 2, and the conductor bump 6 is attached to the electrode 5. A method of joining to the corresponding wiring layer 5 by welding or pressure bonding is employed.

そして、母基板10上の全配線基板領域11にわたり各配線基板領域11およびこれに搭載された各電子部品2を覆うようにして、例えばエポキシ樹脂やポリイミド樹脂,フェノール樹脂,ビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る液状の樹脂封止材14を塗布し、硬化させる。   The wiring board regions 11 and the electronic components 2 mounted on the wiring board regions 11 on the mother board 10 are covered so as to cover, for example, epoxy resin, polyimide resin, phenol resin, bismaleimide triazine resin, etc. A liquid resin sealing material 14 made of a thermosetting resin is applied and cured.

なお、母基板10上に液状の樹脂封止材14を塗布するには、一定量ずつ吐出可能なノズルを母基板10上に配置し、このノズルを水平方向に移動させながらノズルから一定量の液状の樹脂封止材14を吐出させる方法、または液状の樹脂封止材14をスクリーン印刷法により母基板10上に塗布する方法等が採用される。このとき、側面導体層5aが被着された穴13はその上端が絶縁層10aで塞がれていることから、母基板10上に塗布した樹脂封止材14が穴13内に流れ込むことは一切ない。同時に、樹脂封止材14を母基板10上の全配線基板領域11にわたり塗布することから、樹脂封止材14を各配線基板領域11上にまとめて塗布することができ、その結果、樹脂封止材14の塗布の作業性が極めて簡易になる。また、母基板10上に塗布した樹脂封止材14を硬化させるには、例えば熱硬化法や紫外線硬化法により硬化させる方法が採用される。   In order to apply the liquid resin sealing material 14 on the mother substrate 10, a nozzle capable of discharging a certain amount is arranged on the mother substrate 10, and a certain amount of nozzle is moved from the nozzle while moving the nozzle in the horizontal direction. A method of discharging the liquid resin sealing material 14 or a method of applying the liquid resin sealing material 14 onto the mother substrate 10 by a screen printing method is employed. At this time, since the upper end of the hole 13 to which the side conductor layer 5a is deposited is closed by the insulating layer 10a, the resin sealing material 14 applied on the mother substrate 10 does not flow into the hole 13. Nothing at all. At the same time, since the resin sealing material 14 is applied over the entire wiring substrate region 11 on the mother substrate 10, the resin sealing material 14 can be applied collectively on each wiring substrate region 11, and as a result, the resin sealing The workability of applying the stopper 14 is extremely simple. Moreover, in order to harden the resin sealing material 14 apply | coated on the motherboard 10, the method of hardening by the thermosetting method or the ultraviolet curing method is employ | adopted, for example.

そして、最後に、母基板10および樹脂封止材14をダイアモンドカッターやレーザカッターを用いて分割線12に沿って分割することにより、中間層の絶縁層1bおよび下層の絶縁層1cの側面に、上端が上層の絶縁層1aで塞がれた切欠き部4が形成される。また、上面から内部および切欠き部4内の側面導体層5aを介して下面に導出される配線層5が被着された配線基板1の上面に、電子部品2がその各電極と対応する配線層5に導体バンプ6を介して電気的に接続されるようにして搭載され、配線基板1の上面に電子部品2を覆うようにして樹脂封止材3が固着された電子装置が多数個同時集約的に製作される。   Finally, by dividing the mother substrate 10 and the resin sealing material 14 along the dividing line 12 using a diamond cutter or a laser cutter, the side surfaces of the intermediate insulating layer 1b and the lower insulating layer 1c are A cutout portion 4 whose upper end is blocked by the upper insulating layer 1a is formed. Further, on the upper surface of the wiring board 1 to which the wiring layer 5 led out from the upper surface to the lower surface through the side conductor layers 5a inside and in the notch portion 4 is attached, the electronic component 2 has wiring corresponding to each electrode. A large number of electronic devices mounted on the layer 5 so as to be electrically connected via the conductor bumps 6 and having the resin sealing material 3 fixed on the upper surface of the wiring board 1 so as to cover the electronic component 2 are simultaneously provided. Made intensively.

パッケージにおいて、切欠き部4の上端部には側面導体層5aが形成されていない非形成部が設けられているが、その非形成部の上下方向の長さは0.05〜0.5mmが好ましい。0.05mm未満では、非形成部の長さが短いため、母基板10の切欠き部用の穴13の内面にめっき金属層を被着させる際に非形成部に空気溜りが発生すると、側面導体層5aの一部を空気溜りが覆ってしまい、側面導体層5aの一部にめっき金属層が被着されない事態が生じ易い。0.5mmを超えると、非形成部の長さが長くなるため、空気溜りが側面導体5aの一部を覆うことは無く良好にめっき金属層を被着できるものの、配線基板1の厚みが厚くなり薄型化に不利となる。   In the package, a non-formed portion where the side conductor layer 5a is not formed is provided at the upper end portion of the notch portion 4, and the vertical length of the non-formed portion is 0.05 to 0.5 mm. preferable. If it is less than 0.05 mm, the length of the non-formed part is short, and therefore when the plated metal layer is deposited on the inner surface of the hole 13 for the notch part of the mother substrate 10, The air reservoir covers a part of the conductor layer 5a, and a situation in which the plated metal layer is not deposited on a part of the side conductor layer 5a easily occurs. If the thickness exceeds 0.5 mm, the length of the non-formed portion becomes long, so that the air reservoir does not cover a part of the side conductor 5a and the plated metal layer can be satisfactorily deposited, but the thickness of the wiring board 1 is thick. This is disadvantageous for thinning.

パッケージは、配線基板1の主面に電子部品2が搭載される搭載部7および電子部品2の電極が接続される配線層5が形成されているとともに、配線基板1の角部および側面の少なくとも一方に、配線基板1の下面から上面に向けて形成された切欠き部4に配線層5と電気的に接続された側面導体層5aが形成されている。このような構造により、切欠き部4内の側面導体層5aと外部電気回路基板の接続用導体との間に半田のメニスカスが良好に形成されて、外部電気回路基板に極めて強固に実装させることができる。   The package includes a mounting portion 7 on which the electronic component 2 is mounted on the main surface of the wiring substrate 1 and a wiring layer 5 to which the electrodes of the electronic component 2 are connected, and at least corners and side surfaces of the wiring substrate 1. On the other hand, a side conductor layer 5 a electrically connected to the wiring layer 5 is formed in a cutout portion 4 formed from the lower surface to the upper surface of the wiring substrate 1. With such a structure, a good solder meniscus is formed between the side conductor layer 5a in the cutout portion 4 and the connection conductor of the external electric circuit board, and it is mounted on the external electric circuit board very firmly. Can do.

また、パッケージの切欠き部4は、配線基板1の下面から上面に向けて途中まで形成されているとともに、側面導体層5aは、切欠き部4下端から上側に向けて下層の絶縁層1c上面の位置まで形成されている。このようなパッケージは多数個取り配線基板として製造方法する際、母基板10の切欠き部用の穴13の内面にめっき金属層を被着させる際に、空気溜りが発生しやすい穴13の上端部に相当する中間層の絶縁層1bの側面には側面導体層5aが被着されていないため、側面導体層5aが腐食されるのを有効に防止できる。   Further, the cutout portion 4 of the package is formed partway from the lower surface to the upper surface of the wiring substrate 1, and the side conductor layer 5a is formed on the upper surface of the lower insulating layer 1c from the lower end of the cutout portion 4 to the upper side. It is formed to the position of. When such a package is manufactured as a multi-cavity wiring board, the upper end of the hole 13 is prone to air trapping when a plated metal layer is deposited on the inner surface of the hole 13 for the notch portion of the mother board 10. Since the side conductor layer 5a is not deposited on the side surface of the intermediate insulating layer 1b corresponding to the portion, it is possible to effectively prevent the side conductor layer 5a from being corroded.

また、電子装置は、上記パッケージと、搭載部7に搭載されるとともに配線層5に電気的に接続された電子部品2と、電子部品2を覆う樹脂封止材3とを具備したことにより、切欠き部4内の側面導体層5aと外部電気回路基板の接続用導体との間に半田のメニスカスが良好に形成されて電子装置が外部電気回路基板に極めて強固に実装される信頼性の高いものとなる。   Further, the electronic device includes the package, the electronic component 2 mounted on the mounting portion 7 and electrically connected to the wiring layer 5, and the resin sealing material 3 covering the electronic component 2. A highly reliable meniscus of solder is formed between the side conductor layer 5a in the notch 4 and the connection conductor of the external electric circuit board, so that the electronic device is mounted extremely firmly on the external electric circuit board. It will be a thing.

なお、本発明は上述の実施の形態の一例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。   Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

本発明の電子部品搭載用パッケージについて実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment about the electronic component mounting package of this invention. 図1の電子部品搭載用パッケージを母基板から多数個取りによって製造する製造方法を説明するための母基板の断面図である。It is sectional drawing of the motherboard for demonstrating the manufacturing method which manufactures the electronic component mounting package of FIG. 従来の電子部品搭載用パッケージの断面図である。It is sectional drawing of the conventional electronic component mounting package. 図3の電子部品搭載用パッケージを母基板から多数個取りによって製造する製造方法を説明するための母基板の断面図である。FIG. 4 is a cross-sectional view of a mother board for explaining a manufacturing method for producing a large number of electronic component mounting packages of FIG. 3 from a mother board. 従来の電子部品搭載用パッケージの他の例を示す断面図である。It is sectional drawing which shows the other example of the conventional electronic component mounting package.

符号の説明Explanation of symbols

1:配線基板
2:電子部品
3:樹脂封止材
5:配線層
5a:側面導体層
10:母基板
11:配線基板領域
12:分割線
13:切欠き部用の穴
1: Wiring board 2: Electronic component 3: Resin encapsulant 5: Wiring layer 5a: Side conductor layer 10: Mother board 11: Wiring board area 12: Dividing line 13: Hole for notch

Claims (3)

電子部品が搭載される搭載部および前記電子部品の電極が接続される配線層が形成された配線基板領域が多数配列されているとともに、下面且つ隣接しあう前記配線基板領域の分割線上に切欠き部用の非貫通の穴を有し、前記配線層と電気的に接続されるとともに前記穴の内面の下端から上側に向けて途中まで形成された側面導体層を有し、前記分割線に沿って分割することにより前記配線基板領域および前記切欠き部を有する多数の電子部品搭載用パッケージを得るための母基板を準備する工程と、
前記側面導体層の表面にめっき金属層を形成する工程とを具備することを特徴とする電子部品搭載用パッケージの製造方法。
A plurality of wiring board regions in which a mounting portion on which electronic components are mounted and wiring layers to which electrodes of the electronic components are connected are formed are arranged, and notches are formed on the lower surface and adjacent dividing lines of the wiring board regions. A non-through hole for a portion, and a side conductor layer that is electrically connected to the wiring layer and formed partway from the lower end of the inner surface of the hole toward the upper side, along the dividing line Preparing a mother board for obtaining a large number of electronic component mounting packages having the wiring board region and the cutout portion by dividing the wiring board area;
And a step of forming a plated metal layer on the surface of the side conductor layer.
電子部品が搭載される搭載部および前記電子部品の電極が接続される配線層が形成された配線基板領域が多数配列されているとともに、下面且つ隣接しあう前記配線基板領域の分割線上に切欠き部用の非貫通の穴を有し、前記配線層と電気的に接続されるとともに前記穴の内面の下端から上側に向けて途中まで形成された側面導体層を有する母基板を準備する工程と、
前記側面導体層の表面にめっき金属層を形成する工程と、
前記母基板の上面における前記多数の配線基板領域の前記搭載部にそれぞれ電子部品を搭載する工程と
前記母基板の上面における前記多数の配線基板領域および前記電子部品を覆うように樹脂封止材を塗布する工程と、
前記分割線に沿って前記母基板および前記樹脂封止材を分割することにより前記切欠き部を有する多数の電子装置を得る工程とを順次具備することを特徴とする電子装置の製造方法。
A plurality of wiring board regions in which a mounting portion on which electronic components are mounted and wiring layers to which electrodes of the electronic components are connected are formed are arranged, and notches are formed on the lower surface and adjacent dividing lines of the wiring board regions. Preparing a mother board having a non-through hole for a portion, electrically connected to the wiring layer, and having a side conductor layer formed partway from the lower end of the inner surface of the hole toward the upper side; ,
Forming a plated metal layer on the surface of the side conductor layer;
A step of mounting electronic components on the mounting portions of the multiple wiring board regions on the upper surface of the mother board, and a resin sealing material to cover the multiple wiring board regions and the electronic components on the upper surface of the mother board. Applying step;
And a step of sequentially obtaining a large number of electronic devices having the notches by dividing the mother substrate and the resin sealing material along the dividing line.
前記樹脂封止材は前記母基板の上面の前記非貫通の穴に対応する部位を覆っていることを特徴とする請求項2記載の電子装置の製造方法。   3. The method of manufacturing an electronic device according to claim 2, wherein the resin sealing material covers a portion corresponding to the non-through hole on the upper surface of the mother board.
JP2008045176A 2008-02-26 2008-02-26 Electronic component mounting package manufacturing method and electronic device manufacturing method Expired - Fee Related JP4651686B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008045176A JP4651686B2 (en) 2008-02-26 2008-02-26 Electronic component mounting package manufacturing method and electronic device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008045176A JP4651686B2 (en) 2008-02-26 2008-02-26 Electronic component mounting package manufacturing method and electronic device manufacturing method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2003116400A Division JP4150285B2 (en) 2003-04-21 2003-04-21 Mother board for electronic component mounting package

Publications (2)

Publication Number Publication Date
JP2008147706A JP2008147706A (en) 2008-06-26
JP4651686B2 true JP4651686B2 (en) 2011-03-16

Family

ID=39607449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008045176A Expired - Fee Related JP4651686B2 (en) 2008-02-26 2008-02-26 Electronic component mounting package manufacturing method and electronic device manufacturing method

Country Status (1)

Country Link
JP (1) JP4651686B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003243559A (en) * 2002-02-19 2003-08-29 Taiyo Yuden Co Ltd Terminal structure of wiring board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003243559A (en) * 2002-02-19 2003-08-29 Taiyo Yuden Co Ltd Terminal structure of wiring board

Also Published As

Publication number Publication date
JP2008147706A (en) 2008-06-26

Similar Documents

Publication Publication Date Title
JPWO2010041356A1 (en) Manufacturing method of electronic component module
CN107993985A (en) Electro part carrying substrate, electronic device and electronic module
JP6767204B2 (en) Boards for mounting electronic components, electronic devices and electronic modules
JP3699609B2 (en) Electronic component mounting board
US9526167B2 (en) Many-up wiring substrate, wiring board, and electronic device
JP2023091083A (en) Substrate for mounting electronic element, electronic device, and electronic module
JP4711823B2 (en) Electronic component storage package and electronic device
JP6780996B2 (en) Wiring boards, electronics and electronic modules
JP6698301B2 (en) Wiring board, electronic device and electronic module
JP4651686B2 (en) Electronic component mounting package manufacturing method and electronic device manufacturing method
JP4150285B2 (en) Mother board for electronic component mounting package
JP4912118B2 (en) Electronic component storage package and electronic device
JP2013207204A (en) Wiring mother board
US10937707B2 (en) Wiring substrate, electronic device, and electronic module
JP4272550B2 (en) Multiple wiring board
JP6933716B2 (en) Substrate for mounting electronic components, electronic devices and electronic modules
JP6978258B2 (en) Substrate for mounting electronic devices, electronic devices and electronic modules
WO2018097313A1 (en) Wiring board, electronic device, and electronic module
JP6737646B2 (en) Wiring board, electronic device and electronic module
JP2020035898A (en) Substrate for mounting electronic element, electronic apparatus, and electronic module
JP2013182909A (en) Multi-piece substrate for mounting electronic component
JP2013175659A (en) Multiple patterning wiring board
JP6818457B2 (en) Wiring boards, electronics and electronic modules
JP4986500B2 (en) Laminated substrate, electronic device and manufacturing method thereof.
JP5058071B2 (en) Electronic component mounting board

Legal Events

Date Code Title Description
TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101116

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20101214

R150 Certificate of patent or registration of utility model

Ref document number: 4651686

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131224

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees