JP2001117772A5 - - Google Patents

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Publication number
JP2001117772A5
JP2001117772A5 JP2000310363A JP2000310363A JP2001117772A5 JP 2001117772 A5 JP2001117772 A5 JP 2001117772A5 JP 2000310363 A JP2000310363 A JP 2000310363A JP 2000310363 A JP2000310363 A JP 2000310363A JP 2001117772 A5 JP2001117772 A5 JP 2001117772A5
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JP
Japan
Prior art keywords
instruction
instructions
data
instruction group
group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000310363A
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English (en)
Japanese (ja)
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JP2001117772A (ja
JP3776302B2 (ja
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Publication date
Priority claimed from US09/417,582 external-priority patent/US6711670B1/en
Application filed filed Critical
Publication of JP2001117772A publication Critical patent/JP2001117772A/ja
Publication of JP2001117772A5 publication Critical patent/JP2001117772A5/ja
Application granted granted Critical
Publication of JP3776302B2 publication Critical patent/JP3776302B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000310363A 1999-10-14 2000-10-11 コンピュータ・プログラムのハザードを検出するシステム Expired - Fee Related JP3776302B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/417,582 US6711670B1 (en) 1999-10-14 1999-10-14 System and method for detecting data hazards within an instruction group of a compiled computer program
US09/417582 1999-10-14

Publications (3)

Publication Number Publication Date
JP2001117772A JP2001117772A (ja) 2001-04-27
JP2001117772A5 true JP2001117772A5 (enExample) 2005-06-23
JP3776302B2 JP3776302B2 (ja) 2006-05-17

Family

ID=23654573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000310363A Expired - Fee Related JP3776302B2 (ja) 1999-10-14 2000-10-11 コンピュータ・プログラムのハザードを検出するシステム

Country Status (2)

Country Link
US (1) US6711670B1 (enExample)
JP (1) JP3776302B2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4368320B2 (ja) * 2005-03-16 2009-11-18 富士通株式会社 情報処理システム，パイプライン処理装置，ビジー判定プログラム及び同プログラムを記録したコンピュータ読取可能な記録媒体
GB2447907B (en) * 2007-03-26 2009-02-18 Imagination Tech Ltd Processing long-latency instructions in a pipelined processor
US20090150653A1 (en) * 2007-12-07 2009-06-11 Pedro Chaparro Monferrer Mechanism for soft error detection and recovery in issue queues
US8635501B2 (en) 2011-07-25 2014-01-21 Microsoft Corporation Detecting memory hazards in parallel computing
US8707107B1 (en) * 2011-12-09 2014-04-22 Symantec Corporation Systems and methods for proactively facilitating restoration of potential data failures
US9372695B2 (en) 2013-06-28 2016-06-21 Globalfoundries Inc. Optimization of instruction groups across group boundaries
US9348596B2 (en) 2013-06-28 2016-05-24 International Business Machines Corporation Forming instruction groups based on decode time instruction optimization
KR102179385B1 (ko) * 2013-11-29 2020-11-16 삼성전자주식회사 명령어를 실행하는 방법 및 프로세서, 명령어를 부호화하는 방법 및 장치 및 기록매체
US11409530B2 (en) * 2018-08-16 2022-08-09 Arm Limited System, method and apparatus for executing instructions

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2038264C (en) * 1990-06-26 1995-06-27 Richard James Eickemeyer In-memory preprocessor for a scalable compound instruction set machine processor
US5471591A (en) * 1990-06-29 1995-11-28 Digital Equipment Corporation Combined write-operand queue and read-after-write dependency scoreboard
KR100309566B1 (ko) * 1992-04-29 2001-12-15 리패치 파이프라인프로세서에서다중명령어를무리짓고,그룹화된명령어를동시에발행하고,그룹화된명령어를실행시키는방법및장치
US5481743A (en) * 1993-09-30 1996-01-02 Apple Computer, Inc. Minimal instruction set computer architecture and multiple instruction issue method
US5848288A (en) * 1995-09-20 1998-12-08 Intel Corporation Method and apparatus for accommodating different issue width implementations of VLIW architectures

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