JP2007531133A5 - - Google Patents

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Publication number
JP2007531133A5
JP2007531133A5 JP2007505612A JP2007505612A JP2007531133A5 JP 2007531133 A5 JP2007531133 A5 JP 2007531133A5 JP 2007505612 A JP2007505612 A JP 2007505612A JP 2007505612 A JP2007505612 A JP 2007505612A JP 2007531133 A5 JP2007531133 A5 JP 2007531133A5
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JP
Japan
Prior art keywords
instruction
computer processor
instructions
control
data processing
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Application number
JP2007505612A
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English (en)
Japanese (ja)
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JP2007531133A (ja
JP5198847B2 (ja
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Priority claimed from US10/813,628 external-priority patent/US7949856B2/en
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Publication of JP2007531133A publication Critical patent/JP2007531133A/ja
Publication of JP2007531133A5 publication Critical patent/JP2007531133A5/ja
Application granted granted Critical
Publication of JP5198847B2 publication Critical patent/JP5198847B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2007505612A 2004-03-31 2005-03-22 二重経路プロセッサの処理制御のための装置および方法 Expired - Lifetime JP5198847B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/813,628 US7949856B2 (en) 2004-03-31 2004-03-31 Method and apparatus for separate control processing and data path processing in a dual path processor with a shared load/store unit
US10/813,628 2004-03-31
PCT/GB2005/001059 WO2005096140A2 (en) 2004-03-31 2005-03-22 Apparatus and method for control processing in dual path processor

Publications (3)

Publication Number Publication Date
JP2007531133A JP2007531133A (ja) 2007-11-01
JP2007531133A5 true JP2007531133A5 (enExample) 2010-11-11
JP5198847B2 JP5198847B2 (ja) 2013-05-15

Family

ID=34962961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007505612A Expired - Lifetime JP5198847B2 (ja) 2004-03-31 2005-03-22 二重経路プロセッサの処理制御のための装置および方法

Country Status (8)

Country Link
US (2) US7949856B2 (enExample)
EP (2) EP1735700B1 (enExample)
JP (1) JP5198847B2 (enExample)
KR (1) KR20070026434A (enExample)
CN (1) CN100472433C (enExample)
CA (1) CA2560465A1 (enExample)
TW (2) TWI450192B (enExample)
WO (1) WO2005096140A2 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8484441B2 (en) 2004-03-31 2013-07-09 Icera Inc. Apparatus and method for separate asymmetric control processing and data path processing in a configurable dual path processor that supports instructions having different bit widths
US9047094B2 (en) * 2004-03-31 2015-06-02 Icera Inc. Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor
US7949856B2 (en) * 2004-03-31 2011-05-24 Icera Inc. Method and apparatus for separate control processing and data path processing in a dual path processor with a shared load/store unit
CN100456230C (zh) * 2007-03-19 2009-01-28 中国人民解放军国防科学技术大学 超长指令字与单指令流多数据流融合的计算群单元
US8281111B2 (en) * 2008-09-23 2012-10-02 Qualcomm Incorporated System and method to execute a linear feedback-shift instruction
US8755515B1 (en) 2008-09-29 2014-06-17 Wai Wu Parallel signal processing system and method
JP2011028543A (ja) * 2009-07-27 2011-02-10 Renesas Electronics Corp 情報処理システム及びその情報処理方法
US8842121B2 (en) * 2011-02-03 2014-09-23 Intel Corporation Stream compaction for rasterization
CN102945150B (zh) * 2012-09-18 2015-11-18 苏州华周胶带有限公司 一种实现多功能用户界面的方法
KR20140126189A (ko) * 2013-04-22 2014-10-30 삼성전자주식회사 프로세서의 멀티 실행 모드 지원 장치 및 방법
US9772848B2 (en) 2014-11-14 2017-09-26 Intel Corporation Three-dimensional morton coordinate conversion processors, methods, systems, and instructions
US9772850B2 (en) 2014-11-14 2017-09-26 Intel Corporation Morton coordinate adjustment processors, methods, systems, and instructions
US9772849B2 (en) 2014-11-14 2017-09-26 Intel Corporation Four-dimensional morton coordinate conversion processors, methods, systems, and instructions
CN107251504B (zh) * 2015-02-12 2021-08-27 华为技术有限公司 使用stf自动检测wlan分组的系统和方法
US10402199B2 (en) 2015-10-22 2019-09-03 Texas Instruments Incorporated Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor
CN105912307B (zh) * 2016-04-27 2018-09-07 浪潮(北京)电子信息产业有限公司 一种Flash控制器数据处理方法及装置
CN111242293B (zh) * 2020-01-13 2023-07-18 腾讯科技（深圳）有限公司 一种处理部件、数据处理的方法以及电子设备
WO2022251984A1 (zh) * 2021-05-29 2022-12-08 华为技术有限公司 一种数据处理方法及装置

Family Cites Families (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228498A (en) * 1977-10-12 1980-10-14 Dialog Systems, Inc. Multibus processor for increasing execution speed using a pipeline effect
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
DE69031257T2 (de) 1989-09-21 1998-02-12 Texas Instruments Inc Integrierte Schaltung mit einem eingebetteten digitalen Signalprozessor
CA2073516A1 (en) * 1991-11-27 1993-05-28 Peter Michael Kogge Dynamic multi-mode parallel processor array architecture computer system
JPH05324430A (ja) 1992-05-26 1993-12-07 Toshiba Corp データ処理装置
US5423051A (en) * 1992-09-24 1995-06-06 International Business Machines Corporation Execution unit with an integrated vector operation capability
US5600801A (en) 1993-07-15 1997-02-04 Dell Usa, L.P. Multiple function interface device for option card
US5600810A (en) * 1994-12-09 1997-02-04 Mitsubishi Electric Information Technology Center America, Inc. Scaleable very long instruction word processor with parallelism matching
US6052773A (en) * 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5737631A (en) * 1995-04-05 1998-04-07 Xilinx Inc Reprogrammable instruction set accelerator
JP2931890B2 (ja) * 1995-07-12 1999-08-09 三菱電機株式会社 データ処理装置
JP3658072B2 (ja) 1996-02-07 2005-06-08 株式会社ルネサステクノロジ データ処理装置およびデータ処理方法
JPH09265397A (ja) * 1996-03-29 1997-10-07 Hitachi Ltd Ｖｌｉｗ命令用プロセッサ
GB2311882B (en) 1996-04-04 2000-08-09 Videologic Ltd A data processing management system
US5956518A (en) * 1996-04-11 1999-09-21 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
DE19634031A1 (de) * 1996-08-23 1998-02-26 Siemens Ag Prozessor mit Pipelining-Aufbau
US6006321A (en) * 1997-06-13 1999-12-21 Malleable Technologies, Inc. Programmable logic datapath that may be used in a field programmable device
US5922065A (en) * 1997-10-13 1999-07-13 Institute For The Development Of Emerging Architectures, L.L.C. Processor utilizing a template field for encoding instruction sequences in a wide-word format
JP3451921B2 (ja) 1998-03-30 2003-09-29 松下電器産業株式会社 プロセッサ
EP0953898A3 (en) * 1998-04-28 2003-03-26 Matsushita Electric Industrial Co., Ltd. A processor for executing Instructions from memory according to a program counter, and a compiler, an assembler, a linker and a debugger for such a processor
US6226735B1 (en) * 1998-05-08 2001-05-01 Broadcom Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements
US6292845B1 (en) * 1998-08-26 2001-09-18 Infineon Technologies North America Corp. Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively
DE19843640A1 (de) * 1998-09-23 2000-03-30 Siemens Ag Verfahren zum Konfigurieren eines konfigurierbaren Hardware-Blocks
US6553414B1 (en) * 1998-10-02 2003-04-22 Canon Kabushiki Kaisha System used in plural information processing devices for commonly using peripheral device in network
KR100731371B1 (ko) * 1999-02-15 2007-06-21 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 구성가능 기능 유닛을 포함하는 프로세서를 사용해서 컴퓨터 프로그램을 실행하는 방법, 프로세서 및 컴퓨터 판독가능 기록 매체
EP1050810A1 (en) * 1999-05-03 2000-11-08 STMicroelectronics SA A computer system comprising multiple functional units
GB2352066B (en) * 1999-07-14 2003-11-05 Element 14 Ltd An instruction set for a computer
US6526430B1 (en) * 1999-10-04 2003-02-25 Texas Instruments Incorporated Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing)
US7039790B1 (en) * 1999-11-15 2006-05-02 Texas Instruments Incorporated Very long instruction word microprocessor with execution packet spanning two or more fetch packets with pre-dispatch instruction selection from two latches according to instruction bit
EP1102163A3 (en) 1999-11-15 2005-06-29 Texas Instruments Incorporated Microprocessor with improved instruction set architecture
US6255849B1 (en) * 2000-02-04 2001-07-03 Xilinx, Inc. On-chip self-modification for PLDs
TW516320B (en) 2000-02-22 2003-01-01 Intervideo Inc Implementation of quantization for SIMD architecture
JP2001306321A (ja) 2000-04-19 2001-11-02 Matsushita Electric Ind Co Ltd プロセッサ
US7120781B1 (en) * 2000-06-30 2006-10-10 Intel Corporation General purpose register file architecture for aligned simd
WO2002033504A2 (en) * 2000-10-02 2002-04-25 Altera Corporation Programmable logic integrated circuit devices including dedicated processor components
US20020174266A1 (en) * 2001-05-18 2002-11-21 Krishna Palem Parameterized application programming interface for reconfigurable computing systems
JP2003005958A (ja) 2001-06-25 2003-01-10 Pacific Design Kk データ処理装置およびその制御方法
JP2003099397A (ja) 2001-09-21 2003-04-04 Pacific Design Kk データ処理システム
US6798239B2 (en) * 2001-09-28 2004-09-28 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
JP3785343B2 (ja) 2001-10-02 2006-06-14 日本電信電話株式会社 クライアントサーバシステム及びクライアントサーバシステムにおけるデータ通信方法
JP3779602B2 (ja) * 2001-11-28 2006-05-31 松下電器産業株式会社 Ｓｉｍｄ演算方法およびｓｉｍｄ演算装置
KR100464406B1 (ko) 2002-02-08 2005-01-03 삼성전자주식회사 가변길이 ｖｌｉｗ 명령어를 위한 디스패치 장치 및 방법
JP3857614B2 (ja) * 2002-06-03 2006-12-13 松下電器産業株式会社 プロセッサ
US7159099B2 (en) * 2002-06-28 2007-01-02 Motorola, Inc. Streaming vector processor with reconfigurable interconnection switch
JP3982353B2 (ja) * 2002-07-12 2007-09-26 日本電気株式会社 フォルトトレラントコンピュータ装置、その再同期化方法及び再同期化プログラム
US7024543B2 (en) * 2002-09-13 2006-04-04 Arm Limited Synchronising pipelines in a data processing apparatus
TW569138B (en) 2002-09-19 2004-01-01 Faraday Tech Corp A method for improving instruction selection efficiency in a DSP/RISC compiler
US7464254B2 (en) * 2003-01-09 2008-12-09 Cisco Technology, Inc. Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data
JP2004309570A (ja) 2003-04-02 2004-11-04 Seiko Epson Corp 光通信モジュール、光通信装置、及びその製造方法
US7496776B2 (en) * 2003-08-21 2009-02-24 International Business Machines Corporation Power throttling method and apparatus
US7385931B2 (en) * 2003-08-22 2008-06-10 Fujitsu Limited Detection of network misconfigurations
US7176713B2 (en) * 2004-01-05 2007-02-13 Viciciv Technology Integrated circuits with RAM and ROM fabrication options
US7949856B2 (en) * 2004-03-31 2011-05-24 Icera Inc. Method and apparatus for separate control processing and data path processing in a dual path processor with a shared load/store unit
US9047094B2 (en) * 2004-03-31 2015-06-02 Icera Inc. Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor

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