CN100472433C - 用于在双通道处理器中控制处理的装置和方法 - Google Patents
用于在双通道处理器中控制处理的装置和方法 Download PDFInfo
- Publication number
- CN100472433C CN100472433C CNB2005800106607A CN200580010660A CN100472433C CN 100472433 C CN100472433 C CN 100472433C CN B2005800106607 A CNB2005800106607 A CN B2005800106607A CN 200580010660 A CN200580010660 A CN 200580010660A CN 100472433 C CN100472433 C CN 100472433C
- Authority
- CN
- China
- Prior art keywords
- instruction
- instructions
- computer processor
- control
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
- G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
- Hardware Redundancy (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/813,628 US7949856B2 (en) | 2004-03-31 | 2004-03-31 | Method and apparatus for separate control processing and data path processing in a dual path processor with a shared load/store unit |
| GB10/813,628 | 2004-03-31 | ||
| PCT/GB2005/001059 WO2005096140A2 (en) | 2004-03-31 | 2005-03-22 | Apparatus and method for control processing in dual path processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1950795A CN1950795A (zh) | 2007-04-18 |
| CN100472433C true CN100472433C (zh) | 2009-03-25 |
Family
ID=34962961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005800106607A Expired - Fee Related CN100472433C (zh) | 2004-03-31 | 2005-03-22 | 用于在双通道处理器中控制处理的装置和方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US7949856B2 (enExample) |
| EP (2) | EP1735700B1 (enExample) |
| JP (1) | JP5198847B2 (enExample) |
| KR (1) | KR20070026434A (enExample) |
| CN (1) | CN100472433C (enExample) |
| CA (1) | CA2560465A1 (enExample) |
| TW (2) | TWI413935B (enExample) |
| WO (1) | WO2005096140A2 (enExample) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8484441B2 (en) | 2004-03-31 | 2013-07-09 | Icera Inc. | Apparatus and method for separate asymmetric control processing and data path processing in a configurable dual path processor that supports instructions having different bit widths |
| US7949856B2 (en) * | 2004-03-31 | 2011-05-24 | Icera Inc. | Method and apparatus for separate control processing and data path processing in a dual path processor with a shared load/store unit |
| US9047094B2 (en) | 2004-03-31 | 2015-06-02 | Icera Inc. | Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor |
| CN100456230C (zh) * | 2007-03-19 | 2009-01-28 | 中国人民解放军国防科学技术大学 | 超长指令字与单指令流多数据流融合的计算群单元 |
| US8281111B2 (en) * | 2008-09-23 | 2012-10-02 | Qualcomm Incorporated | System and method to execute a linear feedback-shift instruction |
| US8755515B1 (en) | 2008-09-29 | 2014-06-17 | Wai Wu | Parallel signal processing system and method |
| JP2011028543A (ja) * | 2009-07-27 | 2011-02-10 | Renesas Electronics Corp | 情報処理システム及びその情報処理方法 |
| US8842121B2 (en) * | 2011-02-03 | 2014-09-23 | Intel Corporation | Stream compaction for rasterization |
| CN102945150B (zh) * | 2012-09-18 | 2015-11-18 | 苏州华周胶带有限公司 | 一种实现多功能用户界面的方法 |
| KR20140126189A (ko) * | 2013-04-22 | 2014-10-30 | 삼성전자주식회사 | 프로세서의 멀티 실행 모드 지원 장치 및 방법 |
| US9772849B2 (en) | 2014-11-14 | 2017-09-26 | Intel Corporation | Four-dimensional morton coordinate conversion processors, methods, systems, and instructions |
| US9772848B2 (en) | 2014-11-14 | 2017-09-26 | Intel Corporation | Three-dimensional morton coordinate conversion processors, methods, systems, and instructions |
| US9772850B2 (en) | 2014-11-14 | 2017-09-26 | Intel Corporation | Morton coordinate adjustment processors, methods, systems, and instructions |
| EP3257162B1 (en) | 2015-02-12 | 2023-08-09 | Huawei Technologies Co., Ltd. | System and method for auto-detection of wlan packets using header |
| US10402199B2 (en) | 2015-10-22 | 2019-09-03 | Texas Instruments Incorporated | Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor |
| CN105912307B (zh) * | 2016-04-27 | 2018-09-07 | 浪潮(北京)电子信息产业有限公司 | 一种Flash控制器数据处理方法及装置 |
| CN111242293B (zh) * | 2020-01-13 | 2023-07-18 | 腾讯科技(深圳)有限公司 | 一种处理部件、数据处理的方法以及电子设备 |
| CN116917876A (zh) * | 2021-05-29 | 2023-10-20 | 华为技术有限公司 | 一种数据处理方法及装置 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1072788A (zh) * | 1991-11-27 | 1993-06-02 | 国际商业机器公司 | 动态多方式并行处理器阵列体系结构的计算机系统 |
| US5600810A (en) * | 1994-12-09 | 1997-02-04 | Mitsubishi Electric Information Technology Center America, Inc. | Scaleable very long instruction word processor with parallelism matching |
| CN1467622A (zh) * | 2002-06-03 | 2004-01-14 | ���µ�����ҵ��ʽ���� | 处理器 |
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| DE69031257T2 (de) | 1989-09-21 | 1998-02-12 | Texas Instruments Inc | Integrierte Schaltung mit einem eingebetteten digitalen Signalprozessor |
| JPH05324430A (ja) | 1992-05-26 | 1993-12-07 | Toshiba Corp | データ処理装置 |
| US5423051A (en) * | 1992-09-24 | 1995-06-06 | International Business Machines Corporation | Execution unit with an integrated vector operation capability |
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| US9047094B2 (en) * | 2004-03-31 | 2015-06-02 | Icera Inc. | Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor |
-
2004
- 2004-03-31 US US10/813,628 patent/US7949856B2/en not_active Expired - Lifetime
-
2005
- 2005-03-22 EP EP05729441.5A patent/EP1735700B1/en not_active Expired - Lifetime
- 2005-03-22 CA CA002560465A patent/CA2560465A1/en not_active Abandoned
- 2005-03-22 CN CNB2005800106607A patent/CN100472433C/zh not_active Expired - Fee Related
- 2005-03-22 JP JP2007505612A patent/JP5198847B2/ja not_active Expired - Lifetime
- 2005-03-22 EP EP10177669.8A patent/EP2290526B1/en not_active Expired - Lifetime
- 2005-03-22 KR KR1020067020244A patent/KR20070026434A/ko not_active Ceased
- 2005-03-22 WO PCT/GB2005/001059 patent/WO2005096140A2/en not_active Ceased
- 2005-03-24 TW TW094109124A patent/TWI413935B/zh not_active IP Right Cessation
- 2005-03-24 TW TW099133459A patent/TWI450192B/zh not_active IP Right Cessation
-
2010
- 2010-12-09 US US12/964,525 patent/US8484442B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1072788A (zh) * | 1991-11-27 | 1993-06-02 | 国际商业机器公司 | 动态多方式并行处理器阵列体系结构的计算机系统 |
| US5600810A (en) * | 1994-12-09 | 1997-02-04 | Mitsubishi Electric Information Technology Center America, Inc. | Scaleable very long instruction word processor with parallelism matching |
| CN1467622A (zh) * | 2002-06-03 | 2004-01-14 | ���µ�����ҵ��ʽ���� | 处理器 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1735700A2 (en) | 2006-12-27 |
| TWI413935B (zh) | 2013-11-01 |
| CA2560465A1 (en) | 2005-10-13 |
| US20110078416A1 (en) | 2011-03-31 |
| EP2290526A1 (en) | 2011-03-02 |
| TWI450192B (zh) | 2014-08-21 |
| US7949856B2 (en) | 2011-05-24 |
| TW201106265A (en) | 2011-02-16 |
| CN1950795A (zh) | 2007-04-18 |
| WO2005096140A3 (en) | 2006-07-06 |
| JP5198847B2 (ja) | 2013-05-15 |
| TW200540707A (en) | 2005-12-16 |
| EP1735700B1 (en) | 2018-09-12 |
| KR20070026434A (ko) | 2007-03-08 |
| JP2007531133A (ja) | 2007-11-01 |
| WO2005096140A2 (en) | 2005-10-13 |
| US8484442B2 (en) | 2013-07-09 |
| US20050223193A1 (en) | 2005-10-06 |
| EP2290526B1 (en) | 2018-05-30 |
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Legal Events
| Date | Code | Title | Description |
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| C06 | Publication | ||
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| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: HUIDA TECHNOLOGY ENGLAND CO., LTD. Free format text: FORMER OWNER: ICERA INC. Effective date: 20130121 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20130121 Address after: London, England Patentee after: ICERA Inc. Address before: Bristol Patentee before: Icera Inc. Effective date of registration: 20130121 Address after: Bristol Patentee after: Icera Inc. Address before: Bristol Patentee before: Icera Inc. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090325 |
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| CF01 | Termination of patent right due to non-payment of annual fee |