TW569138B - A method for improving instruction selection efficiency in a DSP/RISC compiler - Google Patents

Abstract

A method for improving instruction selection efficiency in a DSP/RISC compiler. Concurrently obtaining optimal performance and space, the method includes the following steps: determining a semantic tree for a basic block; finding all matching combinations for the semantic tree with reference to a set of patterns; determining cycle number and instruction length for all combinations; filtering the instruction length greater than a predetermined instruction length and extra ones having the same cycle number and instruction length according to the determined cycle number and instruction length; and choosing one combination with the smallest cycle number from the remaining combinations and outputting the one combination as the desired object code.

Description

569138 V. Description of the invention (1) Field of the invention The present invention relates to a method for improving the performance of instruction selection of a digital signal processor / reduced DSP / RISC compiler in order to obtain optimization at the same time. Performance and space usage. Related technical notes

Figure 1 shows the structure of a typical compiler. In Fig. 1, the structure includes a human-readable source code 11, a compiler 2 and a target purpose code 13. The compiler 12 includes a front end 2000, an optimizer 202, a syntax processor 204, a pattern table generator 206, and a code generator 208. As shown in Figure 1, the front end 200 receives the human-readable source code 11, for example, using C, C ++, VB, or PASCAL high-level languages (these can be stored in internal memory or external hardware) Source code) and perform a symbol analysis. The optimizer 202 translates the source code 11 into an optimized intermediate representation (IR). The syntax processor 204 performs a syntax analysis and its execution result is input into a pattern table generator to generate a set of pattern matching tables (PMTs). According to the above-mentioned intermediate expressions (IR) and pattern matching tables (PMTs), the matching of the semantic tree pattern is performed 'so that the code generator 208 outputs a destination code 13. Those familiar with this

Those skilled in the art should understand that the object code 13 may include an assembly code or a binary code as desired. ， 口 叩 The above intermediate expression (IR) contains some basic blocks. A basic block is a series of intermediate instructions with a single entry at the top and a single exit at the bottom. Each basic block can represent one or more

569138 V. Description of the invention (2) Independent data dependent figures, each figure contains one or t d es). Each node is roughly represented in the target machine (not shown) by order 'to enable the target machine to perform-the work related to the instruction: and in the material dependency graph τ the operation of a node will follow the water = or U 1 A variable (in which the former-node is so called because it is executed before the γ-Ichiro point). However, the operation of the Erlang point does not depend on the generated data and / or its next-node (unless it exists in a circle so that the next node will execute before the previous node). Traditionally, the unique information of the machine (such as the characteristics of the instruction, the delay of the finger A, the number and type of registers used by the instruction, etc.) is embedded in the translator. Therefore, the optimizer 20 in the compiler 12 is a randomizer type. The optimizer 202, which depends on the type of randomizer, continuously performs the work of instruction selection, register allocation, and instruction reorganization and parallelization. An example is given below to illustrate the differences between the conventional techniques in the instruction selection of a semantic tree. η ^ Figure 2 is an example of a basic block and a graph of a semantic tree operated by the compiler of Figure 1. As shown in Figure 2, this example shows a basic block with an independent data dependency graph, which contains an expression pRO = abs (pRl-pR2) + (pR3-pR4) and its semantic tree. Among them, pRO-4 is a temporary register. To complete this semantic tree, the code generator 208 performs the tree pattern matching operation. This tree pattern matching is a bottom-up instruction selection operation performed before the register allocation operation. As shown in Figure 3, the node register pR5 and pR7 first select one from the pattern table generator respectively.

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569138 V. Description of the invention (3) The matching pattern is provided. Then, the node register pR6 and pR8 are formed in the same way as the previous node register. Finally, the semantic tree is completed when the node register pR0 is formed and output by the code generator 208. However, a conventional compiler such as Fig. 2 has the problem that it cannot provide optimized space usage and optimized execution performance at the same time. In these cases, the optimization of space usage is often sacrificed. For example, in the optimizer 202, there are two schemes to form a node PR6 or PR8. The first scheme is shown in Figure 4a. It uses a conditional instruction and a jump instruction that requires 6 clocks for execution. This first solution produces a result of 2 instruction sizes (space usage) and an average of 4 clocks (execution performance). The second scheme is shown in Figure 4b, using mutually exclusive, 32-time signed shifts and subtraction operations. This second scheme produces a result of 3 instruction sizes and an average of 3 clocks. Therefore, when using the former to generate optimized space usage, it requires 11 clocks and 7 instructions as shown in Figure 5a. And when Ϊ. When using the latter to generate optimal execution performance, it requires the clocks and 9 instructions as shown in the figure below. As mentioned above, you can see the efficiency and space usage ::: Valley. As shown in Figure 6, it exhibits a negative linear relationship (a = straight line) and has a better second quality at the lower left (at point 3) and a poorer lower right (at point b). Quality. For example = when-the user needs -12K space 'Because the processor is growing by 2n, it should be used "a Japanese plug four ICT, Tian Ren π Therefore, the user must purchase a 16K A digital signal processor of a large size, where η is an integer. This method will waste 1/4 of the above 16K capacity. The pq day s κ 左 # JA / 4

569138 V. Description of the invention (4) "-^ It is used for the widely used multimedia, especially in the development of a digital processor / reduced instruction set computing system for image processing, which is becoming more and more serious. SUMMARY OF THE INVENTION Accordingly, one of the objects of the present invention is to provide a method for improving the instruction selection performance of a digital signal processor / reduced instruction set arithmetic compiler, so as to obtain optimized execution performance and space usage at the same time. The present invention provides a method for improving the instruction selection performance of a digital signal processor / reduced instruction and arithmetic compiler (DSP / RISC compiler), which determines an optimum within a limited use space selected by a user. The code size is optimized to generate optimized execution performance and space usage at the same time. In this method, 3 the following steps: determine a semantic tree of a basic biock; find all matches by referring to a set of patterns = a combination of the above semantic trees (aU matching c〇 [nbinati〇 ns); determine the number of cycles (cycle number) and instruction length (instruction length) of each combination; according to a predetermined number of clocks and instruction length, filter the number of clocks that exceed the predetermined number of clocks and have 3: Temple = the excess of the number and the instruction length; and from the remainder after filtering, and ', and a, select a group with the least number of clocks as the output, as the desired destination code (〇bject c〇 (je). Detailed description of the preferred embodiment. The same functional elements are represented by the same reference numerals throughout the text. Figure 7 is a diagram of a digital processor / reduced instruction set operation compilation according to the present invention. (DSP / RISC compiler) w ^^

569138 V. Description of the invention (5) Flow chart of the method for selecting the effectiveness. In Figure 7, the method includes steps: determining a semantic tree (S1) of a basic block (S1); and finding all combinations that match the above semantic tree by referring to a set of patterns ( al 1 matching combinations) (S2); determine the number of cycles (cycle nuniber ·) and instruction length (instructioon length) (s3) of each combination; root, fixed number of clocks and instruction length, filtering, the above clocks Among the numbers, the number of clocks exceeding the preliminaries is the same as having the same number of clocks and the excess of the command length (S4 ^ and a combination of > and the number of clocks is selected from the remaining combinations after the filtering above). For the output, it is used as the expected destination code (0 is called "seven"). As shown in Figure 7, when comparing the present invention with the conventional command selection: Temple 'the latter does not look for all possible combinations to determine the best space. ^ Complete the semantic tree of its basic block. For the same example (si) above; the root of the invention 'its instruction selection logic is based on the same example shown in Figure 2. ^ Tu Chongzhong, A group of patterns is selected. As shown in FIG. 8, the group of patterns 81 is temporarily stored in the Lang point. There are 4 kinds of patterns in the device _ (P ^ l), abs (Prl), pRl + pR2, and state—⑽. Symbols such as (fbsl), 4 '2 represents the number of clocks and 2 instructions. An absolute value operation sj Similarly, the symbol (abs2), 4, 2 means 4 clocks and 2 instructions f & pair value operation-2. X-addition or subtraction requires 1 :: number and 1 instruction. The example shown in the known example is to use only the first or first absolute value operation to complete the semantic tree. However, according to the present invention, the semantic tree can be configured to have four combinations 91 as shown in FIG. 9, respectively With

569138

V. Description of the invention (6) There are 11 clocks and 7 instructions; 9 clocks and 9 instructions; order; and 10 clocks and 8 instructions (S3). Because the last two digits and 8 refer to the number of clocks and instructions, a group is discarded, as described below and the predetermined instruction length limit of γ with the same 8 instruction space is described below. Together. The second combination deletion is under consideration (S4). In the remaining combination, the second and upper Λ have 9 orders.

This combination of abs2 has a number of 10 clocks, and its number of clocks: another combination of the number of: = J, so it outputs an objective code with an absl & abs2 proud of it (S5). The logic rule used to perform the above steps is as follows: comp_C (v) Ον = Φ for all peP, if p can match v then i / = v + rl (p); tf2 = v-fi: 2 (p); 'for all Cn, ± eCn and all C / 2rjeC / 2 if s ize (C / ifi) + s ize (c / 2, j) + s ize (p) then

Cv = insert (Cv, (p, s ize (C ~ i) + size (C / Zr j) + s ize (p), cycle (C / i, i) + cycle (C / 2, j) + cycle (p) Ά i2)); return Cv As mentioned above, the subroutine name of this program is comp_C (v). Cv is a candidate group for each node v, which is initially set to an empty set (Φ). P is one

0697-8165TWF (n); P2002-018; sue.ptd 569138 V. Description of the invention (7) ----- Group preset pattern. p is-the selected pattern. It is the memory space defined by the i-th element in the group G from the pattern root to the leftmost node and ~ A from the pattern root to the right-most node in the group Cv. Set (: νΛ = (pattern name (p), clock number (cycle), instruction length (s 1 ze), left operation node (beat), right operation node (deduction)), where C ^ i represents the cost The length of η and the number of m clocks are combined with the left node and the right node to complete the pattern on the semantic tree to complete the i-th element in the set of d =. The way to obtain the group Cv can be more than just a pattern. Therefore, When a vector at a node has a length that falls within the limited memory space (that is, the total instruction length is within sizj (cw HSiZe (c ^ Hsize (p) W)), the vector will be inserted into In the candidate group cv, the above logic (program subroutine) is executed recursively until the unique root r operation is completed. For example, as shown in Figure 10, a node with nodes u, V, χ, y, and … The semantic tree has the following possible instruction selection groups: Cu = {(-, 1,1, a, b) 丨,,

Cv = {(-, l, l, c, d)}, Cx = {(absl, 5,3, u, Φ), (abs2,4,4, u, Φ)}, Cy = {(absl, 5,3, v, φ), (abs2,4,4, v, 0)} & Cw = {(+, li, 7, x, y), (+, 1Q, 8, x, y), (+, 9, 9, x, y)}. With the above optimized instruction selection, as shown in Fig. 1 'compare all candidates in the root group Cw, at a region boundary (as shown by the dotted line' is not a straight line boundary as in the conventional technology) Under the constraints, Cu = {(-, 1,1, a, b)} and Cv = {(—,!,; [, C, d)}

569138 V. Description of the invention (8) »

A path of Cx = {(absl, 5,3, u, φ)} and Cy = {(abs2 C: -two (+, 1〇, 8, χ 'y)} is input': Φ)} to the root (The same structure as shown in Figure 1). From this point of view, the purpose of the Haiba translator is small, and it can achieve higher execution efficiency than the conventional technology. The same memory is large. Although the present invention has a better practice # This invention, anyone who is familiar with this technology: If =, but it is not the scope of the attached application /, _, so the invention # 1 Ming patent The ones defined by the rail fence shall prevail. Bao 5 Chu 0697-8165TWF (n); P2002-018; sue.ptd Page 12 138 Schematic illustrations to illustrate the simple description of the illustrations, to make the above and other objects, features and characteristics of the present invention easy to see. ", Here is a more detailed explanation such as; a more general example, and in conjunction with the attached drawings, detailed Figure 1 is the structure of a typical compiler; Figure 2 is an example of a basic block and its semantic tree; The point Λ 3Λ is the basic block example graph of all r on the semantic tree of Fig. 2 decomposed by the compiler; J all the meaning trees ϊ 4 / ® are—with the first kind of instruction chosen by the compiler. Part of the pattern of my tree; The selected image is a partial pattern with the second instruction selected by the compiler. The selected image of Figure 5a is Figure 4 of the first tree; Figure 2b is the semantics completed by the selection of Figure 4b. Figure 5b is the figure of the tree of Figure 4b. Number vs. space graph; Logic 5 | / Shovel: 8 2 = Inventor of the invention to improve on the-digital signal Flow chart of the method of selecting performance for / reduced instruction set operation compiler (·, command line, outside—Shia, SP / RISC compiler); Figure 8 is a group pattern according to the present invention Example;; An example of the basic block in Figure 2 Figure 9 is a graph of the second sense tree according to the present invention; 罘 A private 7 selection completed 浯

569138 Brief Description of Drawings Figure 10 is an example of the result after implementing the above selection logic of the present invention; and Figure 11 is a graph of the number of clocks versus space according to the present invention. [Notation] 1 1: Human-readable source code 12: Compiler 13: Object code 2 0 0: Front end 202: Optimizer 2 0 4 · · Syntax processor 206: Pattern table generator 2 0 8 : Code Generator

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Claims (1)

569138 VI. Scope of patent application 1 · A method for improving the instruction selection performance of a digital signal processor / reduced instruction set arithmetic compiler (DSP / RISC compiler), including the following steps: Determine a basic block A semantic tree; finding all matching combinations that match the semantic tree by referring to a set of patterns; determining the CyCle number and instruction length of each combination; according to a A predetermined number of clocks and instruction length, filtering out the above-mentioned number of clocks that exceeds the predetermined number of clocks and those having the same number of clocks and instruction length; A set of combinations with the least number of clocks is used as the output, as the desired object code (〇bject code) ° 2 * As the patent application scope item 丨 to improve the digital signal processor / reduced instruction set operation compiler (DSP / RISC ompiler) instruction selection method, where the basic block represents one or more independent dependent graphics, each It comprises one or more nodes. / 3. If the method of patent application No. 2 is used to improve the instruction performance of the digital signal reduced instruction set arithmetic compiler (DSP / RISC commpUer), wherein each node represents an instruction. 7, 4 · Instructions for improving digital signals such as the reduced application instruction set (DSP / RISC coinpiler) according to item 丨 of the scope of patent application 0697-8165TWF (n); P2002-018; sue.ptd p. 15 569138 6. A method of applying patent scope and effectiveness, wherein each of the patterns includes an entrance node on the top and a node connected to the entrance node. 5 · Method 1 for improving the instruction selection performance of a digital signal processor / reduced instruction set arithmetic compiler (DSp / RISC compiler) as described in the first item of the patent scope, wherein each of the patterns includes one on the top An ingress node and a plurality of nodes connected to the ingress node. 6 · The method of improving the instruction selection performance of the digital signal processor / reduced instruction set arithmetic compiler (DSP / RISC compi ier) according to item 1 of the scope of patent application, wherein the set of patterns is machine-dependent. 7 · The method for improving the instruction selection performance of the digital signal processor / reduced instruction set arithmetic compiler (DSP / RISC compi ler) according to item 1 of the scope of patent application, wherein the instruction length is machine-dependent. For example, if the method for selecting a digital signal processor / reduced-core set-computing compiler (DSP / risc compiler) is selected as the first method in the scope of patent application, the predetermined instruction length is determined by the The capacity of the digital signal processor / reduced instruction set operation compiler is determined. # 9 · As stated in item # 1 of the patent scope, to improve the digital signal processor / f = instruction set arithmetic compiler (DSP / RISC compiler) instruction selection method b month, where 'the expected destination code is one Combined language code. / Bamboo 4: The first item in the scope of the digital signal processor is used to improve the efficiency of the digital signal processor, the instruction selection effect of the DSP / RISC compiler, and the method, wherein the expected destination code is Is a binary code. / 浐 t m The scope of the first item is to improve the digital signal processor, the month θ said v set arithmetic compiler (DSP / RISc cmpiier) instruction selection 〇697.8165TW (n); P2〇2.〇i8; sue > ptd page 16 569138 6. Method of applying patent scope 1 effectiveness, wherein the semantic tree matching is performed from the bottom to the completion of the substrate block configuration Up to a single root. 1 2 · The method for improving the instruction selection performance of a digital signal processor / reduced set computing compiler (DSP / risC compiler) according to item 1 of the scope of patent application, which further includes using an optimizer To configure this method. 1 3 · To improve digital signal processing as described in item 11 of the patent application To output the desired destination code. -Instruction selection of DSP / RISC compiler-The steps include using a code generator to execute the method Page 17