JP3464019B2 - Register allocation method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compiler which outputs an execution program from a source program, and more particularly to a technique which is effective when applied to a compilation method using virtual registers.

[0002]

2. Description of the Related Art A compiler that translates (compiles) a source program described in language specifications such as C language, FORTRAN, and COBOL to generate a target program is "syntactic analysis", "code optimization", "optimization". A series of processing such as "processing" and "code output" is performed.

In a conventional compiler, the work area reserved by the compiler during processing is reserved in the main memory of the computer on which the compiler is actually operating, or in a register when the work area is short. When an area longer than the register length is required, it is generally secured in the main memory.

Recently, there is known a method in which a compiler also generates a virtual register (hereinafter, simply referred to as "virtual register") during the processing and allocates a work area to this virtual register. The following are prior arts that introduce the concept of this virtual register.

Japanese Patent Laid-Open No. 3-73026 discloses a technique for setting an infinite number of virtual registers at the time of compilation to reduce data transfer with the main memory. Further, as a technique for allocating to a real register when executing an object program including an instruction sequence using virtual registers, Japanese Patent Laid-Open No. 2-1.
There is 94439 issue. Further, as a technique for improving efficiency by using a profit index when allocating a virtual register to a real memory, there is JP-A-2-236638.

[0006]

As is apparent from the above-mentioned prior art, by introducing the concept of a virtual register into the compilation process, the register allocation process is performed by assigning the virtual register to the source program and the virtual register. Is allocated to the real register to improve the processing efficiency at the time of compilation and the execution efficiency of the target program.

However, in the above-mentioned prior arts, it is premised that the length of the virtual register is set to be the same as the length of the real register. That is, since the variable value stored in the virtual register is stored in the real register as it is when the object program is executed, the virtual register length needs to match the real register length.

Therefore, in the COBOL language or the like which requires a work area longer than the virtual register length, it is difficult to allocate to the virtual register, so that the work area must be secured in the main memory at the time of compilation.

As is well known, a data transfer instruction to and from a main memory requires a longer time for both reference and update than that for a register, so that the execution efficiency of the program cannot help but be lowered.

The present invention has been made in view of such a point, and the virtual register can be applied even in a language system requiring a work area larger than the register length to significantly improve the processing efficiency during program execution. It is to provide the technology to improve.

[0011]

According to the present invention, as shown in FIG. 1 which is a principle diagram, the parsing means 1 acquires syntax tree information, generates work variables based on the syntax tree information, and then allocates virtual registers. In the means 2, if the work variable is smaller than the single real register, one virtual register having the same length as the real register is set, and if the variable is larger than the single real register, it is the same as the real register. A virtual register list is set by combining a plurality of virtual registers having lengths. Then, in the virtual register arithmetic expansion means 3, when the variables stored in the virtual register are arithmetically operated,
Convert to an operation with the same data length as the actual register.

[0012]

According to the present invention, when the variable is allocated to the virtual register in the virtual register allocating means 2, the length of the variable to be allocated is compared with the length of the real register. Here, it is assumed that each virtual register has the same length as the actual register length. Then, when the variable to be allocated is larger than the data length of one real register, a virtual register list combining a plurality of virtual registers is set. As a result, allocation of data longer than the length of one real register to the virtual register is realized.

In the case of expanding an operation for a virtual register to which a variable is assigned, a plurality of registers (virtual register list) are taken into consideration in consideration of connection between individual virtual registers (virtual register including upper byte, etc.).
The arithmetic processing for (for example, addition of variables between two registers) may be expanded to the arithmetic operation for each register.

According to the present invention, there are no restrictions on register usage as in the case of expressing a floating point operation by a plurality of registers. Therefore, the use of registers can be completely controlled by software. Further, since the configuration of the register used is not changed like the vector operation, complicated preprocessing in hardware or software is unnecessary.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a flow chart showing the overall flow of a compiling process which is an embodiment of the present invention.

As shown in the figure, the compilation process is performed in the order of syntax analysis → area allocation → virtual register allocation → virtual register arithmetic expansion → optimization → real register allocation. In the "parsing" step, first, C language, FORTRAN, C
A syntax of a source program written in a high-level programming language such as OBOL and its meaning are analyzed, and a syntax tree is generated based on the analysis. The following processing will be performed based on the syntax tree generated here.

In the "area allocation" step, the variable explicitly described by the user and the variable used by the compiler for work are allocated to the memory. In the "virtual register allocation" step, one or more virtual registers are mainly allocated to the work variables generated by the compiler. Here, one of two virtual register allocation methods is selected in consideration of how the variables are used. FIG. 3 shows this determination flow.

In the figure, first, the length of the variable to be stored in the register is compared with the unit register length (the byte length forming the actual register) (step 301), and the variable length is smaller than the unit register length, or If they are equal, one virtual register is set and the variable is stored (step 302). On the other hand, if the variable length to be stored is larger than the unit register, the number (n) of unit registers required to store this variable is determined (30
3), n virtual registers are set (304). For example, if the unit register length is 4 bytes and the variable to be stored is 10 bytes, 3 virtual registers will be allocated. At this time, when the variable is a numerical value, the data is stored in the LSB → MSB direction as shown in FIG. On the other hand, when the variable is a character string other than a numerical value, the data is stored in the MSB → LSB direction. Thus, when the variable is a numerical value, LSB → MSB
The reason why the data is stored in the direction is to handle the carry process in the calculation. Details of this carry will be described in the next virtual register arithmetic expansion step.

In the "virtual register arithmetic expansion" step,
In consideration of the connection between virtual registers (such as the virtual register including the upper byte of the stored variable), the calculation processing for multiple virtual registers (addition of variables between two registers, etc.) is performed for calculation between unit registers. expand.

A specific example of this arithmetic expansion is shown below. The following is a virtual register list (a set of virtual registers composed of multiple register blocks) PRGL1 and PRG.
This is a specific example in which L2 and L2 are added and the result is stored in PRGL3. Here, the virtual register list PR
LG1 to PRLG3 are configured as shown in FIG. That is, the virtual register lists PRLG1 to PRL
Each G3 is composed of 12 bytes, and each of these virtual register lists is composed of three 4-byte virtual registers (PRG) that are unit register lengths (real register lengths). Note that the following list is a conceptual description and differs from the actual assembler description.

[0021]

[Equation 1] 10: MOVE [PRGL1 containing the least significant byte
(PRG (1-3))], PRG-a 20: MOVE [Block containing the least significant byte of PRGL2 (PRG (2-
3))], PRG-b 30: ADD PRG-a, PRG-b, PRG-C 40: IF Carry PRG-d, 1 50: STORE PRG-c, [PRGL3 least significant (PRG (3-3 )] 60: MOVE [PRGL1 next block (PRG (1-2))], PRG-a 70: MOVE [PRGL2 next block (PRG (2-2))], PRG-b 80: ADD PRG -a, PRG-b, PRG-c 90: IF Carry 100: ADD PRG-c, PRG-d, PRG-c 110: STORE PRG-c, [Next block of PRGL3 (PRG (3-2)] 120: JUMP 60 In the assembler program shown in the above equation 1, in the tenth line, the stored values are sequentially registered from the lowest block (PRG (1-3)) of the virtual register PRGL1 to the register PR.
It is taken out to G-a. In the 11th line, the lowest block (PRG) of the virtual register PRGL2 is similarly processed.
The stored value is taken out to the register PRG-b in order from (2-3)).

On line 30, PRG-a and PRG-b
Stored values are added and the result is stored in PRG-c. If a carry occurs, 1 is stored in PRG-d set as the operation work register (40th line). Then, the stored value of PRG-c is stored in the lowest block (PRG (3-3)) of the virtual register list PRLG3.

As described above, the virtual register PRLG3
After the calculation of the lowest block of the above is completed, the calculation of the middle block is performed as shown in the following 60th line to 110th line and FIG.

On the 60th line, the value of the next PRG in the virtual register PRGL1 read on the 10th line, that is, the value of the block immediately above the block read on the 10th line (PRG (1-2)). Is stored in PRG-a. Similarly, in the 70th line, the virtual register PRGL2
The next block of PRG (2-2)
Store in Gb. Then, PRG-a and PRG-b are added and the result is stored in PRG-c. At this time, if a carry has occurred on the 40th line, P
The value "1" of PRG-d is added to RG-c and the result is substituted into PRG-c. The value of this PRG-c is stored in the middle block (PRG (3-2)) of the virtual register PRLG3. If a carry occurs further at this time, "1" is added to the operation work register PRG-d.

Next, the uppermost blocks (PRG (1-1), PRG (2-1)) of PRLG1 and PRLG2 are subjected to arithmetic processing, and the result is calculated as the block of PRLG3 (PRG).
(3-1)), but this process starts from the 60th line.
Since it is the same as the processing in the 110th line (processing shown in FIG. 6), description thereof will be omitted.

As described above, according to the present embodiment, the operation of the virtual register list which is longer than the actual register is decomposed into the operation processing of each unit register length (4 bytes in the above example), thereby The processing can be performed without considering the length of the register.

The "optimization process" is performed on the intermediate language having the virtual register described above as an argument. After this, "real register allocation" is performed. Allocation to the actual registers can be suppressed by using the coloring method of the prior art, etc., and only the minimum part of the work area needs to be allocated to the main memory. Is possible.

[0028]

According to the present invention, a recent computer has a large number of registers (real registers), so that a work area longer than the length of the registers (real registers) is allocated to a plurality of registers (virtual registers). By distributing and securing,
It is possible to shorten the reference time to the work area and the update time, and to shorten the program execution time.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a flowchart showing a compiling process which is an embodiment of the present invention.

FIG. 3 is a flowchart showing a process of register allocating means 2 in the embodiment.

FIG. 4 is a schematic diagram showing a method of storing variables in registers in the embodiment.

FIG. 5 is an explanatory diagram showing an operation between virtual register lists in the embodiment.

FIG. 6 is an explanatory diagram showing an operation between virtual register lists in the embodiment.

[Explanation of symbols]

1 ... Analysis means 2..Virtual register allocation means 3 ... Computing means 4..Judgment means

Claims (3)

(57) [Claims] 1. An analyzing unit for analyzing a source program written in a programming language, and a work variable generated based on syntax tree information obtained by the analyzing unit, the variable being a single real register. If the variable is larger than a single real register, one virtual register with the same length as the real register is set. If the variable is larger than a single real register, it is configured by combining multiple virtual registers with the same length. Virtual register allocating means for setting a virtual register list, and virtual register arithmetic expansion means for converting the variables stored in the virtual registers into arithmetic operations with the same data length as the actual registers. The virtual register arithmetic expansion means is a virtual register list.
Register with the same length as the virtual register that composes
And a carry operation register that indicates a carry.
Has a virtual register when performing operations on the virtual register list.
Carry occurred in operation of lower block of starist
In this case, add "1" to the work register for calculation.
If you want to perform arithmetic processing of the upper block than
"1" stored in the work register is calculated in the upper block
Register allocation method characterized by expanding so as to add to the result . 2. The virtual register allocating means is provided with a judging means for judging whether or not a work area to be secured in the compilation requires an area larger than the size of the real register, and the judging means secures the area. Set a single virtual register if the work area to be used does not require an area larger than the size of the real register, and set a virtual register list consisting of multiple virtual registers if it needs a large area. The register allocating method according to claim 1, wherein: 3. The virtual register allocating means stores a numerical value from the least significant bit to the most significant bit when the variable is numerical data when the variable is stored in the virtual register or virtual register list. The register allocating method according to claim 1, wherein the register allocating method is a register allocating method.