JPH11345127A - Compiler - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compiler capable of generating a machine word program in a small instruction code size. SOLUTION: A first instruction stream length calculating means 32 calculates an instruction stream length, when each variable in a source program is allocated to a first register source, while using an instruction described in a first instruction format. A second instruction stream length calculating means 33 calculates an instruction stream length, when each variable in the source program is allocated to a second register source different from the first register source, while using an instruction described in a second instruction format having an instruction length different from that of the first instruction format. Resource allocation is performed, corresponding to the calculated results.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a compiler for translating a source program written in a high-level programming language into a machine language program.

[0002]

2. Description of the Related Art In recent years, it has been actively practiced to write programs in a high-level programming language such as C language to improve the development efficiency of the programs. By using a high-level programming language, the programmer can arbitrarily define the processing such as holding, calculating, and transferring numerical values in a program by calculating (steps) using variables, and use only the required number. Programmers can write programs freely. The described program (hereinafter, referred to as a source program) is a machine language program that can be understood by a computer by being compiled by a compiler. The operations in this machine language program are expressed by machine language instructions,
Since the machine language instruction uses a register or a memory as an operand, it is necessary to assign a register or a memory to the variable. This allocation processing is called resource allocation processing. If the resource allocation process is optimal, the code size of the machine language program is minimized.

In general, when a register is allocated to each variable, better results are obtained in terms of code size and execution time than when memory is allocated. However, since the number of registers that can be used is small, how to efficiently allocate register resources and use a machine language instruction with a register as an operand is an optimization in the resource allocation process. As a conventional resource allocation optimizing method, based on a section in which the value in which each variable is stored is valid (referred to as a variable live range), it is determined which variable is allocated to the same register. A method is adopted in which inspection is performed and resource allocation is performed using the results.

On the other hand, the inventor of the present application has disclosed in Japanese Patent Application No.
80, proposes a data processing device using the following two instruction formats and register models. FIGS. 10 to 20 show an outline of the first instruction format.

The first instruction format is a variable length instruction having a minimum instruction word length of 1 byte, and a 2-bit field is used as a register address designation field. Therefore, four registers can be specified in one register addressing field. In this architecture, four address registers and four data registers are defined. By discriminating whether to use the address register or the data register as the instruction operation, the instruction can use the eight registers in total.

FIG. 10 shows a first instruction format (1) in which the first instruction field of the first byte, which is the minimum instruction word length, is composed of an operation designation field and an arbitrary number of register address designation fields. Shows the bit allocation of.

The first instruction format (1)-(a) includes an instruction format including two fields of a 2-bit register address designation field in the first instruction field and having a minimum instruction word length of 1 byte. , Which is an instruction format in which two operands can be specified.

[0008] The first instruction format (1)-(b) includes two 2-bit register addressing fields in the first instruction field, and further adds an additional information field to make a total of 2 bytes or more. This is an instruction format having an instruction word length.

The first instruction format (1)-(c) includes one 2-bit register addressing field in the first instruction field, and is composed of 1 byte which is the minimum instruction word length. , Which is an instruction format in which one operand can be specified.

The first instruction format (1)-(d) includes an instruction word length of 2 bytes or more in which the first instruction field includes one register address designating field of 2 bits and further includes an additional information field. The instruction format has

The first instruction format (1)-(e) is an instruction format which does not include the register address designation field in the first instruction field and is composed of 1 byte which is the minimum instruction word length. This is an instruction format that cannot use operands.

The first instruction format (1)-(f) has an instruction format that does not include a register addressing field in the first instruction field and has an instruction word length of 2 bytes or more in which an additional information field is added. It is.

FIG. 11 shows a part of a specific instruction list for each bit allocation shown in FIG. The mnemonic of the instruction is shown on the left side, and the operation of the instruction is shown on the right side.

FIG. 12 shows that the first instruction field of the first byte, which is the minimum instruction word length, is composed of an instruction word length designation field, and the second instruction field is composed of an operation designation field and an arbitrary number of register address designations. FIG. 9 shows bit assignment of a first instruction format (2) composed of fields.

The first instruction format (2)-(a) is an instruction format including two fields of a 2-bit register address designation field in the second instruction field and composed of two bytes, and has two operands. Is an instruction format that can be specified.

The first instruction format (2)-(b) includes two 2-bit register addressing fields in the second instruction field, and further adds an additional information field to make a total of 3 bytes or more. This is an instruction format having an instruction word length.

The first instruction format (2)-(c) includes one 2-bit register addressing field in the second instruction field, and is an instruction format composed of 2 bytes, and has one operand. Is an instruction format that can be specified.

The first instruction format (2)-(d) includes an instruction word length of 3 bytes or more in which the second instruction field includes one register address designating field of 2 bits and further includes an additional information field. The instruction format has

The first instruction format (2)-(e) is an instruction format composed of two bytes without including the register address designation field in the second instruction field. This is an impossible instruction format.

The first instruction format (2)-(f) does not include the register address designation field in the second instruction field, and further has an instruction word length of 2 bytes or more with an additional information field added. It is.

FIG. 13 shows a part of a specific instruction list for each bit allocation shown in FIG. The mnemonic of the instruction is shown on the left side, and the operation of the instruction is shown on the right side.

Therefore, in the first instruction format shown in FIGS. 10 to 13, the first instruction field has a basic instruction word length, the first to Mth instruction fields have a maximum instruction word length M, and N Instruction word length (N is an integer between 1 and M)
This has an unique feature that the minimum instruction word length is 1 byte, and has an instruction format suitable for reducing the program size.

FIG. 14 shows a first example of the data processing apparatus.
Is shown in FIG. The first register file 220 includes four address registers A0 to A3.
, Four data registers D0 to D3, a stack pointer SP223, a PSW (Processor Status Word) 224 holding internal status information and control information, and a program counter PC225.

FIG. 15 is a diagram showing the access to the address registers A0 to A3 and the data registers D0 to D3 of the first register file 220 in more detail. The figure shows the register name specified in the instruction, the bit assignment in the instruction code specified in the register address specification field, the physical register number for accessing the physical register, and the access target. Is a list of physical register names.

As shown in FIG. 15, in the first instruction format, an instruction addressing field specified in an instruction to access four address registers A0 to A3 and four data registers D0 to D3 are provided. The instruction addressing field specified in the instruction to access D3 is exactly the same. That is, a 2-bit instruction addressing field is used to specify the address of the register, and it is distinguished whether the instruction operation itself accesses the address register or the data register.

Next, FIG. 16 shows the bit assignment of the second instruction format that is additionally extended with respect to the first instruction format of FIGS. 10 and 12 which is the basic instruction format of the present architecture.

In the bit assignment of the second instruction format shown in FIG. 16, the first instruction field of the first byte, which is the minimum instruction word length, comprises an instruction word length designation field, and the second and third instruction fields Consists of an operation specification field and an arbitrary number of register address specification fields. The register addressing field in the second instruction format is composed of 4 bits.

In FIG. 16, the second instruction format (a) is an instruction format that includes two fields of a 4-bit register address designation field in the third instruction field and is composed of 3 bytes. Is an instruction format that can be specified.

The second instruction format (b) includes two 4-bit register addressing fields in the third instruction field, and further adds an additional information field to make the instruction word length more than 4 bytes in total. The instruction format has

The second instruction format (c) is an instruction format including one 4-bit register address specification field in the third instruction field and composed of three bytes, and one operand can be specified. Instruction format.

The second instruction format (d) includes an instruction having a 4-bit register address designating field in the third instruction field, and further having an instruction word length of 4 bytes or more obtained by adding an additional information field. Format.

Therefore, the second instruction format is also:
A variable length instruction having an N instruction word length (N is an integer between 1 and M) is specified, with the first instruction field as the basic instruction word length and the first through Mth instruction fields as the longest instruction word length M. .

FIG. 17 shows a part of a specific instruction list for each bit allocation shown in FIG. The mnemonic of the instruction is shown on the left side, and the operation of the instruction is shown on the right side. In the mnemonic, Rm,
Rn or Ri indicates the designation of a register address. A second register file 120 as shown in FIG. 18 is defined as a register that can be designated, and four address registers A0 to A3 and four data registers D0-D3,
And 16 comprising eight extension registers E0 to E7.
General purpose registers. Further, the second register file 120 includes a stack pointer SP 122 and a PSW (Processor) holding internal status information and control information.
Status Word) 123 and a program counter PC 124.

FIG. 19 shows that when executing an instruction defined in the first instruction format, the register name specified in the instruction, the bit assignment on the instruction code specified in the register address specification field, and the like. , The physical register number to access the physical register, and
This is a list of physical register names to be accessed. In the first instruction format, the register specification field has only two bits, but the address needs to be converted because there are 16 general-purpose registers that need to be accessed with 4-bit addresses. For example, when accessing the address register A0, “1000” is generated as a physical address number, and when accessing the data register D1, “1101” is generated as a physical address number. It is necessary to output to 121.

FIG. 20 is a diagram showing, when an instruction defined in the second instruction format is executed, the register name specified in the instruction, the bit assignment on the instruction code specified in the register address specification field, and the like. , The physical register number to access the physical register, and
This is a list of physical register names to be accessed. In the second instruction format, 4
Since there is a register address specification field of bits, the four bits are directly specified as a physical register number.

[0036]

SUMMARY OF THE INVENTION The present inventor has filed Japanese Patent Application No. Hei.
In a data processing device as proposed in Japanese Patent Application No. 0-59680, if resources are simply allocated with priority given to a register over a memory as performed by a conventional compiler, the following problems exist.

1) When the variables assigned to the first register file (register resources) are processed using the instructions described in the first instruction format, and when the variables assigned to the second register file are Since the instruction length is different between the case where the processing is performed using the instruction described in the second instruction format, the instruction code size does not become the minimum by treating both of them uniformly without prioritizing them.
That is, the conventional compiler does not consider whether each variable is preferentially assigned to the first register file or to the second register file. For example, if each variable is allocated to the second register file in the order of its appearance, and these variables are processed using an instruction described in the second instruction format, the instruction length of the second instruction format is The instruction code size increases as the instruction length becomes longer than the instruction length of the instruction format No. 1.

2) In the case where a variable is processed using an instruction described in the second instruction format, an instruction sequence including a data transfer instruction for transferring data from a memory to a register has a first instruction format. When processing variables using, the instruction length may become shorter even though the number of instructions increases. Therefore, simply allocating variables to register resources rather than memory does not minimize the code size.

An object of the present invention is to provide a compiler that generates a machine language program with a small instruction code size in a processor having an instruction set in which register resources that can be handled differ according to the instruction format and instruction lengths differ according to the instruction format used. To provide.

[0040]

According to the present invention, a frequently used variable is assigned to a register which can be used in a format having a short instruction length.
And obtaining a machine language program in which those variables are processed using the short instruction length format.

That is, the compiler according to the first aspect of the present invention inputs a source program including a plurality of instructions,
A compiler for translating this source program into a machine language program, wherein an instruction sequence in which each variable in the source program is assigned to a first register resource using an instruction described in a first instruction format Using a first instruction sequence length calculating means for calculating the length of each instruction, and using each instruction in the source program as an instruction described in a second instruction format having an instruction length different from the first instruction format. A second register resource different from the first register resource.
Second instruction string length calculating means for calculating the length of the instruction string when the instruction string is allocated to the register resources of the first and second register resources, and using the instruction length calculation results calculated by the first and second instruction length calculating means. Assigning is performed.

According to a second aspect of the present invention, in the compiler according to the first aspect, a third instruction sequence length calculation for calculating an instruction sequence length when each variable in the source program is allocated to a memory. Means for allocating resources using the instruction length calculation results calculated by the first, second, and third instruction length calculation means.

According to a third aspect of the present invention, in the compiler according to the first aspect, the instruction length calculation results calculated by the first and second instruction length calculating means are compared, and resource allocation with a small instruction sequence length is performed. Is performed.

According to a fourth aspect of the present invention, in the compiler according to the first aspect, the first register resource is a part of the second register resource.

According to a fifth aspect of the present invention, in the compiler according to the fourth aspect, an instruction length of the first instruction format is shorter than an instruction length of the second format instruction format.

According to a sixth aspect of the present invention, there is provided the compiler according to the first aspect, wherein, among the variables in the source program, a frequently used variable is preferentially described in the first instruction format. Is allocated to the first register resource.

According to a seventh aspect of the present invention, in the compiler according to the sixth aspect, when the variable assigned to the first register resource is manipulated for each variable in the source program, The operation is described by preferentially using the instruction format.

According to an eighth aspect of the present invention, in the compiler according to the sixth aspect, among the variables in the program, a variable having a high frequency of use and a variable used together with the variable are preferentially ranked first. One register resource is allocated.

A recording medium according to a ninth aspect of the present invention is a computer-readable recording medium storing a machine language program obtained by translating a source program including a plurality of instructions, wherein the machine language program has a first register. An instruction described in a first instruction format using resources;
Using a second register resource different from the first register resource, instructions described in a second instruction format having an instruction length different from the first instruction format are mixed, and the first instruction The format and the second instruction format are characterized by being identified by a value of a specific area in the instruction.

With the above arrangement, according to the present invention, in a processor having an instruction set in which register resources that can be handled differ according to the type of instruction format and instruction lengths differ according to the type of instruction format, each variable is set to the first value. The length of the instruction string length when the instruction is described in the instruction format and the variable is assigned to the first register resource, and each variable is stored in the second register resource using the instruction described in the second instruction format. Is calculated, and an appropriate resource allocation is performed according to the calculation result, so that a machine language program with a small code size is generated.

[0051]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

First, regarding the machine language instruction set of the processor targeted by the compiler in the present invention,
As a processor having a machine language instruction set in which different register resources can be handled according to the instruction format and the instruction length varies according to the instruction format, data having two types of instruction formats proposed in Japanese Patent Application No. 10-59680. Processing equipment.

FIG. 1 is a configuration diagram of a compiler according to the embodiment of the present invention. The compiler uses the parsing means 1
, An optimization unit 2, a resource allocation unit 3, and a code generation unit 4.

The syntactic analysis means 1 performs lexical analysis, syntactic analysis and semantic analysis of the source program 5 stored as a file. The analysis result is output as an intermediate language program.

The optimizing means 2 optimizes the intermediate language program for the purpose of reducing the program size of the finally generated machine language program 6 and shortening the execution time.

The resource allocating means 3 determines the live range of the program variable, allocates a register or memory as a resource to each variable for each live range, and also allocates an optimal instruction for the same operation. .

The code generation means 4 converts the optimized intermediate language program into machine language instructions of the target machine according to the allocation result of the resource allocation means 3 and outputs it as a machine language program 6.

Since the syntax analysis means 1, the optimization means 2, and the code generation means 4 are known, detailed description will be omitted.

FIG. 2 is a configuration diagram of the resource allocating means 3 of the compiler according to the embodiment of the present invention. In the figure, reference numeral 31 denotes a live range determination unit that determines a live range for each variable. Reference numeral 32 denotes first instruction length calculating means for calculating an instruction sequence length when variables are assigned to registers using an instruction group having a first instruction format. In the first instruction format, only some registers can be handled. Reference numeral 33 denotes second instruction length calculation means for calculating an instruction length when a variable is assigned to a register using an instruction group having the second instruction format. The second instruction format can handle all register resources. 3
Reference numeral 4 denotes third instruction length calculation means for calculating an instruction length when a variable is allocated to a memory. Reference numeral 35 denotes a live range determination unit 3
1 is a variable resource allocating unit that allocates variable resources according to the determination result of one live range and the first to third instruction length calculating means 32 to 34. Reference numeral 36 denotes a control unit for controlling the entire resource allocation unit 3 except the control unit 36.

The operation of the resource allocation of the compiler configured as described above will be described below with reference to the drawings. FIG. 3 is a flowchart showing a processing flow of resource allocation of the control unit 36 of the compiler according to the embodiment of the present invention.

FIG. 4 shows an example of an intermediate code program to which the compiler allocates resources. The intermediate codes s1 to s8 shown in FIG. 4 are set as basic blocks to be subjected to the current resource allocation. For the sake of simplicity, here, resource allocation within a basic block will be described, but the same can be said for resource allocation beyond a basic block.

For the sake of simplicity, the allocation of register resources is performed under the following conditions.

1) Among the register resources (A0 to A3, D0 to D3) that can be operated in the first instruction format, address registers A0 to A3 are used as pointers and do not store data variables. I do.

2) Among register resources (A0 to A3, D0 to D3) that can be operated in the first instruction format,
The data registers D0 to D3 can all be used for storing and manipulating data variables. Of these, the registers D0 and D1 are used as work registers and no variables are assigned.

3) Register resources (A0-A3, D0-D3, E0-E7) that can be operated in the second instruction format
Of the extension registers E0 to E7, data and addresses can be freely used.

These conditions are set for the sake of simplicity, and do not impose any restrictions on the present invention.

A process for allocating resources to the intermediate code program in FIG. 4 will be described with reference to this flowchart.

First, in step 301, the life span and reference frequency of each variable are checked for all variables in the basic block. Here, register allocation is performed only for register resources that can be operated in the first instruction format, specifically, registers A0 to A3 and D0 to D3.
Only. Based on the result, the variable resource allocating unit 35 checks whether register allocation is possible for register resources that can be operated in the first instruction format. Here, it is not important how to assign variables to these registers, and the instruction length of the first instruction format is larger than the instruction length of the second instruction format for the same operation. Since it is smaller than the length, it is most important that register resources be allocated only to register resources that can be handled in the first instruction format.

Next, in step 302, step 30
Based on the check result of No. 1, it is determined whether or not all variables can be allocated resources only with register resources that can be operated in the first instruction format.

If possible, variables are allocated only to register resources that can be operated in the first instruction format, and resource allocation ends (step 303).

Since there are many variables in a normal basic block, in most cases, there are variables that cannot be allocated to register resources that can be operated in the first instruction format. In step 302, if all variables cannot be assigned with register resources that can be operated in the first instruction format, first, register resources that can be operated in the first instruction format are assigned with priority. The priority assignment processing will be described below.

FIG. 5 is a diagram showing the lifespan of variables in the basic block and the reference frequency, which were examined in step 301 to determine variables to be allocated to register resources that can be operated in the first instruction format. It is. As a result, variables p1 and p2, which are the most frequently referred, are assigned to registers D2 and D3 among the registers that can be operated in the first instruction format. Here, the decision as to which variable is to be assigned to a register is made based on the number of register resources that can be handled, the live range of each variable, and the reference frequency. In this case, since the registers D0 and D1 cannot be used due to the above-described conditions, the register resources that can be used are two registers D2 and D3, and the two most frequently used variables are allocated.

Next, in step 304, the variable resource allocating unit 35 assigns the first variable to the first
Register resources that cannot be operated in the instruction format of the second instruction format and can be operated only by the second instruction format, specifically,
The first combination (resource allocation) of allocating to memory resources is classified.

Further, in step 304, when the control unit 36 has allocated the register resources in the first combination, it is appropriate to use the first instruction format using the work registers D0 and D1. Alternatively, a second combination (allocation of instructions) is considered, including whether it is appropriate to use the second instruction format without using the work registers D0 and D1. FIGS. 7 to 9 show examples of the second combination for the specific first combination using the extension registers E0 to E7 and the registers D2 and D3. The description of these drawings will be described later in detail. Ultimately, the instruction sequence length is calculated for all combinations.
It does not matter which combination you choose.

In steps 305 to 307 described below, the instruction sequence length is calculated for each of the second combinations (FIGS. 7 to 9).

That is, in step 305, the length of the instruction sequence allocated to the registers is calculated using the first instruction format. In step 306, the length of the instruction sequence allocated to the registers is calculated using the second instruction format.

Similarly, in step 307, variables are allocated not to the register resources but to the memory resources, and the instruction sequence length when the first instruction format is allocated is calculated.
Here, for simplicity of description, it is assumed that an address when a variable is assigned to a memory resource can be specified by an absolute address of 16 bits, and a memory / register transfer instruction for the variable is 3 bytes. And In step 307, variables are allocated to memory resources instead of register resources, and the instruction sequence length when the second instruction format is allocated is calculated. Here, for the sake of simplicity, it is assumed that an address when a variable is assigned to a memory resource can be specified by an absolute address of 16 bits.
The memory / register move instruction for the variable is 4
Byte.

In step 308, the step 305 is executed.
The instruction sequence length of the entire basic block in this combination is calculated using the result of Step 307.

The above processing is executed for all combinations (step 309), and in step 310, the combination that results in the minimum instruction sequence length in the basic block is selected).

The processing of the compiler for minimizing the machine language program size by the above processing will be described in more detail with reference to the drawings.

First, FIG. 6 shows that register resources which can be accessed by the first instruction format for register assignment of each variable and other register resources are assigned to register resources in the order of appearance without assigning priority. 2 shows a resource assignment of variables in a case where the instruction is assigned (conventional method), and a machine language instruction program when instructions are assigned in accordance with the assignment. In this case, the instruction sequence length for the basic block is 46 bytes.

Next, FIG. 7 shows only the registers that can be operated in the first instruction format by the processing of step 302 in FIG. 3 based on the live ranges and the appearance frequencies of the variables shown in FIG. In this case, specifically, registers are preferentially assigned to the D2 register and the D3 register, and as a result,
A resource allocation of a variable when the variable p1 is allocated to the register D2 and a variable p2 is allocated to the register D3, and a machine language instruction program when an instruction is allocated corresponding to the allocation. In this case, the instruction sequence length for the basic block is 42 bytes, which indicates that the code size of 4 bytes can be reduced as compared with the case shown in FIG.

Further, in FIG. 8, the assignment of register resources is the same as that described in FIG. 7, but instead of selecting the second instruction format as the instruction format, the first instruction format is used.
2 shows a machine language instruction program when the instruction format is selected and the method of assigning instructions is changed. in this case,
The total instruction length of the basic instruction block itself is 44 bytes, which is 2 bytes larger than that of FIG. 7, but if the machine language instruction sequence length is compared for each intermediate language, the intermediate language Regarding s1 and the intermediate language s8, it can be seen that these languages s1 and s8 each include an instruction described in the first instruction format, and each machine language instruction length is reduced by one byte. Here, in the intermediate language s1, frequently used variables p1 and p2 are allocated to registers D2 and D3 in the first register file 220, respectively. The variable t1 used together with these variables p1 and p2 is also temporarily allocated to the work register D0 in the first register file 220. This gives the instruction mo
v D2, D0 and the instructions add D3, D0 are each described in one byte using the first instruction format.

Finally, FIG. 9 shows a machine instruction program in which the allocation of register resources and the allocation of instructions are optimized based on the results shown in FIGS. In FIG. 9, the intermediate language having a shorter machine language instruction length among the intermediate languages of FIGS. 7 and 8, that is, the intermediate languages s2 to s7 of FIG. Uses the intermediate languages s1 and s8 of FIG. Note that the intermediate languages s2 and s3 in FIG. 7 and the intermediate languages s2 and s3 in FIG. 8 have the same machine instruction length, but the intermediate languages s2 and s3 in FIG. The intermediate language is used. As a result, in FIG. 9, the code is further reduced by 2 bytes from the state of FIG. 7, and the machine language instruction program having the smallest code size is different from the intermediate language program shown in FIGS. Has been generated.

The machine language instruction program shown in FIG. 9 includes an instruction mov D2, D0 and an instruction add D3, D0 of the intermediate language s1 and an instruction add5, D0 of the intermediate language s8.
0 is described in the first instruction format using the registers D0, D2, and D3, and the other intermediate languages s2 to s7 are stored in the second instruction format.
Is described in the second instruction format using the register file 120 of
It is recorded on a computer-readable recording medium.

In the above example, the variables p1, p2, t1 to t8 of the basic block are stored in the registers D2, D3, E8.
Although variables are allocated to 0 to E7, if variables requiring resource allocation simultaneously exist beyond the number of registers that can be allocated, these variables are allocated to the registers and memory resources. In this case, step S30 in FIG.
In step 7, the instruction sequence length when allocated to memory resources is calculated. When a part of the variables is allocated to the memory resources in this manner, in the instruction sequence including the data transfer instruction, any of the registers in the first register file 220 is temporarily used to use the first instruction format. You. As a result, the number of instructions increases, but the length of the instruction sequence becomes shorter, and the instruction code size may become smaller.

[0087]

As described above, according to the compiler of the present invention, in a processor having an instruction set which can handle different register resources according to the type of instruction format and has a different instruction length according to the type of instruction format. Thus, a remarkable effect that a compiler capable of generating a machine language program having a small code size can be provided is obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of a compiler according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration of a resource allocating unit of the compiler according to the embodiment;

FIG. 3 is a flowchart illustrating a processing flow relating to resource allocation in a resource allocation unit of the compiler according to the embodiment;

FIG. 4 is a diagram illustrating an example of an intermediate language program.

FIG. 5 is a diagram showing a live range and a reference frequency of each variable in the intermediate language program.

FIG. 6 is a diagram showing an example of resource allocation of variables and a machine language instruction program corresponding thereto.

FIG. 7 is a diagram showing an example of resource allocation of variables and a machine language instruction program corresponding thereto.

FIG. 8 is a diagram showing an example of resource allocation of variables and a machine language instruction program corresponding thereto.

FIG. 9 is a diagram showing an example of resource allocation of variables and a machine language instruction program corresponding thereto.

FIG. 10 is a diagram showing a first instruction format (1) of a data processing device targeted by a compiler according to the present invention.

FIG. 11 is a diagram showing a part of a list of instructions in a first instruction format (1) of the data processing apparatus.

FIG. 12 is a diagram showing a first instruction format (2) of the data processing device.

FIG. 13 is a diagram showing a part of a list of instructions in a first instruction format (2) of the data processing apparatus.

FIG. 14 is a block diagram showing a configuration of a first register file in the data processing device.

FIG. 15 is a diagram showing register numbers of a register file when an instruction of a first instruction format of the data processing device is executed.

FIG. 16 is a diagram showing a second instruction format of the data processing device.

FIG. 17 is a diagram showing a part of a list of instructions in a second instruction format of the data processing apparatus.

FIG. 18 is a block diagram showing a configuration of a register file of the data processing device.

FIG. 19 is a diagram showing register numbers of a register file when executing an instruction of a first instruction format in the data processing apparatus.

FIG. 20 is a diagram showing a register number of a register file when an instruction of a second instruction format is executed in the data processing device.

[Description of Signs] 1 syntax analysis means 2 optimization means 3 resource allocation means 4 code generation means 31 live range determination unit 32 first instruction length calculation means 33 second instruction length calculation means 34 third instruction length calculation means 35 Variable resource allocation unit 36 Control unit

Claims (9)

[Claims] 1. A compiler for inputting a source program consisting of a plurality of instructions and translating the source program into a machine language program, wherein each variable in the source program is described by an instruction described in a first instruction format. A first instruction sequence length calculating means for calculating the length of an instruction sequence when the instruction sequence is allocated to a first register resource using the first and second register resources; A second instruction sequence for calculating the length of an instruction sequence when allocated to a second register resource different from the first register resource using an instruction described in a second instruction format having a different length A compiler comprising: a length calculator; and allocating resources using the instruction length calculation results calculated by the first and second instruction length calculators. 2. The apparatus according to claim 1, further comprising: a third instruction sequence length calculating unit configured to calculate an instruction sequence length when each variable in the source program is allocated to a memory, wherein the first, second, and third instructions are provided. 2. The compiler according to claim 1, wherein resource allocation is performed using an instruction length calculation result calculated by the length calculation means. 3. The compiler according to claim 1, wherein the instruction length calculation results calculated by the first and second instruction length calculation means are compared, and resource allocation with a small instruction string length is performed. 4. The compiler according to claim 1, wherein said first register resource is a part of said second register resource. 5. The compiler according to claim 4, wherein an instruction length of said first instruction format is shorter than an instruction length of said second format instruction format. 6. A method according to claim 1, wherein, among the variables in the source program, a frequently used variable is preferentially allocated to a first register resource using an instruction described in a first instruction format. The compiler according to claim 1, wherein 7. When operating a variable allocated to the first register resource for each variable in the source program, the operation is described by preferentially using the first instruction format. 7. The compiler according to claim 6, wherein: 8. The method according to claim 6, wherein, among the variables in the program, a frequently used variable and a variable used together with the variable are preferentially allocated to the first register resource. Compiler. 9. A computer-readable recording medium recording a machine language program translated from a source program including a plurality of instructions, wherein the machine language program uses a first register resource to execute a first instruction format. And an instruction described in a second instruction format having an instruction length different from the first instruction format using a second register resource different from the first register resource. The first instruction format and the second instruction format are identified by a value of a specific area in the instruction.