EP1267255A3 - Conditional branch execution in a processor with multiple data paths - Google Patents
Conditional branch execution in a processor with multiple data paths Download PDFInfo
- Publication number
- EP1267255A3 EP1267255A3 EP02254001A EP02254001A EP1267255A3 EP 1267255 A3 EP1267255 A3 EP 1267255A3 EP 02254001 A EP02254001 A EP 02254001A EP 02254001 A EP02254001 A EP 02254001A EP 1267255 A3 EP1267255 A3 EP 1267255A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- indicators
- state
- processor
- field
- multiple data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 238000000034 method Methods 0.000 abstract 2
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30054—Unconditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30061—Multi-way branch instructions, e.g. CASE
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Executing Machine-Instructions (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
determining from the opcode field whether or not the test will check the state of one indicator or a plurality of indicators in the designated control store, accessing the designated control store to check the state of said one or said plurality of indicators depending on the determination, and generating a branch target address using information in the destination field in dependence on the state of the or each indicator checked.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US29675801P | 2001-06-11 | 2001-06-11 | |
US296758P | 2001-06-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1267255A2 EP1267255A2 (en) | 2002-12-18 |
EP1267255A3 true EP1267255A3 (en) | 2003-05-02 |
Family
ID=23143419
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02254001A Ceased EP1267255A3 (en) | 2001-06-11 | 2002-06-10 | Conditional branch execution in a processor with multiple data paths |
Country Status (2)
Country | Link |
---|---|
US (1) | US7861071B2 (en) |
EP (1) | EP1267255A3 (en) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7249242B2 (en) | 2002-10-28 | 2007-07-24 | Nvidia Corporation | Input pipeline registers for a node in an adaptive computing engine |
US7127593B2 (en) * | 2001-06-11 | 2006-10-24 | Broadcom Corporation | Conditional execution with multiple destination stores |
US6986025B2 (en) * | 2001-06-11 | 2006-01-10 | Broadcom Corporation | Conditional execution per lane |
US7434036B1 (en) | 2002-08-30 | 2008-10-07 | Verisilicon Holdings Co. Ltd. | System and method for executing software program instructions using a condition specified within a conditional execution instruction |
US7299343B2 (en) * | 2002-09-27 | 2007-11-20 | Verisilicon Holdings (Cayman Islands) Co. Ltd. | System and method for cooperative execution of multiple branching instructions in a processor |
US20040064684A1 (en) * | 2002-09-30 | 2004-04-01 | Kalluri Seshagiri P. | System and method for selectively updating pointers used in conditionally executed load/store with update instructions |
US20060259752A1 (en) * | 2005-05-13 | 2006-11-16 | Jeremiassen Tor E | Stateless Branch Prediction Scheme for VLIW Processor |
US9069547B2 (en) | 2006-09-22 | 2015-06-30 | Intel Corporation | Instruction and logic for processing text strings |
US8677106B2 (en) * | 2009-09-24 | 2014-03-18 | Nvidia Corporation | Unanimous branch instructions in a parallel thread processor |
GB2474521B (en) * | 2009-10-19 | 2014-10-15 | Ublox Ag | Program flow control |
US8908564B2 (en) * | 2010-06-28 | 2014-12-09 | Avaya Inc. | Method for Media Access Control address learning and learning rate suppression |
US9696975B2 (en) * | 2010-09-03 | 2017-07-04 | International Business Machines Corporation | Allocating register halves independently |
US8924693B2 (en) * | 2011-01-21 | 2014-12-30 | Apple Inc. | Predicting a result for a predicate-generating instruction when processing vector instructions |
CN111527485B (en) * | 2017-11-03 | 2023-09-12 | 相干逻辑公司 | memory network processor |
US20240103860A1 (en) * | 2022-09-26 | 2024-03-28 | Advanced Micro Devices, Inc. | Predicates for Processing-in-Memory |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0130381A2 (en) * | 1983-06-30 | 1985-01-09 | International Business Machines Corporation | Mechanism for implementing one machine cycle executable branch-on-any-bit-in-any-register instructions in a primitive instruction set computing system |
US6052776A (en) * | 1996-10-18 | 2000-04-18 | Hitachi, Ltd. | Branch operation system where instructions are queued until preparations is ascertained to be completed and branch distance is considered as an execution condition |
EP1089170A2 (en) * | 1999-10-01 | 2001-04-04 | Hitachi, Ltd. | Processor architecture and method of processing branch control instructions |
Family Cites Families (36)
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US3325785A (en) * | 1964-12-18 | 1967-06-13 | Ibm | Efficient utilization of control storage and access controls therefor |
US3958227A (en) * | 1974-09-24 | 1976-05-18 | International Business Machines Corporation | Control store system with flexible control word selection |
US4589065A (en) * | 1983-06-30 | 1986-05-13 | International Business Machines Corporation | Mechanism for implementing one machine cycle executable trap instructions in a primitive instruction set computing system |
US4589087A (en) * | 1983-06-30 | 1986-05-13 | International Business Machines Corporation | Condition register architecture for a primitive instruction set machine |
US4748585A (en) | 1985-12-26 | 1988-05-31 | Chiarulli Donald M | Processor utilizing reconfigurable process segments to accomodate data word length |
US5056015A (en) | 1988-03-23 | 1991-10-08 | Du Pont Pixel Systems Limited | Architectures for serial or parallel loading of writable control store |
US5001662A (en) | 1989-04-28 | 1991-03-19 | Apple Computer, Inc. | Method and apparatus for multi-gauge computation |
US5471593A (en) * | 1989-12-11 | 1995-11-28 | Branigin; Michael H. | Computer processor with an efficient means of executing many instructions simultaneously |
GB2273377A (en) | 1992-12-11 | 1994-06-15 | Hughes Aircraft Co | Multiple masks for array processors |
DE4345028A1 (en) * | 1993-05-06 | 1994-11-10 | Hewlett Packard Co | Device for reducing delays due to branching |
JP2832899B2 (en) | 1993-05-31 | 1998-12-09 | 松下電器産業株式会社 | Data processing device and data processing method |
AU677673B2 (en) | 1993-10-12 | 1997-05-01 | Samsung Electronics Co., Ltd. | Method and apparatus for executing an atomic read-modify-write instruction |
US5530825A (en) * | 1994-04-15 | 1996-06-25 | Motorola, Inc. | Data processor with branch target address cache and method of operation |
US5568631A (en) | 1994-05-05 | 1996-10-22 | International Business Machines Corporation | Multiprocessor system with a shared control store accessed with predicted addresses |
US5926642A (en) | 1995-10-06 | 1999-07-20 | Advanced Micro Devices, Inc. | RISC86 instruction set |
JP3442225B2 (en) * | 1996-07-11 | 2003-09-02 | 株式会社日立製作所 | Arithmetic processing unit |
JPH1049368A (en) * | 1996-07-30 | 1998-02-20 | Mitsubishi Electric Corp | Microporcessor having condition execution instruction |
US5838984A (en) | 1996-08-19 | 1998-11-17 | Samsung Electronics Co., Ltd. | Single-instruction-multiple-data processing using multiple banks of vector registers |
US5909572A (en) | 1996-12-02 | 1999-06-01 | Compaq Computer Corp. | System and method for conditionally moving an operand from a source register to a destination register |
US6366999B1 (en) * | 1998-01-28 | 2002-04-02 | Bops, Inc. | Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution |
US6338137B1 (en) | 1998-05-29 | 2002-01-08 | Texas Instruments Incorporated | Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer |
US6240510B1 (en) * | 1998-08-06 | 2001-05-29 | Intel Corporation | System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions |
US7114056B2 (en) | 1998-12-03 | 2006-09-26 | Sun Microsystems, Inc. | Local and global register partitioning in a VLIW processor |
US6282628B1 (en) * | 1999-02-24 | 2001-08-28 | International Business Machines Corporation | Method and system for a result code for a single-instruction multiple-data predicate compare operation |
US6675291B1 (en) | 1999-05-31 | 2004-01-06 | International Business Machines Corporation | Hardware device for parallel processing of any instruction within a set of instructions |
GB2352536A (en) | 1999-07-21 | 2001-01-31 | Element 14 Ltd | Conditional instruction execution |
US6513109B1 (en) * | 1999-08-31 | 2003-01-28 | International Business Machines Corporation | Method and apparatus for implementing execution predicates in a computer processing system |
DE19942836C2 (en) | 1999-09-08 | 2003-04-17 | Porsche Ag | Disc element for a wheel bolt or wheel nut of a motor vehicle |
US6484255B1 (en) * | 1999-09-20 | 2002-11-19 | Intel Corporation | Selective writing of data elements from packed data based upon a mask using predication |
US6622238B1 (en) * | 2000-01-24 | 2003-09-16 | Hewlett-Packard Development Company, L.P. | System and method for providing predicate data |
US6748521B1 (en) | 2000-02-18 | 2004-06-08 | Texas Instruments Incorporated | Microprocessor with instruction for saturating and packing data |
US6757819B1 (en) | 2000-02-18 | 2004-06-29 | Texas Instruments Incorporated | Microprocessor with instructions for shifting data responsive to a signed count value |
US7017032B2 (en) | 2001-06-11 | 2006-03-21 | Broadcom Corporation | Setting execution conditions |
US6986025B2 (en) | 2001-06-11 | 2006-01-10 | Broadcom Corporation | Conditional execution per lane |
US7127593B2 (en) | 2001-06-11 | 2006-10-24 | Broadcom Corporation | Conditional execution with multiple destination stores |
KR100419344B1 (en) | 2001-09-10 | 2004-02-19 | 주식회사 오스테오시스 | Apparatus for measuring density of bone |
-
2002
- 2002-05-30 US US10/157,079 patent/US7861071B2/en not_active Expired - Fee Related
- 2002-06-10 EP EP02254001A patent/EP1267255A3/en not_active Ceased
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0130381A2 (en) * | 1983-06-30 | 1985-01-09 | International Business Machines Corporation | Mechanism for implementing one machine cycle executable branch-on-any-bit-in-any-register instructions in a primitive instruction set computing system |
US6052776A (en) * | 1996-10-18 | 2000-04-18 | Hitachi, Ltd. | Branch operation system where instructions are queued until preparations is ascertained to be completed and branch distance is considered as an execution condition |
EP1089170A2 (en) * | 1999-10-01 | 2001-04-04 | Hitachi, Ltd. | Processor architecture and method of processing branch control instructions |
Also Published As
Publication number | Publication date |
---|---|
EP1267255A2 (en) | 2002-12-18 |
US20020199090A1 (en) | 2002-12-26 |
US7861071B2 (en) | 2010-12-28 |
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