JP2001216160A5 - - Google Patents

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Publication number
JP2001216160A5
JP2001216160A5 JP2001020550A JP2001020550A JP2001216160A5 JP 2001216160 A5 JP2001216160 A5 JP 2001216160A5 JP 2001020550 A JP2001020550 A JP 2001020550A JP 2001020550 A JP2001020550 A JP 2001020550A JP 2001216160 A5 JP2001216160 A5 JP 2001216160A5
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JP
Japan
Prior art keywords
instruction
instructions
register
bit
unwritten
Prior art date
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Application number
JP2001020550A
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English (en)
Japanese (ja)
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JP3808314B2 (ja
JP2001216160A (ja
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Priority claimed from US09/493,986 external-priority patent/US6715060B1/en
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Publication of JP2001216160A publication Critical patent/JP2001216160A/ja
Publication of JP2001216160A5 publication Critical patent/JP2001216160A5/ja
Application granted granted Critical
Publication of JP3808314B2 publication Critical patent/JP3808314B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2001020550A 2000-01-28 2001-01-29 長レイテンシ命令に対する命令属性およびステータス情報を示す処理システムおよび方法 Expired - Fee Related JP3808314B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/493,986 US6715060B1 (en) 2000-01-28 2000-01-28 Utilizing a scoreboard with multi-bit registers to indicate a progression status of an instruction that retrieves data
US09/493986 2000-01-28

Publications (3)

Publication Number Publication Date
JP2001216160A JP2001216160A (ja) 2001-08-10
JP2001216160A5 true JP2001216160A5 (enExample) 2005-07-07
JP3808314B2 JP3808314B2 (ja) 2006-08-09

Family

ID=23962536

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001020550A Expired - Fee Related JP3808314B2 (ja) 2000-01-28 2001-01-29 長レイテンシ命令に対する命令属性およびステータス情報を示す処理システムおよび方法

Country Status (2)

Country Link
US (2) US6715060B1 (enExample)
JP (1) JP3808314B2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6715060B1 (en) * 2000-01-28 2004-03-30 Hewlett-Packard Development Company, L.P. Utilizing a scoreboard with multi-bit registers to indicate a progression status of an instruction that retrieves data
US7055021B2 (en) * 2002-02-05 2006-05-30 Sun Microsystems, Inc. Out-of-order processor that reduces mis-speculation using a replay scoreboard
US6996665B2 (en) * 2002-12-30 2006-02-07 International Business Machines Corporation Hazard queue for transaction pipeline
US7711928B2 (en) * 2004-03-31 2010-05-04 Oracle America, Inc. Method and structure for explicit software control using scoreboard status information
JP4243271B2 (ja) * 2005-09-30 2009-03-25 富士通マイクロエレクトロニクス株式会社 データ処理装置およびデータ処理方法
US7610470B2 (en) * 2007-02-06 2009-10-27 Sun Microsystems, Inc. Preventing register data flow hazards in an SST processor
GB2447907B (en) * 2007-03-26 2009-02-18 Imagination Tech Ltd Processing long-latency instructions in a pipelined processor
US20100077145A1 (en) * 2008-09-25 2010-03-25 Winkel Sebastian C Method and system for parallel execution of memory instructions in an in-order processor
US8850129B2 (en) * 2010-06-24 2014-09-30 International Business Machines Corporation Memory ordered store system in a multiprocessor computer system
US9529596B2 (en) * 2011-07-01 2016-12-27 Intel Corporation Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bits
US9086873B2 (en) 2013-03-15 2015-07-21 Intel Corporation Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture
GB2563582B (en) * 2017-06-16 2020-01-01 Imagination Tech Ltd Methods and systems for inter-pipeline data hazard avoidance
US11455171B2 (en) * 2019-05-29 2022-09-27 Gray Research LLC Multiported parity scoreboard circuit

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903196A (en) * 1986-05-02 1990-02-20 International Business Machines Corporation Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor
US5219781A (en) * 1988-12-08 1993-06-15 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing semiconductor memory device having a stacked type capacitor
US5179702A (en) * 1989-12-29 1993-01-12 Supercomputer Systems Limited Partnership System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling
JP3146077B2 (ja) 1991-11-15 2001-03-12 松下電器産業株式会社 プロセッサ
JPH05298097A (ja) 1992-04-20 1993-11-12 Mitsubishi Electric Corp 情報処理装置
US6101596A (en) 1995-03-06 2000-08-08 Hitachi, Ltd. Information processor for performing processing without register conflicts
US5838943A (en) * 1996-03-26 1998-11-17 Advanced Micro Devices, Inc. Apparatus for speculatively storing and restoring data to a cache memory
US5860017A (en) 1996-06-28 1999-01-12 Intel Corporation Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction
US5859999A (en) 1996-10-03 1999-01-12 Idea Corporation System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers
US6219781B1 (en) * 1998-12-30 2001-04-17 Intel Corporation Method and apparatus for performing register hazard detection
US6715060B1 (en) * 2000-01-28 2004-03-30 Hewlett-Packard Development Company, L.P. Utilizing a scoreboard with multi-bit registers to indicate a progression status of an instruction that retrieves data

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