JP2001110934A - Semiconductor device, semiconductor chip support board therefor, and manufacturing method thereof device - Google Patents

Semiconductor device, semiconductor chip support board therefor, and manufacturing method thereof device

Info

Publication number
JP2001110934A
JP2001110934A JP28735999A JP28735999A JP2001110934A JP 2001110934 A JP2001110934 A JP 2001110934A JP 28735999 A JP28735999 A JP 28735999A JP 28735999 A JP28735999 A JP 28735999A JP 2001110934 A JP2001110934 A JP 2001110934A
Authority
JP
Japan
Prior art keywords
semiconductor chip
opening
supporting substrate
semiconductor device
connection portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28735999A
Other languages
Japanese (ja)
Inventor
Akio Yamazaki
聡夫 山崎
Yoshiaki Wakashima
喜昭 若島
Kazuhisa Suzuki
和久 鈴木
Hiroshi Morita
宏 守田
Naoki Fukutomi
直樹 福富
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP28735999A priority Critical patent/JP2001110934A/en
Publication of JP2001110934A publication Critical patent/JP2001110934A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device together with its manufacturing method by which reliability and productivity of the semiconductor device wherein a chip is mounted on one surface of a semiconductor chip support board with an adhesive are improved. SOLUTION: A semiconductor chip 3 comprising a center pad is mounted on one surface 9a of a semiconductor chip support board 1 with an adhesive 5. An opening part is provided at points of semiconductor chip support board 1 and adhesive 15 which correspond to the center pad position of the semiconductor chip 3, with the opening parts filled with a sealing material 12. Here, an opening part 14 provided at the adhesive 5 is larger than an opening part 6 provided at the semiconductor chip support board 1.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置、それ
に用いる半導体チップ支持基板及び半導体装置の製造方
法に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, a semiconductor chip supporting substrate used for the same, and a method of manufacturing the semiconductor device.

【０００２】[0002]

【従来の技術】従来のＢＧＡ（Ball Grid Array）型で
センターパッドを有する半導体チップが搭載されている
半導体装置としては、例えば特開平１０−３２１６７２
号公報に例示されているものがある。2. Description of the Related Art A conventional BGA (Ball Grid Array) type semiconductor device on which a semiconductor chip having a center pad is mounted is disclosed, for example, in JP-A-10-321672.
Is exemplified in Japanese Patent Publication No.

【０００３】上記従来技術の半導体装置においては、図
１７に示すように、第一の面に導体リード１００７を備
える絶縁基板１００３を含み、主面１００１ａに電極パ
ッド１００２を備える半導体チップ１００１はその主面
を上記第一の面に向けて、絶縁基板１００３上に接着層
１００８を介して搭載される。As shown in FIG. 17, the semiconductor device of the prior art includes an insulating substrate 1003 having a conductor lead 1007 on a first surface and a semiconductor chip 1001 having an electrode pad 1002 on a main surface 1001a. It is mounted on an insulating substrate 1003 with an adhesive layer 1008 facing the first surface.

【０００４】絶縁基板１００３はまた、第一の面側に導
体リード１００７のインナーリード及び電極パッド１０
０２を露出させるための開口１００４及び１００５を備
えている。開口１００４及び１００５を通して伸びる導
体ワイヤ１００９により導体リード１００７のインナー
リードと電極パッド１００２とが接続され、導体リード
１００７のアウターリードには外部接続端子１０１１が
接続される。[0004] The insulating substrate 1003 also has an inner lead of the conductor lead 1007 and an electrode pad 10
02 is provided with openings 1004 and 1005 for exposing 02. The inner lead of the conductor lead 1007 and the electrode pad 1002 are connected by the conductor wire 1009 extending through the openings 1004 and 1005, and the outer connection terminal 1011 is connected to the outer lead of the conductor lead 1007.

【０００５】上記導体ワイヤ１００９及び開口１００
４、１００５は、これらが外気に晒されないように保護
するための封止材として樹脂１０１０が形成されてい
る。The conductor wire 1009 and the opening 100
In Nos. 4 and 1005, a resin 1010 is formed as a sealing material for protecting them from being exposed to the outside air.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、上記従
来技術の半導体装置では、絶縁基板１００３及び導体リ
ード１００７から構成される配線板と半導体チップ１０
０１との接着を実現している接着層１００８と樹脂１０
１０とのはく離がおこる場合があり、当該半導体装置の
信頼性を下げる一因となっている。However, in the above-described conventional semiconductor device, the wiring board composed of the insulating substrate 1003 and the conductor leads 1007 and the semiconductor chip 10
Adhesive layer 1008 and resin 10 realizing the adhesion with resin 01
Separation from the semiconductor device 10 may occur, which is one of the causes of lowering the reliability of the semiconductor device.

【０００７】上述した接着層１００８と樹脂１０１０と
のはく離は、絶縁基板１００３及び導体リード１００７
から構成される配線板における開口１００４に比べて接
着層１００８の開口１１００の大きさが小さく、接着層
１００８と樹脂１０１０とのはく離を誘発しやすくなっ
ているためと考えられる。The peeling between the adhesive layer 1008 and the resin 1010 is performed by the insulating substrate 1003 and the conductor leads 1007.
It is considered that the size of the opening 1100 of the adhesive layer 1008 is smaller than that of the opening 1004 in the wiring board made of, and the separation between the adhesive layer 1008 and the resin 1010 is easily induced.

【０００８】本発明は上記点を鑑みてなされたもので、
その目的は、半導体チップ支持基板の一方の面に接着材
を介してチップが搭載されている半導体装置および該半
導体の製造方法において、該半導体装置の信頼性の向上
および生産性の向上を図ることが可能な半導体装置、そ
れに用いる半導体チップ支持基板及びそれらの製造方法
を提供することにある。[0008] The present invention has been made in view of the above points,
An object of the present invention is to improve reliability and productivity of a semiconductor device in which a chip is mounted on one surface of a semiconductor chip support substrate via an adhesive and a method of manufacturing the semiconductor. It is an object of the present invention to provide a semiconductor device which can be used, a semiconductor chip supporting substrate used for the same, and a method for manufacturing the same.

【０００９】[0009]

【課題を解決するための手段】上記目的を達成するため
に本発明は、半導体チップ支持基板の一方の面にはイン
ナー接続部及び外部接続部が設けられ、他方の面に形成
された接着材を介してセンターパッドを有する半導体チ
ップが搭載された半導体装置およびその製造方法におい
て、前記半導体チップのセンターパッド位置に対応する
前記半導体チップ支持基板及び前記接着材層の位置にそ
れぞれ開口部が形成され、前記開口部を経由するボンデ
ィングリードにより前記半導体チップのパッドが前記イ
ンナー接続部と接続され、前記開口部に封止材が充填さ
れているものであって、前記接着材層に形成された開口
部が前記半導体チップ支持基板に形成された開口部に比
べて大きいことを特徴とする。In order to achieve the above object, the present invention provides a semiconductor chip supporting substrate in which an inner connecting portion and an outer connecting portion are provided on one surface and an adhesive formed on the other surface. A semiconductor device having a semiconductor chip having a center pad mounted thereon and a method of manufacturing the same, wherein openings are respectively formed at positions of the semiconductor chip support substrate and the adhesive material layer corresponding to the center pad position of the semiconductor chip. A pad connected to the inner connecting portion by a bonding lead passing through the opening, wherein the opening is filled with a sealing material, wherein the opening formed in the adhesive layer is The portion is larger than an opening formed in the semiconductor chip supporting substrate.

【００１０】ここで、前記接着材層に設けられた開口部
輪郭と、それに対応する前記基板に設けられた開口部輪
郭との水平距離が０．０３ｍｍ以上０．５ｍｍ以下であ
ることが好ましい。Here, it is preferable that the horizontal distance between the contour of the opening provided in the adhesive layer and the corresponding contour of the opening provided in the substrate is 0.03 mm or more and 0.5 mm or less.

【００１１】また、前記接着材層に設けられた開口部よ
り水平方向外側に、前記インナー接続部を配置すること
が好ましい。It is preferable that the inner connecting portion is disposed horizontally outside of an opening provided in the adhesive layer.

【００１２】また、前記半導体チップ支持基板の開口部
直下に前記半導体チップのパッドが位置するように、前
記半導体チップを前記半導体チップ支持基板に搭載し、
前記接着材層の開口部が、前記半導体チップ支持基板の
開口部直下領域を少なくとも含み、前記直下領域よりも
大きい面積を備えることが好ましい。The semiconductor chip is mounted on the semiconductor chip support substrate such that pads of the semiconductor chip are located immediately below the opening of the semiconductor chip support substrate.
It is preferable that the opening of the adhesive layer includes at least a region immediately below the opening of the semiconductor chip supporting substrate, and has an area larger than the region immediately below the opening.

【００１３】また、前記封止材を充填する際には真空差
圧印刷法を用いることが好ましい。When filling the sealing material, it is preferable to use a vacuum differential pressure printing method.

【００１４】また、上記目的を達成するために本発明
は、半導体チップ支持基板の一方の面にはインナー接続
部及び外部接続部が設けられ、他方の面には形成された
接着材を介してセンターパッドを有する半導体チップが
搭載された半導体装置において、前記半導体チップのセ
ンターパッド位置に対応する前記半導体チップ支持基板
及び前記接着材層の位置に、該接着材層の開口部が該半
導体チップ支持基板の開口部に比べて大きくなるように
それぞれ開口部が形成され、前記開口部を経由するボン
ディングリードにより前記半導体チップのパッドが前記
インナー接続部と接続され、前記開口部に封止材が充填
されているものであって、前記半導体チップ支持基板の
一方の面には、前記開口部を略中心とした凹部が形成さ
れていることを特徴とする。According to another aspect of the present invention, there is provided a semiconductor chip supporting substrate in which an inner connecting portion and an outer connecting portion are provided on one surface and an adhesive formed on the other surface. In a semiconductor device in which a semiconductor chip having a center pad is mounted, an opening of the adhesive layer is provided at a position of the semiconductor chip supporting substrate and the adhesive layer corresponding to a center pad position of the semiconductor chip. Each opening is formed so as to be larger than the opening of the substrate, the pad of the semiconductor chip is connected to the inner connection portion by a bonding lead passing through the opening, and the opening is filled with a sealing material. Wherein a concave portion is formed on one surface of the semiconductor chip supporting substrate, the concave portion being substantially centered on the opening. To.

【００１５】ここで、前記半導体チップ支持基板の一方
の面に形成された凹部の一部は、前記インナー接続部で
構成されることが好ましい。Here, it is preferable that a part of the concave portion formed on one surface of the semiconductor chip supporting substrate is constituted by the inner connecting portion.

【００１６】また、上記目的を達成するために本発明
は、上述した本発明の半導体装置のいずれかに用いられ
る半導体チップ支持基板において、その一方の面にはイ
ンナー接続部及び外部接続部が設けられ、他方の面には
接着材層を介した半導体チップ搭載面を有し、半導体チ
ップ支持基板に開口部が半導体チップのパッド位置に対
応するように設けられ、前記接着材層に設ける開口部が
前記半導体チップ支持基板に設けられた開口部に比べて
大きいことを特徴とする。According to another aspect of the present invention, there is provided a semiconductor chip supporting substrate used in any of the above-described semiconductor devices according to the present invention, wherein an inner connection portion and an external connection portion are provided on one surface. The other surface has a semiconductor chip mounting surface via an adhesive layer, and an opening is provided in the semiconductor chip supporting substrate so as to correspond to a pad position of the semiconductor chip, and an opening provided in the adhesive layer Is larger than an opening provided in the semiconductor chip supporting substrate.

【００１７】上記本発明の半導体チップ支持基板におい
て、半導体チップを搭載するための凹部が設けられてい
る場合には、前記一方の面に形成された開口部を略中心
とする凹部をさらに形成するものとする。In the above-mentioned semiconductor chip supporting substrate of the present invention, when a concave portion for mounting a semiconductor chip is provided, a concave portion having a center substantially at the opening formed on the one surface is further formed. Shall be.

【００１８】[0018]

【発明の実施の形態】本発明で使用する半導体チップ
は、半導体であるシリコン等の小片上に薄膜によりトラ
ンジスタ、ダイオード、抵抗、コンデンサ等の多数の回
路素子、すなわち集積回路が形成されたものである。半
導体チップ表面には、信号の入出力や電源を外部から供
給するために半導体チップのパッドが複数形成されてい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor chip used in the present invention is a semiconductor chip in which a number of circuit elements such as transistors, diodes, resistors, capacitors, etc., that is, integrated circuits are formed on a small piece of silicon as a semiconductor by thin films. is there. A plurality of pads of the semiconductor chip are formed on the surface of the semiconductor chip in order to input / output signals and supply power from outside.

【００１９】半導体チップのパッドの配置は、半導体チ
ップの各辺周辺のうち一辺以上に配列されているペリフ
ェラルパッドタイプ、マトリックスの一部に配置されて
いるエリアパッドタイプ、チップのセンター付近の数列
に配置されているセンターパッドタイプのうち、センタ
ーパッドタイプを主な対象としている。The arrangement of the pads of the semiconductor chip includes a peripheral pad type arranged on one or more sides of each side of the semiconductor chip, an area pad type arranged on a part of the matrix, and several rows near the center of the chip. The center pad type is mainly targeted among the arranged center pad types.

【００２０】本発明の半導体チップ支持基板は、絶縁基
材層と配線層の多層構造体及び配線層間を電気的に接続
するバイアホール等から構成される配線層が一層以上の
多層基板から構成される。The semiconductor chip supporting substrate of the present invention comprises a multilayer substrate having one or more wiring layers comprising a multilayer structure of an insulating base material layer and a wiring layer and via holes for electrically connecting the wiring layers. You.

【００２１】絶縁基材層の構成としては、樹脂単体、ガ
ラスクロスと樹脂の複合体、有機または無機フィラーと
樹脂の複合体、セラミックス単体などが用いられる。As the constitution of the insulating base material layer, a resin simple substance, a composite of glass cloth and resin, a composite of organic or inorganic filler and resin, a ceramic simple substance and the like are used.

【００２２】樹脂材料としては、エポキシ樹脂、メラミ
ン樹脂、尿素樹脂、アクリル樹脂、フェノール樹脂、ポ
リイミド樹脂、テフロン樹脂、ポリエチレン樹脂、ポリ
エステル樹脂、ポリアミド樹脂、シリコーン樹脂等が用
いられる。As the resin material, epoxy resin, melamine resin, urea resin, acrylic resin, phenol resin, polyimide resin, Teflon resin, polyethylene resin, polyester resin, polyamide resin, silicone resin and the like are used.

【００２３】有機フィラーとしては、エポキシ樹脂、メ
ラミン樹脂、尿素樹脂、アクリル樹脂、フェノール樹
脂、ポリイミド樹脂、テフロン樹脂、ポリエチレン樹
脂、ポリエステル樹脂、ポリアミド樹脂、シリコーン樹
脂等の樹脂を使用する溶剤に不溶となるまで高分子化し
微粒子化したタイプあるいは、架橋し微粒子化したタイ
プのフィラーである。The organic filler is insoluble in solvents using resins such as epoxy resin, melamine resin, urea resin, acrylic resin, phenol resin, polyimide resin, Teflon resin, polyethylene resin, polyester resin, polyamide resin and silicone resin. It is a type of filler that has been polymerized and made into fine particles to the extent possible, or a type that has been crosslinked and made into fine particles.

【００２４】無機フィラーとしては、アルミナ、シリ
カ、マグネシア、フェライトなどの金属酸化物の微粒
子、あるいはタルク、マイカ、カオリン、ゼオライトな
どの珪酸塩類、硫酸バリウム、炭酸カルシウムなどの微
粒子が使用される。As the inorganic filler, fine particles of metal oxides such as alumina, silica, magnesia and ferrite, or fine particles such as silicates such as talc, mica, kaolin and zeolite, barium sulfate and calcium carbonate are used.

【００２５】この中で、ガラスクロス材にエポキシ樹脂
等を含浸してなるガラスエポキシ材を用いることが特に
製造工程における剛性及び信頼性等の観点から望まし
い。Among them, it is desirable to use a glass epoxy material obtained by impregnating a glass cloth material with an epoxy resin or the like, particularly from the viewpoint of rigidity and reliability in the manufacturing process.

【００２６】半導体チップ支持基板の一方の面には接着
材を介して半導体チップが搭載されている。本発明の半
導体チップ支持基板の一方の面（Ｂ面）には半導体チッ
プのパッドと接続する領域であるインナー接続部が設け
られている。また、半導体チップ支持基板の一方の面
（Ｂ面）には、本半導体装置から外部装置に接続する領
域である外部接続部が形成されている。通常、外部接続
部には外部装置との連結のためのはんだ等の金属端子が
設けられる。A semiconductor chip is mounted on one surface of the semiconductor chip supporting substrate via an adhesive. On one surface (B surface) of the semiconductor chip supporting substrate of the present invention, an inner connection portion which is a region connected to a pad of the semiconductor chip is provided. On one surface (B surface) of the semiconductor chip supporting substrate, an external connection portion, which is a region connecting the semiconductor device to an external device, is formed. Usually, a metal terminal such as a solder for connection with an external device is provided in the external connection portion.

【００２７】半導体チップ支持基板を構成する配線材料
は銅、アルミニウム、ニッケル、鉄、クロム、銀等の金
属材料や合金等が用いられる。また、必要に応じて配線
表面にはニッケル、金、錫、はんだなどのめっき等によ
る表面処理が施されている。配線は、エッチング法、ア
ディティブ法、セミアディティブ法、配線転写法等で形
成される。特に、Ｂ面に形成された配線は基材内に埋め
込まれていることが好ましい。As a wiring material constituting the semiconductor chip supporting substrate, a metal material such as copper, aluminum, nickel, iron, chromium, silver, or an alloy is used. Further, the surface of the wiring is subjected to a surface treatment such as plating of nickel, gold, tin, solder, or the like as necessary. The wiring is formed by an etching method, an additive method, a semi-additive method, a wiring transfer method, or the like. In particular, the wiring formed on the surface B is preferably embedded in the base material.

【００２８】接着材は樹脂、または樹脂と有機または無
機フィラーを主成分とした絶縁材料である。樹脂の材質
としては、例えば、エポキシ樹脂、メラミン樹脂、尿素
樹脂、アクリル樹脂、フェノール樹脂、ポリイミド樹
脂、テフロン樹脂、ポリエチレン樹脂、ポリエステル樹
脂、ポリアミド樹脂、シリコーン樹脂等がある。The adhesive is a resin or an insulating material containing a resin and an organic or inorganic filler as main components. Examples of the resin material include an epoxy resin, a melamine resin, a urea resin, an acrylic resin, a phenol resin, a polyimide resin, a Teflon resin, a polyethylene resin, a polyester resin, a polyamide resin, and a silicone resin.

【００２９】有機フィラーとしては、エポキシ樹脂、メ
ラミン樹脂、尿素樹脂、アクリル樹脂、フェノール樹
脂、ポリイミド樹脂、テフロン樹脂、ポリエチレン樹
脂、ポリエステル樹脂、ポリアミド樹脂、シリコーン樹
脂等の樹脂を使用する溶剤に不溶となるまで高分子化し
微粒子化したタイプあるいは、架橋し微粒子化したタイ
プのフィラーである。As the organic filler, epoxy resin, melamine resin, urea resin, acrylic resin, phenol resin, polyimide resin, Teflon resin, polyethylene resin, polyester resin, polyamide resin, and silicone resin are used. It is a type of filler that has been polymerized and made into fine particles to the extent possible, or a type that has been crosslinked and made into fine particles.

【００３０】無機フィラーとしては、アルミナ、シリ
カ、マグネシア、フェライトなどの金属酸化物の微粒
子、あるいはタルク、マイカ、カオリン、ゼオライトな
どの珪酸塩類、硫酸バリウム、炭酸カルシウムなどの微
粒子を使用する。As the inorganic filler, fine particles of metal oxides such as alumina, silica, magnesia, and ferrite, or silicates such as talc, mica, kaolin, and zeolite, and fine particles such as barium sulfate and calcium carbonate are used.

【００３１】上記フィラーは１種または２種以上を混合
して使用する。また、接着材は必ずしも一層で形成する
必要はなく、必要に応じて異種または同質の材料を２層
以上に形成してもよい。この接着材はエラストマ的性状
を示すものを用いることが好ましい。The above fillers are used alone or in combination of two or more. Further, the adhesive does not necessarily need to be formed in one layer, and different kinds or materials of the same quality may be formed in two or more layers as needed. It is preferable to use an adhesive having an elastomeric property.

【００３２】本発明の接着材及び半導体チップ支持基板
には、開口部がインナー接続部に対応した位置に設けら
れている。対応する位置に設けるとは、半導体チップの
パッドと半導体チップ支持基板のインナーボンディング
端子が、この開口部を介してボンディングワイヤーを用
いて接続可能になる位置に設けることを意味している。In the adhesive and the semiconductor chip supporting substrate of the present invention, openings are provided at positions corresponding to the inner connection portions. Providing at the corresponding position means that the pad of the semiconductor chip and the inner bonding terminal of the semiconductor chip supporting substrate are provided at a position where they can be connected to each other by using a bonding wire through the opening.

【００３３】好ましくは、インナー接続部は接着材層に
設けられた開口部より水平方向外側に配置する。これ
は、ワイヤボンディングする際に接着材の開口部がある
とボンディグミスが発生する可能性があるからである。
これによって、接着材層の開口部の上限が決められる。[0033] Preferably, the inner connecting portion is arranged horizontally outside of the opening provided in the adhesive layer. This is because there is a possibility that bonding errors may occur if there is an opening of the adhesive during wire bonding.
Thereby, the upper limit of the opening of the adhesive layer is determined.

【００３４】本発明による半導体装置では、前記接着材
層に設けられた開口部が前記基板に設けられた開口部に
比べて大きくなるように設計されることを特徴とする。The semiconductor device according to the present invention is characterized in that the opening provided in the adhesive layer is designed to be larger than the opening provided in the substrate.

【００３５】このとき、前記接着材層に設けられた開口
部輪郭から前記基板に設けられた開口部輪郭までの水平
方向距離は、０．０３ｍｍ〜０．５ｍｍの範囲であるこ
とが好ましく、特に０．１ｍｍ〜０．３ｍｍの範囲が好
ましい。At this time, the horizontal distance from the contour of the opening provided in the adhesive layer to the contour of the opening provided in the substrate is preferably in the range of 0.03 mm to 0.5 mm. A range of 0.1 mm to 0.3 mm is preferred.

【００３６】ボンディングワイヤーは、材質としては、
導電材料であり、例えば、金、銅線、アルミ線、それら
の樹脂被覆金属線等がある。ボンディングワイヤーの形
態として、独立したワイヤーであることが望ましいが、
チップ搭載基板のインナーボンディング端子を基板の開
口部まで延長したリードも含んでいる。The material of the bonding wire is as follows:
A conductive material such as gold, copper wire, aluminum wire, or a resin-coated metal wire thereof. As a form of the bonding wire, it is desirable to be an independent wire,
It also includes a lead in which the inner bonding terminal of the chip mounting substrate is extended to the opening of the substrate.

【００３７】封止材は樹脂単体または樹脂と有機または
無機フィラーを主成分とした絶縁材料である。樹脂の材
質としては、例えば、エポキシ樹脂、メラミン樹脂、尿
素樹脂、アクリル樹脂、フェノール樹脂、ポリイミド樹
脂、テフロン樹脂、ポリエチレン樹脂、ポリエステル樹
脂、ポリアミド樹脂等がある。The sealing material is a resin alone or an insulating material containing a resin and an organic or inorganic filler as main components. Examples of the resin material include an epoxy resin, a melamine resin, a urea resin, an acrylic resin, a phenol resin, a polyimide resin, a Teflon resin, a polyethylene resin, a polyester resin, and a polyamide resin.

【００３８】有機フィラーとしては、エポキシ樹脂、メ
ラミン樹脂、尿素樹脂、アクリル樹脂、フェノール樹
脂、ポリイミド樹脂、テフロン樹脂、ポリエチレン樹
脂、ポリエステル樹脂、ポリアミド樹脂等の樹脂を使用
する溶剤に不溶となるまで高分子化し微粒子化したタイ
プあるいは、架橋し微粒子化したタイプのフィラーが用
いられる。As the organic filler, an epoxy resin, a melamine resin, a urea resin, an acrylic resin, a phenol resin, a polyimide resin, a Teflon resin, a polyethylene resin, a polyester resin, a polyamide resin or the like is used until the organic filler becomes insoluble in a solvent. A filler of molecular type and fine particle or a type of cross-linked fine particle type is used.

【００３９】無機フィラーとしては、アルミナ、シリ
カ、マグネシア、フェライトなどの金属酸化物の微粒
子、あるいはタルク、マイカ、カオリン、ゼオライトな
どの珪酸塩類、硫酸バリウム、炭酸カルシウムなどの微
粒子を使用する。上記フィラーは１種または２種以上を
混合して使用する。As the inorganic filler, fine particles of a metal oxide such as alumina, silica, magnesia, and ferrite, or silicates such as talc, mica, kaolin, and zeolite, and fine particles such as barium sulfate and calcium carbonate are used. The filler is used alone or in combination of two or more.

【００４０】封止材の形成方式は規定しないが、液状の
樹脂を必要領域に塗布し、その後硬化または溶剤等の揮
発等により固体状態にするポッティング法という方式と
本発明の組合せが良く、真空雰囲気で充填する真空差圧
印刷法と本発明の組合せが最も好適である。Although the method of forming the sealing material is not specified, a combination of the method of the present invention with a method of applying a liquid resin to a required area and then setting the liquid resin into a solid state by curing or volatilizing a solvent or the like is preferable, and The combination of the present invention with a vacuum differential pressure printing method filling with an atmosphere is most preferred.

【００４１】真空差圧印刷法とは、複雑な内部構造を有
する印刷部分に気泡が残らないように印刷樹脂を充填す
るために考案された方法であり、具体的には特開平１１
−４０５９０号公報に開示された方法がある。The vacuum differential pressure printing method is a method devised to fill a printing resin having a complicated internal structure with a printing resin so as not to leave air bubbles.
There is a method disclosed in JP-A-40590.

【００４２】本方法においては印刷部位全体、即ち印刷
装置の一部分又は全部、印刷マスク、液状樹脂封止材及
び被印刷物を真空容器の中に設置し、まず真空容器を高
真空にして１回目の印刷を行う。この状態では印刷部の
細部には樹脂が充填されにくい。In the present method, the entire printing portion, that is, a part or the whole of the printing apparatus, the printing mask, the liquid resin sealing material and the printing material are placed in a vacuum container. Perform printing. In this state, it is difficult for the details of the printing section to be filled with the resin.

【００４３】そこで、次に真空容器を中真空状態にする
と１回目の印刷で樹脂が充填されなかった高真空の空洞
部分が中真空状態でつぶされ、空洞がほとんど無くな
り、同時に空洞部に充填された樹脂分だけ樹脂表面に窪
みが発生する。その状態で中真空のまま２回目の印刷を
行い、樹脂表面の窪みを埋めた後、大気圧に戻し被印刷
物を取り出す。Then, when the vacuum container is then brought into the medium vacuum state, the high vacuum cavity portion, which was not filled with resin in the first printing, is crushed in the medium vacuum state, and the cavity almost disappears, and at the same time, the cavity portion is filled. Depression is generated on the resin surface by the amount of the resin. In this state, the second printing is performed while maintaining the medium vacuum, and after filling the depressions on the resin surface, the pressure is returned to the atmospheric pressure, and the printing object is taken out.

【００４４】封止材は開口部内に充填されることが好ま
しく、少なくとも半導体チップのパッド部周辺に加え
て、ボンディングワイヤー周辺、インナーボンディング
部周辺等にも配置することがさらに好ましい。It is preferable that the sealing material is filled in the opening, and it is more preferable that the sealing material is disposed around the bonding wire, the inner bonding portion, etc. in addition to at least the periphery of the pad of the semiconductor chip.

【００４５】本発明の第一の実施の形態を図１を用いて
説明する。図１に本実施形態における半導体装置の断面
図を示す。The first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a sectional view of the semiconductor device according to the present embodiment.

【００４６】本実施形態の半導体装置において、配線基
板２の一方の面（Ａ面）９ａに接着材５を介して半導体
チップ３が半導体チップのパッド４を基板側にして搭載
されている。配線基板２の他方の面（Ｂ面）９ｂには、
外部接続部７ｃ及びインナー接続部７ａが設けられてい
る。In the semiconductor device of the present embodiment, the semiconductor chip 3 is mounted on one surface (A surface) 9a of the wiring substrate 2 with the pad 4 of the semiconductor chip facing the substrate via the adhesive 5. On the other surface (surface B) 9b of the wiring board 2,
An external connection part 7c and an inner connection part 7a are provided.

【００４７】半導体チップ支持基板１及び接着材５には
開口部６及び開口部１４が設けられていて、半導体チッ
プ支持基板１の開口部６及び接着材層の開口部１４を介
して、半導体チップのパッド４とインナー接続部７ａが
ボンディングワイヤ１１によって接続されている。外部
接続部７cには、はんだボール等の外部接続端子１０が
設けられている。必要に応じて、半導体チップ支持基板
１のＢ面９ｂに封止ダム１３が設けられる。なお、図中
の８はマスク樹脂、１２は封止材である。An opening 6 and an opening 14 are provided in the semiconductor chip supporting substrate 1 and the adhesive 5, and the semiconductor chip is opened through the opening 6 of the semiconductor chip supporting substrate 1 and the opening 14 of the adhesive layer. The pad 4 and the inner connection portion 7a are connected by a bonding wire 11. An external connection terminal 10 such as a solder ball is provided in the external connection portion 7c. If necessary, a sealing dam 13 is provided on the B surface 9b of the semiconductor chip supporting substrate 1. In the drawing, 8 is a mask resin, and 12 is a sealing material.

【００４８】本発明においては、図１に示すように、接
着材層の開口部１４が半導体チップ支持基板の開口部６
より大きい構成になっていることが特徴である。In the present invention, as shown in FIG. 1, the opening 14 of the adhesive layer is formed in the opening 6 of the semiconductor chip supporting substrate.
The feature is that it has a larger configuration.

【００４９】本実施形態によれば、開口部６および１４
に封止材１２が充填されている半導体装置において、接
着材５の層に設けられた開口部１４が半導体チップ支持
基板に設けられた開口部６に比べて大きくなる構造にす
ることによって、接着材５の吸湿量を少なくし、半導体
チップ３と封止材１２との接着力をより効果的に利用す
ることが可能となるため、接着材５と封止材１２とのは
く離を未然に防ぎ、信頼性の高い小型半導体装置を実現
することができる。According to the present embodiment, the openings 6 and 14
In the semiconductor device in which the sealing material 12 is filled, the opening 14 provided in the layer of the adhesive 5 is made larger than the opening 6 provided in the semiconductor chip supporting substrate, so that the bonding is performed. Since the amount of moisture absorbed by the material 5 can be reduced and the adhesive force between the semiconductor chip 3 and the sealing material 12 can be used more effectively, peeling of the bonding material 5 from the sealing material 12 can be prevented. Thus, a highly reliable small semiconductor device can be realized.

【００５０】さらに、本実施形態によれば、真空差圧印
刷法により封止材を充填するため、ボイドの発生を起こ
すことなく開口部分をより小さくすることが可能とな
り、全体として封止材の使用量を減らすことが可能にな
るという有利な効果を奏する。Further, according to the present embodiment, since the sealing material is filled by the vacuum differential pressure printing method, the opening can be made smaller without generating voids. There is an advantageous effect that the amount of use can be reduced.

【００５１】本発明の第二の実施の形態を図２を用いて
説明する。図２に本発明の第二の実施の形態の半導体装
置の断面図を示す。A second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

【００５２】本第二の実施形態の半導体装置において
も、上述した第一の実施形態と同様に接着材層の開口部
１４が半導体チップ支持基板１の開口部６よりも大きい
という特徴的構成を備えている。The semiconductor device of the second embodiment also has a characteristic configuration in which the opening 14 of the adhesive layer is larger than the opening 6 of the semiconductor chip supporting substrate 1 as in the first embodiment described above. Have.

【００５３】本実施形態において上記第一の実施形態と
異なる点は、本実施形態の半導体チップ支持基板１のＢ
面９ｂには配線７が埋め込まれた凹部が形成され、該凹
部内にインナー接続部７ａが形成され、マスク樹脂８は
凹部内の周縁部付近にも設けられている、という点であ
る。This embodiment is different from the first embodiment in that the semiconductor chip supporting substrate 1 of this embodiment has a B
The surface 9b is formed with a concave portion in which the wiring 7 is embedded, the inner connecting portion 7a is formed in the concave portion, and the mask resin 8 is also provided near the periphery of the concave portion.

【００５４】なお、本実施形態のようにインナー接続部
が凹部内に設けられていても、配線７が埋め込まれてい
ても、マスク樹脂８が凹部内周縁部に設けれていてもそ
れぞれ、本実施形態による効果には差がない。It should be noted that whether the inner connection portion is provided in the concave portion as in the present embodiment, the wiring 7 is embedded, or the mask resin 8 is provided in the inner peripheral portion of the concave portion, There is no difference in the effect according to the embodiment.

【００５５】さらに、本実施形態によれば、半導体チッ
プ支持基板１の一方の面９ｂに凹部が設けられているた
め、真空差圧印刷法により封止材を充填する際に、開口
部６の上方に盛り上げる封止材を増量することが容易に
なるという有利な効果を奏する。Further, according to the present embodiment, since the concave portion is provided on one surface 9b of the semiconductor chip supporting substrate 1, when the sealing material is filled by the vacuum differential pressure printing method, the opening 6 is formed. There is an advantageous effect that it is easy to increase the amount of the sealing material raised upward.

【００５６】本発明の第三の実施の形態を図３を用いて
説明する。図３に本発明の第三の実施の形態の半導体装
置の断面図を示す。A third embodiment of the present invention will be described with reference to FIG. FIG. 3 is a sectional view of a semiconductor device according to the third embodiment of the present invention.

【００５７】本実施形態による半導体装置についても、
その基本的構成は上述した第一の実施形態と同様である
が、以下の点が異なる。すなわち、半導体チップ支持基
板１の開口部６ａ、６ｂ及び接着材５の開口部１４ａ、
１４ｂが複数個設けられている、という点である。この
場合、接着材５の開口部１４ａ、１４ｂはそれぞれ対応
する半導体チップ支持基板１の開口部６ａ、６ｂに比べ
て大きいという、本発明の特徴的構成になっている。The semiconductor device according to the present embodiment also
The basic configuration is the same as that of the first embodiment described above, except for the following points. That is, the openings 6 a and 6 b of the semiconductor chip support substrate 1 and the openings 14 a of the adhesive 5,
14b is provided in plurality. In this case, the openings 14a and 14b of the adhesive 5 are larger than the corresponding openings 6a and 6b of the semiconductor chip supporting substrate 1, respectively.

【００５８】本実施形態では、複数の開口部１４の穴あ
けにはレーザ等の様々な手法を用いることができるが、
特にレーザ穴あけを用いることにより、半導体装置の高
密度化に対応できるという効果がある。In the present embodiment, various methods such as laser can be used for drilling the plurality of openings 14.
In particular, by using laser drilling, there is an effect that it is possible to cope with high density of a semiconductor device.

【００５９】[0059]

【実施例】本発明の詳細な実施例を図４〜１５を用いて
説明する。図４〜１５は、上記図３に示した構造の半導
体装置の製造方法の一例を説明する断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A detailed embodiment of the present invention will be described with reference to FIGS. 4 to 15 are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device having the structure shown in FIG.

【００６０】最初、図４に示すように、銅箔１６ａ（厚
み：１８μｍ）／ガラスエポキシ材１７（厚み：０．２
ｍｍ）／銅箔１６ｂ（厚み：１８μｍ）の三層構成から
なる周知の銅張り積層板１５（日立化成工業株式会社
製、商品名：ＭＣＬ−Ｅ６７９）を用意する。First, as shown in FIG. 4, copper foil 16a (thickness: 18 μm) / glass epoxy material 17 (thickness: 0.2
mm) / copper foil 16b (thickness: 18 μm), a known copper-clad laminate 15 (manufactured by Hitachi Chemical Co., Ltd., trade name: MCL-E679) having a three-layer configuration.

【００６１】通常のフォトリソ法で片面（Ｂ面）２５ｂ
に配線１８を形成し、他面の銅箔はエッチングにより除
去した（図５）。配線の形成では、レジストとして感光
性のエッチング用ドライフィルムレジスト（日立化成工
業株式会社製、商品名：フォテックＨＮ６４０）を用い
た。One side (B side) 25b by the ordinary photolithography method
Was formed, and the copper foil on the other surface was removed by etching (FIG. 5). In forming the wiring, a photosensitive dry film resist for etching (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN640) was used as the resist.

【００６２】レジストラミネート条件は、ロール圧力
２．０ｋｇｆ／ｃｍ、ロール温度１００°Ｃ、送り速度
１．０ｍ／ｍｉｎとした。露光はオーク株式会社製の平
行露光機（ＥＸＭ−１６００−Ａ）を使用し、露光量８
０ｍＪ／ｃｍ2で行った。現像は、炭酸ナトリウム水溶
液（液濃度：１．０ｗｔ％、液温：２８°Ｃ）を使用
し、スプレー圧１．５ｋｇｆ／ｃｍ2で行った。エッチ
ング液としてアルカリエッチング液（メルテックス社
製、商品名：Ａプロセス）を用いた。液温度４０°Ｃ、
スプレー圧力を１．２ｋｇｆ／ｃｍ2で行った。The conditions for resist lamination were a roll pressure of 2.0 kgf / cm, a roll temperature of 100 ° C., and a feed rate of 1.0 m / min. Exposure was performed using a parallel exposure machine (EXM-1600-A) manufactured by Oak Co., Ltd.
The test was performed at 0 mJ / cm 2 . The development was performed using a sodium carbonate aqueous solution (liquid concentration: 1.0 wt%, liquid temperature: 28 ° C.) at a spray pressure of 1.5 kgf / cm 2 . As an etching solution, an alkali etching solution (trade name: A process, manufactured by Meltex Co., Ltd.) was used. Liquid temperature 40 ° C,
The spray pressure was 1.2 kgf / cm 2 .

【００６３】次に、配線板に所定の開口部２４ａ、２４
ｂをルータ加工で形成した（図６）。なお、本例では開
口部を複数個に分割して設けた例を示したが、分割せず
に単一の開口部を設ける場合についても、本実施例の製
造方法と同様の方法を用いることができる。さらに、開
口部を設ける工程は必ずしもこの段階に限定されるもの
ではなく、前後の工程で設ける構成としてもよい。Next, predetermined openings 24a, 24a are formed in the wiring board.
b was formed by router processing (FIG. 6). Note that, in this example, an example in which the opening is divided into a plurality of portions is provided. However, even when a single opening is provided without division, a method similar to the manufacturing method of the present embodiment is used. Can be. Further, the step of providing the opening is not necessarily limited to this stage, and the opening may be provided in the preceding and following steps.

【００６４】次に、外部接続部１８ｃ及びインナー接続
部１８ａを開口させるように、ソルダーレジスト１９を
形成する。液状の感光性ソルダーレジスト（日立化成工
業株式会社製、ＰＳＲ−７０００）を印刷法で必要領域
部に塗布し、フォトリソ法でパターン形成した。印刷マ
スクはシルクスクリーンマスクを用い、レジスト厚み
（硬化後）を２０μｍとなるように形成し、脱泡後、乾
燥（温度８５°Ｃ、時間２５分）し、露光した。露光
は、平行露光機を用い、露光量は５００ｍＪ／ｃｍ2と
した。現像では、現像液に１ｗｔ％炭酸ナトリウム水溶
液を用い、液温度３０°Ｃ、現像時間９０秒、スプレー
圧２ｋｇｆ／ｃｍ2とした。現像後、後加熱（温度１５
０°Ｃ、１時間）を行った。Next, a solder resist 19 is formed so as to open the external connection portion 18c and the inner connection portion 18a. A liquid photosensitive solder resist (manufactured by Hitachi Chemical Co., Ltd., PSR-7000) was applied to a required area by a printing method, and a pattern was formed by a photolithographic method. The print mask was formed using a silk screen mask so that the resist thickness (after curing) was 20 μm, and after defoaming, drying (temperature 85 ° C., time 25 minutes) and exposure. For exposure, a parallel exposure machine was used, and the exposure amount was 500 mJ / cm 2 . In the development, a 1 wt% sodium carbonate aqueous solution was used as a developer, the liquid temperature was 30 ° C., the development time was 90 seconds, and the spray pressure was 2 kgf / cm 2 . After development, post-heating (temperature 15
(0 ° C., 1 hour).

【００６５】本例では、Ｂ面２５ｂのみにソルターレジ
ストを形成した例を示したが、Ａ面２５ａにもソルター
レジスト等の樹脂層を設けてもよい。次に露出している
インナー接続部及び外部接続部にニッケルめっき（厚
さ：５μｍ）（不図示）及び金めっき（厚さ：０．７μ
ｍ）（不図示）を施し、半導体チップ支持基板２７を得
た（図７）。In this embodiment, an example is shown in which a salter resist is formed only on the B side 25b, but a resin layer such as a sorter resist may be provided on the A side 25a. Next, nickel plating (thickness: 5 μm) (not shown) and gold plating (thickness: 0.7 μm) are applied to the exposed inner connection portion and external connection portion.
m) (not shown) to obtain a semiconductor chip supporting substrate 27 (FIG. 7).

【００６６】次に、接着フィルム（日立化成工業株式会
社製、商品名：ＤＦ−３３５）を打抜き加工で所定の形
状に加工した。この打抜き加工した接着フィルム２１を
半導体チップ支持基板２７のＡ面２５ａに圧着した（図
８）。接着条件は、温度１６０°Ｃ、時間５秒、圧力３
ｋｇｆ／ｃｍ2とした。Next, an adhesive film (trade name: DF-335, manufactured by Hitachi Chemical Co., Ltd.) was processed into a predetermined shape by punching. The punched adhesive film 21 was pressed against the A surface 25a of the semiconductor chip supporting substrate 27 (FIG. 8). The bonding conditions were as follows: temperature 160 ° C., time 5 seconds, pressure 3
kgf / cm 2 .

【００６７】次に、半導体チップ３０を所定の位置に接
着する（図９）。接着条件は、温度２２０°Ｃ、時間５
秒、圧力３００ｇｆ／ｃｍ2とした。このとき、接着材
の開口部２６ａ、２６ｂの輪郭部分から半導体チップ支
持基板の開口部２４ａ、２４ｂの輪郭部分までの横方向
距離は、１００μｍとなった。Next, the semiconductor chip 30 is bonded to a predetermined position (FIG. 9). The bonding conditions were as follows: temperature 220 ° C., time 5
Second, the pressure was 300 gf / cm 2 . At this time, the lateral distance from the outline of the openings 26a and 26b of the adhesive to the outline of the openings 24a and 24b of the semiconductor chip supporting substrate was 100 μm.

【００６８】次に、市販のワイヤーボンディング装置
（新川株式会社製、装置名：ＵＴＣ−２３０ＢＩ）によ
り、半導体チップのパッド部２８と対応するインナー接
続部１８ａを金線（２５μｍ径）２２を介して電気的に
接続した（図１０）。Next, the inner connection portion 18a corresponding to the pad portion 28 of the semiconductor chip is connected via a gold wire (25 μm diameter) 22 with a commercially available wire bonding device (manufactured by Shinkawa Corporation, device name: UTC-230BI). It was electrically connected (FIG. 10).

【００６９】次に、半導体チップのパッド部２８、イン
ナー接続部１８ａ及び金線２２等の周辺を防湿及び保護
する目的で半導体用ポッティング樹脂（日立化成工業株
式会社製、ＨＩＲ３０００）で封止した。封止は、東レ
エンジニアリング株式会社製の真空差圧印刷装置（型
番：ＶＤ−１０００）を用い、真空差圧印刷法を用い
た。Next, the semiconductor chip potting resin (HIR3000, manufactured by Hitachi Chemical Co., Ltd.) was sealed with a potting resin for the purpose of preventing and protecting the periphery of the pad portion 28, the inner connection portion 18a and the gold wire 22 of the semiconductor chip. Sealing was performed using a vacuum differential pressure printing method using a vacuum differential pressure printing device (model number: VD-1000) manufactured by Toray Engineering Co., Ltd.

【００７０】真空差圧印刷装置ＶＤ−１０００の真空容
器内に図１１の被封止品、図１１の２３に示すメタル印
刷マスク及び封止樹脂ＨＩＲ−３０００をセットし、５
Ｔｏｒｒに減圧後１回目の印刷を行った。この状態での
断面観察の結果、図１２の２６ａ、２６ｂの周辺に空洞
部が見られた。The sealed product of FIG. 11, the metal print mask and the sealing resin HIR-3000 shown in FIG.
The first printing was performed after decompression in Torr. As a result of cross-sectional observation in this state, a cavity was found around 26a and 26b in FIG.

【００７１】次に真空容器を１５０Ｔｏｒｒにして断面
観察したところ、図１３に示すように空洞部は樹脂で埋
まり、３１の印刷した樹脂の表面に窪みが発生した。１
５０Ｔｏｒｒのまま２回目の印刷を行い窪みを埋めた
後、大気圧に戻し、メタル印刷マスクを取外し、被印刷
品を真空差圧印刷装置から取りだし、１２０°Ｃ、１８
０°Ｃの乾燥炉で各１時間加熱した。Next, when the cross section of the vacuum vessel was observed at 150 Torr, as shown in FIG. 13, the cavity was filled with the resin, and a dent was formed on the surface of the resin printed with 31. 1
After printing the second time at 50 Torr to fill the depressions, the pressure was returned to atmospheric pressure, the metal print mask was removed, and the article to be printed was taken out of the vacuum differential pressure printing apparatus at 120 ° C, 18 ° C.
Each was heated for 1 hour in a drying oven at 0 ° C.

【００７２】乾燥後の製品の断面観察結果は、図１５に
示すように２６ａ、２６ｂを含めて封止内部に空洞、気
泡等が見られず、又、封止樹脂の表面もほぼ平滑で良好
な封止状態が得られていた。As shown in FIG. 15, the cross section of the dried product shows no voids or bubbles inside the sealing, including 26a and 26b, and the surface of the sealing resin is almost smooth and good. A good sealing state was obtained.

【００７３】次に外部接続部１８ｃにフラックスをディ
スペンス塗布し、はんだボールを搭載し、窒素雰囲気炉
でボールをリフローさせて外部接続端子２９を形成した
（図１６）。Next, a flux was applied to the external connection portion 18c by dispensing, a solder ball was mounted, and the ball was reflowed in a nitrogen atmosphere furnace to form an external connection terminal 29 (FIG. 16).

【００７４】本実施例では打抜き加工した接着材単体フ
ィルムを用いたが、他に、接着材のワニスをＰＥＴ（ポ
リエチレンテレフタレート）フィルム、ＯＰＰ（延伸ポ
リプロピレン）フィルム、ＴＰＸ（メチルペンテンコポ
リマ）フィルム等の離型性シート上に塗布し、フィルム
化した２層構成のものを用意し、打抜き加工し、チップ
搭載基板に接着し、離型性シートをはく離する方法でも
よい。また、他に接着材のワニスを離型性シートの所定
パターンに印刷により形成し、半導体チップ支持基板に
接着し、離型性シートをはく離する方法でもよい。接着
材のワニスを直接に半導体チップ支持基板に印刷し、半
硬化させる等の方法を用いてもよい。In this embodiment, a single-piece adhesive material film that has been punched is used. Alternatively, a varnish of the adhesive material may be a PET (polyethylene terephthalate) film, an OPP (stretched polypropylene) film, a TPX (methylpentene polymer) film, or the like. A method of preparing a two-layered film that is applied on a release sheet and formed into a film, punched, adhered to a chip mounting substrate, and peeled off the release sheet may be used. Alternatively, a method of forming a varnish of an adhesive on a predetermined pattern of a release sheet by printing, bonding the varnish to a semiconductor chip supporting substrate, and releasing the release sheet may be used. A method of printing a varnish of the adhesive directly on the semiconductor chip supporting substrate and semi-curing it may be used.

【００７５】これらの方法を用いることによって、半導
体チップ支持基板の開口部に対して精度よく、接着材の
開口部を設けることができる。By using these methods, it is possible to accurately provide an opening for the adhesive with respect to the opening for the semiconductor chip supporting substrate.

【００７６】また、本実施例の説明図では個々のピース
の断面図で説明したが、これらの工程は最終的に複数の
ピースを含む一連の半導体チップ支持基板を用意し、最
終工程または途中工程で分離することも可能である。分
離には、打抜き加工、ウェハー切断に使用されるダイサ
ー、ルータ加工、レーザ加工等が用いられる。In the illustration of this embodiment, the sectional views of the individual pieces have been described. However, in these steps, a series of semiconductor chip supporting substrates including a plurality of pieces are finally prepared, and the final step or the intermediate step is performed. It is also possible to separate them. For separation, a punching process, a dicer used for wafer cutting, a router process, a laser process, or the like is used.

【００７７】本発明の半導体装置においては、図１８に
示すように、センターパッドを有する半導体チップを図
のように分離してペリフェラルパッドタイプの半導体装
置とすることもできる。In the semiconductor device of the present invention, as shown in FIG. 18, a semiconductor chip having a center pad can be separated as shown in the figure to form a peripheral pad type semiconductor device.

【００７８】本実施例に示した方法で半導体チップと外
部接続端子間の電気接続チェック可能な半導体装置を導
通検査正常品３０ピース作製し、吸湿リフロー試験を実
施した。吸湿（温度８５°Ｃ、湿度８５％ＲＨ、１６８
時間）後、赤外線リフロー（最高温度２４５°Ｃ）によ
り導通異常の発生有無をチェックした。３０ピース全て
の導通を確認し、外観等にも異常を認めなかった。According to the method shown in this embodiment, 30 pieces of semiconductor devices which can check the electrical connection between the semiconductor chip and the external connection terminals were manufactured as normal conduction test pieces and subjected to a moisture absorption reflow test. Moisture absorption (temperature 85 ° C, humidity 85% RH, 168
After this time, the presence or absence of a conduction abnormality was checked by infrared reflow (at a maximum temperature of 245 ° C.). The conduction of all 30 pieces was confirmed, and no abnormality was observed in the appearance and the like.

【００７９】比較例として、実施例と同じ材料、工程を
用いて接着材の開口部が半導体チップ支持基板の開口部
に比べて小さな半導体装置を３０ピース作製した。ここ
で、両者の開口部の輪郭間の距離は約５０μｍとなるよ
うにした。これについても実施例と同時に試験を実施し
たが、３０ピース中３０ピースに断線不良が発生した。As a comparative example, using the same material and process as in the example, a 30-piece semiconductor device was manufactured in which the opening of the adhesive was smaller than the opening of the semiconductor chip supporting substrate. Here, the distance between the contours of both openings was set to be about 50 μm. This was also tested at the same time as the example, but a disconnection failure occurred in 30 pieces out of 30 pieces.

【００８０】[0080]

【発明の効果】本発明によれば、半導体チップ支持基板
の一方の面（Ａ面）に接着材を介してセンターパッドを
有す半導体チップが搭載されており、前記半導体チップ
支持基板及び前記接着材の前記半導体チップのセンター
パッド位置に対応する個所に少なくとも１個以上の開口
部が設けられており、前記半導体チップ支持基板の他方
の面（Ｂ面）にインナー接続部及び外部接続部が設けら
れており、前記半導体チップのパッドは前記開口部を経
由するボンディングリードによりインナー接続部と接続
されており、前記開口部に封止材が充填されている半導
体装置において、前記接着材に設けられた開口部が前記
基板に設けられた開口部に比べて大きくなるような構造
にすることによって、信頼性の高い小型半導体装置が実
現する。According to the present invention, a semiconductor chip having a center pad is mounted on one surface (A surface) of a semiconductor chip supporting substrate via an adhesive, and the semiconductor chip supporting substrate and the adhesive At least one opening is provided at a position of the material corresponding to the center pad position of the semiconductor chip, and an inner connection portion and an external connection portion are provided on the other surface (B surface) of the semiconductor chip supporting substrate. The pad of the semiconductor chip is connected to the inner connecting portion by a bonding lead passing through the opening, and in the semiconductor device in which the opening is filled with a sealing material, the pad is provided on the adhesive. By employing a structure in which the opening is larger than the opening provided in the substrate, a highly reliable small semiconductor device is realized.

【００８１】さらに、本発明の半導体装置の封止樹脂形
成工程で真空差圧印刷法を用いることにより、ボンディ
ングワイヤー周囲のみならず、接着材の開口部周囲の半
導体チップと半導体チップ支持基板との間隙をボイドな
く封止樹脂で充填させることができる。Further, by using the vacuum differential pressure printing method in the encapsulating resin forming step of the semiconductor device of the present invention, not only the periphery of the bonding wire but also the semiconductor chip around the opening of the adhesive and the semiconductor chip supporting substrate can be formed. The gap can be filled with the sealing resin without voids.

【００８２】さらに、本発明の半導体装置の製造方法に
よれば、多数の半導体装置を一括して封止できるために
生産性が向上する。Further, according to the method of manufacturing a semiconductor device of the present invention, since a large number of semiconductor devices can be sealed at once, the productivity is improved.

【００８３】さらに、本発明によれば、真空差圧印刷法
を用いて封止樹脂を形成する際、開口部を複数個に分割
する等により、開口面積を小さく設計すると封止材内部
に残留するボイドの低減に有効であり、吸湿リフローや
プレッシャークッカー試験等の不良が低減する。Further, according to the present invention, when the sealing resin is formed by the vacuum differential pressure printing method, if the opening area is designed to be small by dividing the opening into a plurality of parts, the sealing resin remains in the sealing material. This is effective for reducing voids that occur, and reduces defects such as moisture absorption reflow and pressure cooker tests.

【００８４】接着材の印刷による形成法を用いることに
よって、本発明の半導体装置の半導体チップ支持基板の
開口部に対して精度よく接着材の開口部を設けることが
でき、信頼性が向上する。By using the forming method by printing the adhesive, the opening of the adhesive can be accurately provided with respect to the opening of the semiconductor chip supporting substrate of the semiconductor device of the present invention, and the reliability is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施形態における半導体装置の
断面構成を示す断面図である。FIG. 1 is a cross-sectional view illustrating a cross-sectional configuration of a semiconductor device according to a first embodiment of the present invention.

【図２】本発明の第２の実施形態における半導体装置の
断面構成を示す断面図である。FIG. 2 is a cross-sectional view illustrating a cross-sectional configuration of a semiconductor device according to a second embodiment of the present invention.

【図３】本発明の第３の実施形態における半導体装置の
断面構成を示す断面図である。FIG. 3 is a cross-sectional view illustrating a cross-sectional configuration of a semiconductor device according to a third embodiment of the present invention.

【図４】本発明による半導体装置の製造工程における断
面構成例を示す断面図である。FIG. 4 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図５】本発明による半導体装置の製造工程における断
面構成例を示す断面図である。FIG. 5 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図６】本発明による半導体装置の製造工程における断
面構成例を示す断面図である。FIG. 6 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図７】本発明による半導体装置の製造工程における断
面構成例を示す断面図である。FIG. 7 is a sectional view showing an example of a sectional configuration in a manufacturing process of the semiconductor device according to the present invention.

【図８】本発明による半導体装置の製造工程における断
面構成例を示す断面図である。FIG. 8 is a sectional view showing an example of a sectional configuration in a manufacturing process of the semiconductor device according to the present invention.

【図９】本発明による半導体装置の製造工程における断
面構成例を示す断面図である。FIG. 9 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図１０】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 10 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図１１】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 11 is a sectional view showing an example of a sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図１２】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 12 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図１３】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 13 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図１４】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 14 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図１５】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 15 is a sectional view showing an example of a sectional configuration in a manufacturing process of the semiconductor device according to the present invention.

【図１６】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 16 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing step of a semiconductor device according to the present invention.

【図１７】従来技術による半導体装置の断面構成例を示
す断面図である。FIG. 17 is a cross-sectional view illustrating an example of a cross-sectional configuration of a semiconductor device according to a conventional technique.

【図１８】本発明の複数のピースを含む一連のチップ搭
載基板を分離してペリフェラルパッドタイプの半導体装
置とする例を示す断面図である。FIG. 18 is a cross-sectional view showing an example in which a series of chip mounting substrates including a plurality of pieces of the present invention are separated into a peripheral pad type semiconductor device.

【符号の説明】[Explanation of symbols]

１…半導体チップ支持基板、２…配線基板、３…半導体
チップ、４…半導体チップのパッド、５…接着材、６…
半導体チップ支持基板の開口部、７…配線、７ａ…イン
ナー接続部、７ｃ…外部接続部、８…マスク樹脂、１０
…外部接続端子、１１…ボンディングワイヤ、１２…封
止材、１３…封止ダム、１４…接着材層の開口部、１５
…銅張り積層板、１６ａ、１６ｂ…銅箔、１７…ガラス
エポキシ材、１８…配線、１８ａ…インナー接続部、１
８ｃ…外部接続部、２２…金線、２３…メタル印刷マス
ク、２６ａ、２６ｂ…接着材層に形成された開口部、２
８…半導体チップのパッド部、２９…外部接続端子、３
０…半導体チップ、３１…印刷した樹脂。DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip support substrate, 2 ... Wiring board, 3 ... Semiconductor chip, 4 ... Semiconductor chip pad, 5 ... Adhesive, 6 ...
Opening of semiconductor chip supporting substrate, 7: wiring, 7a: inner connection, 7c: external connection, 8: mask resin, 10
... external connection terminals, 11 ... bonding wires, 12 ... sealing material, 13 ... sealing dam, 14 ... openings in the adhesive layer, 15
... copper-clad laminate, 16a, 16b ... copper foil, 17 ... glass epoxy material, 18 ... wiring, 18a ... inner connection part, 1
8c: external connection portion, 22: gold wire, 23: metal print mask, 26a, 26b: opening formed in the adhesive layer, 2
8: pad portion of semiconductor chip, 29: external connection terminal, 3
0: semiconductor chip, 31: printed resin.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴木 和久 東京都港区芝浦四丁目９番25号 芝浦スク エアビル 日立化成工業株式会社内 (72)発明者 守田 宏 東京都港区芝浦四丁目９番25号 芝浦スク エアビル 日立化成工業株式会社内 (72)発明者 福富 直樹 東京都港区芝浦四丁目９番25号 芝浦スク エアビル 日立化成工業株式会社内 Ｆターム(参考） 5F044 AA05 JJ03 5F047 AA17 AB01 BA21 BA34 BA35 BA36 BA39 BA54 BB03  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuhisa Suzuki 4-9-1, Shibaura, Minato-ku, Tokyo Shibaura Suku Air Building Inside Hitachi Chemical Co., Ltd. (72) Inventor Hiroshi Morita 4-9-1, Shibaura, Minato-ku, Tokyo No. 25 Shibaura Square Air Building Hitachi Chemical Co., Ltd. (72) Inventor Naoki Fukutomi 4-9-25 Shibaura Minato-ku, Tokyo Shibaura Square Air Building Hitachi Chemical Co., Ltd. F-term (reference) 5F044 AA05 JJ03 5F047 AA17 AB01 BA21 BA34 BA35 BA36 BA39 BA54 BB03

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】半導体チップ支持基板の一方の面にはイン
ナー接続部及び外部接続部が設けられ、他方の面に形成
された接着材を介してセンターパッドを有する半導体チ
ップが搭載された半導体装置において、 前記半導体チップのセンターパッド位置に対応する前記
半導体チップ支持基板及び前記接着材層の位置にそれぞ
れ開口部が形成され、前記開口部を経由するボンディン
グリードにより前記半導体チップのパッドが前記インナ
ー接続部と接続され、前記開口部に封止材が充填されて
いるものであって、 前記接着材層に形成された開口部が前記半導体チップ支
持基板に形成された開口部に比べて大きいことを特徴と
する半導体装置。1. A semiconductor device in which an inner connection portion and an external connection portion are provided on one surface of a semiconductor chip supporting substrate, and a semiconductor chip having a center pad is mounted via an adhesive formed on the other surface. In the above, openings are respectively formed at positions of the semiconductor chip support substrate and the adhesive material layer corresponding to the center pad positions of the semiconductor chip, and the pads of the semiconductor chip are connected to the inner connection by bonding leads passing through the openings. And a sealing material is filled in the opening, wherein the opening formed in the adhesive layer is larger than the opening formed in the semiconductor chip supporting substrate. Characteristic semiconductor device. 【請求項２】前記接着材層に設けられた開口部輪郭と、
それに対応する前記基板に設けられた開口部輪郭との水
平距離が０．０３ｍｍ以上０．５ｍｍ以下であることを
特徴とする請求項１に記載の半導体装置。2. An outline of an opening provided in the adhesive layer,
2. The semiconductor device according to claim 1, wherein a horizontal distance from a corresponding opening contour provided in the substrate is not less than 0.03 mm and not more than 0.5 mm. 【請求項３】前記半導体チップ支持基板の開口部直下に
前記半導体チップのパッドが位置するように、前記半導
体チップは前記半導体チップ支持基板に搭載され、 前記接着材層の開口部は、前記半導体チップ支持基板の
開口部直下領域を少なくとも含み、前記直下領域よりも
大きい面積を備えることを特徴とする請求項１に記載の
半導体装置。3. The semiconductor chip is mounted on the semiconductor chip support substrate such that a pad of the semiconductor chip is located immediately below an opening of the semiconductor chip support substrate, and the opening of the adhesive layer is formed of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein the semiconductor device includes at least a region immediately below the opening of the chip supporting substrate, and has an area larger than the region immediately below the opening. 【請求項４】前記接着材層に設けられた開口部より水平
方向外側に、前記インナー接続部を配置することを特徴
とする請求項１に記載の半導体装置。4. The semiconductor device according to claim 1, wherein the inner connection portion is disposed horizontally outside an opening provided in the adhesive layer. 【請求項５】請求項１乃至４のいずれかに記載の半導体
装置に用いられる半導体チップ支持基板であって、 その一方の面にはインナー接続部及び外部接続部が設け
られ、 他方の面には接着材層を介した半導体チップ搭載面を有
し、 半導体チップ支持基板に開口部が半導体チップのパッド
位置に対応するように設けられ、 前記接着材層に設ける開口部が前記半導体チップ支持基
板に設けられた開口部に比べて大きいことを特徴とする
半導体チップ支持基板。5. A semiconductor chip supporting substrate used in the semiconductor device according to claim 1, wherein one surface is provided with an inner connection portion and an external connection portion, and the other surface is provided with an inner connection portion. Has a semiconductor chip mounting surface via an adhesive layer, an opening is provided in the semiconductor chip supporting substrate so as to correspond to a pad position of the semiconductor chip, and the opening provided in the adhesive layer is the semiconductor chip supporting substrate. A semiconductor chip supporting substrate, which is larger than an opening provided in the semiconductor chip supporting substrate. 【請求項６】半導体チップ支持基板の一方の面にはイン
ナー接続部及び外部接続部が設けられ、他方の面に形成
された接着材を介してセンターパッドを有する半導体チ
ップが搭載された半導体装置の製造方法において、 前記半導体チップ支持基板及び前記接着材層の前記半導
体チップのセンターパッド位置に対応する位置にそれぞ
れ開口部を形成する工程と、 前記開口部を経由するボンディングリードにより前記半
導体チップのパッドを前記インナー接続部と接続する工
程と、 前記開口部に封止材を充填する工程とを備え、 前記接着材層に形成された開口部が前記半導体チップ支
持基板に形成された開口部に比べて大きいことを特徴と
する半導体装置の製造方法。6. A semiconductor device in which an inner connection portion and an external connection portion are provided on one surface of a semiconductor chip supporting substrate, and a semiconductor chip having a center pad is mounted via an adhesive formed on the other surface. Forming a hole in each of the semiconductor chip supporting substrate and the adhesive layer at a position corresponding to a center pad position of the semiconductor chip; and bonding the semiconductor chip by bonding leads passing through the opening. A step of connecting a pad to the inner connection section; and a step of filling the opening with a sealing material, wherein the opening formed in the adhesive layer is formed in the opening formed in the semiconductor chip supporting substrate. A method of manufacturing a semiconductor device, wherein the method is larger than that of a semiconductor device. 【請求項７】前記封止材を充填する工程では、前記封止
材を真空差圧印刷法によって形成することを特徴とする
請求項６に記載の半導体装置の製造方法。7. The method according to claim 6, wherein in the step of filling the sealing material, the sealing material is formed by vacuum differential printing. 【請求項８】半導体チップ支持基板の一方の面にはイン
ナー接続部及び外部接続部が設けられ、他方の面に形成
された接着材を介してセンターパッドを有する半導体チ
ップが搭載された半導体装置において、 前記半導体チップのセンターパッド位置に対応する前記
半導体チップ支持基板及び前記接着材層の位置に、該接
着材層の開口部が該半導体チップ支持基板の開口部に比
べて大きくなるようにそれぞれ開口部が形成され、前記
開口部を経由するボンディングリードにより前記半導体
チップのパッドが前記インナー接続部と接続され、前記
開口部に封止材が充填されているものであって、 前記半導体チップ支持基板の一方の面には、前記開口部
を略中心とした凹部が形成されていることを特徴とする
半導体装置。8. A semiconductor device in which an inner connection portion and an external connection portion are provided on one surface of a semiconductor chip supporting substrate, and a semiconductor chip having a center pad is mounted via an adhesive formed on the other surface. In the position of the semiconductor chip supporting substrate and the adhesive layer corresponding to the center pad position of the semiconductor chip, the opening of the adhesive layer is larger than the opening of the semiconductor chip supporting substrate. An opening is formed, a pad of the semiconductor chip is connected to the inner connection portion by a bonding lead passing through the opening, and the opening is filled with a sealing material; A semiconductor device, wherein a concave portion is formed on one surface of the substrate, the concave portion being substantially centered on the opening. 【請求項９】前記半導体チップ支持基板の一方の面に形
成された凹部の一部は、前記インナー接続部を構成する
ことを特徴とする請求項８に記載の半導体装置。9. The semiconductor device according to claim 8, wherein a part of a concave portion formed on one surface of said semiconductor chip supporting substrate constitutes said inner connecting portion. 【請求項１０】請求項８または９に記載の半導体装置に
用いられる半導体チップ支持基板であって、 その一方の面にはインナー接続部及び外部接続部が設け
られ、 他方の面には接着材層を介した半導体チップ搭載面を有
し、 半導体チップ支持基板に開口部が半導体チップのパッド
位置に対応するように設けられ、 前記接着材層に設ける開口部が前記半導体チップ支持基
板に設けられた開口部に比べて大きく、 前記一方の面に形成された開口部を略中心とする凹部が
形成されたことを特徴とする半導体チップ支持基板。10. A semiconductor chip supporting substrate used in the semiconductor device according to claim 8, wherein an inner connection portion and an external connection portion are provided on one surface, and an adhesive is provided on the other surface. A semiconductor chip mounting surface with a layer interposed therebetween, an opening provided in the semiconductor chip support substrate corresponding to a pad position of the semiconductor chip, and an opening provided in the adhesive layer provided in the semiconductor chip support substrate A semiconductor chip supporting substrate, wherein a recess is formed which is larger than the opening and is formed substantially at the center of the opening formed on the one surface.
JP28735999A 1999-10-07 1999-10-07 Semiconductor device, semiconductor chip support board therefor, and manufacturing method thereof device Pending JP2001110934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28735999A JP2001110934A (en) 1999-10-07 1999-10-07 Semiconductor device, semiconductor chip support board therefor, and manufacturing method thereof device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28735999A JP2001110934A (en) 1999-10-07 1999-10-07 Semiconductor device, semiconductor chip support board therefor, and manufacturing method thereof device

Publications (1)

Publication Number Publication Date
JP2001110934A true JP2001110934A (en) 2001-04-20

Family

ID=17716355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28735999A Pending JP2001110934A (en) 1999-10-07 1999-10-07 Semiconductor device, semiconductor chip support board therefor, and manufacturing method thereof device

Country Status (1)

Country Link
JP (1) JP2001110934A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030091359A (en) * 2002-05-27 2003-12-03 엘지전자 주식회사 PCB making method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030091359A (en) * 2002-05-27 2003-12-03 엘지전자 주식회사 PCB making method

Similar Documents

Publication Publication Date Title
JP3639088B2 (en) Semiconductor device and wiring tape
JPH11186294A (en) Semiconductor package and manufacture thereof
US7936061B2 (en) Semiconductor device and method of manufacturing the same
JP6806316B2 (en) Printed circuit board, manufacturing method of printed circuit board and semiconductor package including this
JPH09162320A (en) Semiconductor package and semiconductor device
WO2011030542A2 (en) Electronic part module and method for producing same
US20040106288A1 (en) Method for manufacturing circuit devices
JP2002043467A (en) Board for semiconductor package, its manufacturing method, semiconductor package using board and manufacturing method of semiconductor package
KR100608610B1 (en) PCB, manufacturing method thereof and semiconductor package using the same
JP3617072B2 (en) Chip carrier
JP4226839B2 (en) Method for removing uncontrolled voids in a sheet adhesive layer
JP2001110934A (en) Semiconductor device, semiconductor chip support board therefor, and manufacturing method thereof device
JPH07302859A (en) Manufacture of multilayer wiring board for mounting semiconductor chip, and manufacture of semiconductor mounter
JP4589519B2 (en) Manufacturing method of semiconductor circuit components
JP2001127194A (en) Flip chip semiconductor device and its manufacturing method
JP2001110838A (en) Semiconductor device, semiconductor support substrate which is used for that and manufacturing method of semiconductor device
JP2001077536A (en) Printed wiring board with built-in electronic circuit board, and manufacture thereof
JP4452964B2 (en) Semiconductor mounting substrate manufacturing method and semiconductor package manufacturing method
JPH0982835A (en) Circuit substrate and multilayer circuit substrate
JPH10163256A (en) Chip supporting board for semiconductor device
JPH08167676A (en) Semiconductor device
JPH1197574A (en) Electronic parts with bump
JPH0982837A (en) Manufacture of semiconductor package
JPH11220049A (en) Manufacture of substrate
JP4019550B2 (en) Semiconductor package manufacturing method