JP2001110838A - Semiconductor device, semiconductor support substrate which is used for that and manufacturing method of semiconductor device - Google Patents

Semiconductor device, semiconductor support substrate which is used for that and manufacturing method of semiconductor device

Info

Publication number
JP2001110838A
JP2001110838A JP28736099A JP28736099A JP2001110838A JP 2001110838 A JP2001110838 A JP 2001110838A JP 28736099 A JP28736099 A JP 28736099A JP 28736099 A JP28736099 A JP 28736099A JP 2001110838 A JP2001110838 A JP 2001110838A
Authority
JP
Japan
Prior art keywords
semiconductor chip
opening
semiconductor device
supporting substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28736099A
Other languages
Japanese (ja)
Inventor
Akio Yamazaki
聡夫 山崎
Yoshiaki Wakashima
喜昭 若島
Kazuhisa Suzuki
和久 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP28736099A priority Critical patent/JP2001110838A/en
Publication of JP2001110838A publication Critical patent/JP2001110838A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is loaded with a semiconductor chip on the surface on one side of the surfaces of a semiconductor chip support substrate and can reduce the horizontal size of the chip, and the manufacturing method of the device. SOLUTION: A semiconductor chip 3 having a plurality of pads 4 is mounted on the surface 9a on one side of the surfaces of a semiconductor chip support substrate 1 via a bonding agent layer 5, a plurality of apertures 6a, 6b, 14a and 14b are respectively provided in the places, which correspond to the positions of the pads on the chip 3, on the substrate 1 and the layer 5 and a sealing medium 12 is formed on the regions comprising these apertures and gold wires 11 using a vacuum differential pressure printing method.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置、それ
に用いる半導体支持基板、及び半導体装置の製造方法に
関する。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, a semiconductor support substrate used for the same, and a method of manufacturing the semiconductor device.

【０００２】[0002]

【従来の技術】最近の半導体装置は、集積度の増大、高
周波化により、多ピンで小型の半導体装置が望まれてい
る。そのため、従来のリードフレームを用いた周辺端子
タイプは、端子数が増加するとパッケージが大型化して
しまう。対策の一つには端子ピッチの縮小があるが、
０．４ｍｍ以下は困難な状況にある。2. Description of the Related Art In recent semiconductor devices, a multi-pin, small-sized semiconductor device is desired due to an increase in the degree of integration and an increase in frequency. Therefore, in the case of the peripheral terminal type using the conventional lead frame, the package becomes large as the number of terminals increases. One of the measures is to reduce the terminal pitch.
0.4 mm or less is in a difficult situation.

【０００３】端子数の増加への対応策として、端子を面
状に配置するエリアアレイ型のパッケージがある。この
エリアアレイパッケージには、半導体チップのパッド部
から何らかの配線を介して半導体装置の外部接続部に引
き回すための配線基板が必要となるが、配線基板に半導
体チップのパッド部と接続する部分に相当するインナー
接続部及び外部接続部を設け、これら両者を配線基板下
面側に設置することによって、上面と下面を結ぶ層間接
続が不要になるという長所がある。As a measure against the increase in the number of terminals, there is an area array type package in which terminals are arranged in a plane. This area array package requires a wiring board for routing from the pad part of the semiconductor chip to the external connection part of the semiconductor device via some kind of wiring, but it corresponds to the part connected to the pad part of the semiconductor chip on the wiring board. By providing an inner connection portion and an external connection portion, which are provided on the lower surface side of the wiring board, there is an advantage that interlayer connection between the upper surface and the lower surface is not required.

【０００４】このエリアアレイパッケージの一種である
ＣＳＰ型で、複数の電極パッドを有する半導体チップが
搭載されている半導体装置として、例えば特開平１０−
３２１６７２号公報に例示されているものがある。[0004] As a semiconductor device mounted with a semiconductor chip having a plurality of electrode pads of the CSP type, which is a kind of the area array package, for example, Japanese Patent Laid-Open No.
There is one exemplified in Japanese Patent No. 321672.

【０００５】上記従来技術の半導体装置では、第一の面
に導体リードを備える絶縁基板を用い、主面上に複数の
電極パッドを備える半導体チップがその主面を該第一の
面に向けて、該絶縁基板上に接着層を介して搭載され
る。上記絶縁基板はまた、上記第一の面側に導体リード
のインナー接続部及び上記複数の電極パッドを露出させ
るための開口を備え、これら開口を通して伸びるボンデ
ィングワイヤにより導体リードのインナー接続部とそれ
に対応する電極パッドとがそれぞれ接続され、導体リー
ドの外部接続部には外部接続端子が接続される。さら
に、上記ボンディングワイヤ及び開口には、これらが外
気にさらされないように保護するための封止材として樹
脂が形成されている。[0005] In the above-mentioned prior art semiconductor device, an insulating substrate having conductor leads on a first surface is used, and a semiconductor chip having a plurality of electrode pads on a main surface has its main surface facing the first surface. Is mounted on the insulating substrate via an adhesive layer. The insulating substrate also has an opening for exposing the inner connection portion of the conductor lead and the plurality of electrode pads on the first surface side, and the inner connection portion of the conductor lead and a corresponding portion are formed by bonding wires extending through these openings. And the external connection terminal is connected to the external connection portion of the conductor lead. Further, a resin is formed on the bonding wire and the opening as a sealing material for protecting the bonding wire and the opening from being exposed to the outside air.

【０００６】上記従来技術の半導体装置によれば、パッ
ケージの厚みを抑えつつ、接続端子数を多く確保できる
という利点がある。According to the above-described conventional semiconductor device, there is an advantage that a large number of connection terminals can be secured while suppressing the thickness of the package.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、上記従
来技術の半導体装置では、パッケージの水平方向の大き
さを抑える配慮がされておらず、半導体装置の実装高密
度化に対応していない、という問題がある。さらに、上
記従来技術では、半導体チップの電極パッドとインナー
接続部とを接続するボンディングワイヤと、該ボンディ
ングワイヤを通すために設けられた開口とを封止するこ
とが必要となるが、開口部分が大きくなると、封止に必
要な封止材充填量が増加するという問題がある。However, in the above-mentioned conventional semiconductor device, no consideration is given to reducing the size of the package in the horizontal direction, and the semiconductor device is not adapted to the high density mounting of the semiconductor device. There is. Furthermore, in the above-described conventional technology, it is necessary to seal a bonding wire connecting the electrode pad of the semiconductor chip and the inner connection portion and an opening provided for passing the bonding wire. As the size increases, there is a problem that the amount of sealing material required for sealing increases.

【０００８】本発明は、上記の問題点を鑑みてなされた
もので、その目的は、半導体チップが搭載されている半
導体装置、それに用いる半導体チップ支持基板、及び該
半導体装置の製造方法において、半導体チップの電極パ
ッドと配線基板のインナー接続部とを接続するボンディ
ングワイヤを通すために設ける開口部分の開口面積をよ
り小さくすることにより、該半導体装置の水平方向のサ
イズを減少させ、より高密度な実装を実現可能とする半
導体装置、半導体チップ支持基板、およびそれらの製造
方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device having a semiconductor chip mounted thereon, a semiconductor chip supporting substrate used therefor, and a method of manufacturing the semiconductor device. By reducing the opening area of the opening provided for passing the bonding wire connecting the electrode pad of the chip and the inner connection portion of the wiring board, the size of the semiconductor device in the horizontal direction is reduced, and the density of the semiconductor device is increased. An object of the present invention is to provide a semiconductor device, a semiconductor chip supporting substrate, and a method for manufacturing the same, which can be mounted.

【０００９】また、本発明の他の目的は、上記開口部分
の封止に必要となる封止材の充填量をより少なくし、よ
り信頼性の高い樹脂封止を可能とする半導体装置、半導
体チップ支持基板、およびそれらの製造方法を提供する
ことにある。Another object of the present invention is to provide a semiconductor device and a semiconductor device capable of reducing the filling amount of a sealing material required for sealing the above-mentioned opening portion and enabling more reliable resin sealing. An object of the present invention is to provide a chip supporting substrate and a method for manufacturing the same.

【００１０】[0010]

【課題を解決するための手段】上記目的を達成するため
に本発明は、半導体チップ支持基板の一方の面にインナ
ー接続部及び外部接続部が設けられ、他方の面に複数の
パッドを有する半導体チップが搭載された半導体装置に
おいて、前記半導体チップのパッド位置に対応する前記
半導体チップ支持基板上の個所に複数の開口部が形成さ
れ、該複数の開口部の各々を経由するボンディングワイ
ヤにより該半導体チップのパッドと前記インナー接続部
とが接続されるものであって、前記開口部及び前記ボン
ディングワイヤを含む領域に封止材が形成されているこ
とを特徴とする。According to the present invention, there is provided a semiconductor chip supporting substrate having an inner connecting portion and an outer connecting portion provided on one surface and a plurality of pads on the other surface. In a semiconductor device on which a chip is mounted, a plurality of openings are formed at locations on the semiconductor chip support substrate corresponding to pad positions of the semiconductor chip, and the semiconductor is formed by bonding wires passing through each of the plurality of openings. A pad of the chip is connected to the inner connection portion, and a sealing material is formed in a region including the opening and the bonding wire.

【００１１】また本発明では、前記封止材を真空差圧印
刷方法により形成するための封止ダムとして機能する部
材をさらに有することが好ましい。Further, in the present invention, it is preferable to further include a member functioning as a sealing dam for forming the sealing material by a vacuum differential pressure printing method.

【００１２】前記開口部の大きさは、該開口部を経由す
るワイヤボンディング接続を実施するために必要最小限
の大きさ、または、該必要最小限の大きさに対応して設
定された大きさとすることが好ましい。また前記開口部
は、搭載されるべき半導体チップの複数のパッドの各々
にそれぞれ対応するよう個別に形成する構成としても良
い。The size of the opening is a minimum size necessary for performing wire bonding connection through the opening, or a size set corresponding to the minimum size. Is preferred. The openings may be individually formed so as to respectively correspond to a plurality of pads of a semiconductor chip to be mounted.

【００１３】例えば、前記開口部の形状が長方形状であ
る場合には、その短辺の開口サイズが０．１ｍｍ以上
１．０ｍｍ以下とし、また形状が円形状である場合に
は、その開口径が０．１ｍｍ以上１．０ｍｍ以下とする
ことが好ましい。For example, when the shape of the opening is rectangular, the opening size of the short side is 0.1 mm or more and 1.0 mm or less, and when the shape is circular, the opening diameter is Is preferably 0.1 mm or more and 1.0 mm or less.

【００１４】また、本発明においては、前記半導体チッ
プ支持基板を繊維基材と樹脂で構成された複合体で構成
してもよい。Further, in the present invention, the semiconductor chip supporting substrate may be composed of a composite composed of a fiber base material and a resin.

【００１５】また、本発明においては、前記半導体チッ
プ支持基板の一方の面に凹部を形成し、該凹部の底部に
前記開口部が位置するよう構成しても良い。In the present invention, a recess may be formed on one surface of the semiconductor chip supporting substrate, and the opening may be located at the bottom of the recess.

【００１６】また、本発明において、前記半導体チップ
が前記半導体チップ支持基板に接着材層を介して搭載さ
れる場合、前記半導体チップ支持基板の開口部に対応す
る前記接着材層の位置に、該半導体チップ支持基板の開
口部よりも開口面積が大きい開口部を設けることが好ま
しい。In the present invention, when the semiconductor chip is mounted on the semiconductor chip supporting substrate via an adhesive layer, the semiconductor chip is located at a position of the adhesive layer corresponding to an opening of the semiconductor chip supporting substrate. It is preferable to provide an opening having an opening area larger than that of the semiconductor chip supporting substrate.

【００１７】また、上記目的を達成するために本発明
は、一方の面にインナー接続部及び外部接続部が設けら
れ、他方の面に複数のパッドを有する半導体チップが搭
載される半導体チップ支持基板において、前記搭載され
るべき半導体チップのパッドに対応する位置に、該パッ
ドと前記インナー接続部をワイヤボンディングするため
の複数の開口部が形成され、前記開口部を囲む領域に封
止材を真空差圧印刷方法で形成するための封止ダムが形
成されていることを特徴とする。According to another aspect of the present invention, there is provided a semiconductor chip supporting substrate having an inner connection portion and an external connection portion provided on one surface and a semiconductor chip having a plurality of pads mounted on the other surface. A plurality of openings for wire-bonding the pads and the inner connection portions are formed at positions corresponding to the pads of the semiconductor chip to be mounted, and a sealing material is evacuated to a region surrounding the openings. A sealing dam for forming by a differential pressure printing method is formed.

【００１８】前記開口部の大きさは、例えば、該開口部
を経由するワイヤボンディング接続を実施するために必
要最小限の大きさ、または、該必要最小限の大きさに対
応して設定された大きさとすることが好ましい。The size of the opening is set, for example, to a minimum size required for performing wire bonding connection through the opening, or set in accordance with the minimum size. The size is preferably set.

【００１９】また、上記目的を達成するために本発明
は、半導体チップ支持基板の一方の面にインナー接続部
及び外部接続部が設けられ、他方の面に複数のパッドを
有する半導体チップが搭載された半導体装置の製造方法
において、前記半導体チップの複数のパッド位置に対応
する前記半導体チップ支持基板の位置に複数の開口部を
形成する工程と、前記複数の開口部の各々を経由するボ
ンディングワイヤにより前記半導体チップのパッドと前
記インナー接続部とを接続する工程と、前記開口部及び
前記ボンディングワイヤを含む領域に封止材を形成する
工程とを備え、前記封止材を充填する工程では、真空差
圧印刷方法を用いて封止材が形成されることを特徴とす
る。According to another aspect of the present invention, there is provided a semiconductor chip supporting substrate in which an inner connection portion and an external connection portion are provided on one surface and a semiconductor chip having a plurality of pads is mounted on the other surface. Forming a plurality of openings at positions of the semiconductor chip supporting substrate corresponding to a plurality of pad positions of the semiconductor chip, and bonding wires passing through each of the plurality of openings. A step of connecting a pad of the semiconductor chip to the inner connection portion; and a step of forming a sealing material in a region including the opening and the bonding wire. The sealing material is formed using a differential pressure printing method.

【００２０】前記開口部の大きさは、例えば、該開口部
を経由するワイヤボンディング接続を実施するために必
要最小限の大きさ、または、該必要最小限の大きさに対
応して設定された大きさとすることが好ましい。The size of the opening is set, for example, to a minimum size necessary for performing wire bonding connection through the opening, or set in accordance with the minimum size. The size is preferably set.

【００２１】また、前記開口部を形成する工程は、レー
ザ加工によって開口する工程を含むこと好ましい。Further, the step of forming the opening preferably includes the step of opening by laser processing.

【００２２】[0022]

【発明の実施の形態】本発明を適用した半導体チップ
は、半導体であるシリコン等の小片上に薄膜によりトラ
ンジスタ、ダイオード、抵抗、コンデンサ等の多数の回
路素子、すなわち集積回路が形成されたものである。半
導体チップ表面には、信号の入出力や電源を外部から供
給するために半導体チップのパッドが複数形成されてい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor chip to which the present invention is applied is one in which a large number of circuit elements such as transistors, diodes, resistors, capacitors, etc., that is, integrated circuits are formed by thin films on small pieces of silicon or the like as a semiconductor. is there. A plurality of pads of the semiconductor chip are formed on the surface of the semiconductor chip in order to input / output signals and supply power from outside.

【００２３】本発明の半導体チップ支持基板は、絶縁基
材層と配線層の多層構造体及び配線層間を電気的に接続
するバイアホール等から構成される配線層が一層以上の
多層基板から構成される。The semiconductor chip supporting substrate of the present invention comprises a multi-layer substrate having one or more wiring layers comprising a multilayer structure of an insulating base material layer and a wiring layer and via holes for electrically connecting the wiring layers. You.

【００２４】絶縁基材層の構成としては、樹脂単体、セ
ラミック繊維、ガラス繊維やアラミド繊維等の無機、有
機繊維からなる織布や不織布等の繊維基材と樹脂の複合
体、有機または無機フィラーと樹脂の複合体、セラミッ
クス単体などが用いられる。The insulating base layer may be composed of a resin alone, a composite of a fiber base such as a woven or nonwoven fabric made of inorganic or organic fiber such as ceramic fiber, glass fiber or aramid fiber, or an organic or inorganic filler. And a resin composite, a ceramic simple substance and the like are used.

【００２５】樹脂材料としては、エポキシ樹脂、メラミ
ン樹脂、尿素樹脂、アクリル樹脂、フェノール樹脂、ポ
リイミド樹脂、テフロン樹脂、ポリエチレン樹脂、ポリ
エステル樹脂、ポリアミド樹脂、シリコーン樹脂等が用
いられる。As the resin material, epoxy resin, melamine resin, urea resin, acrylic resin, phenol resin, polyimide resin, Teflon resin, polyethylene resin, polyester resin, polyamide resin, silicone resin and the like are used.

【００２６】有機フィラーとしては、エポキシ樹脂、メ
ラミン樹脂、尿素樹脂、アクリル樹脂、フェノール樹
脂、ポリイミド樹脂、テフロン樹脂、ポリエチレン樹
脂、ポリエステル樹脂、ポリアミド樹脂、シリコーン樹
脂等の樹脂を使用する溶剤に不溶となるまで高分子化し
微粒子化したタイプあるいは、架橋し微粒子化したタイ
プのフィラーである。The organic filler is insoluble in solvents using resins such as epoxy resin, melamine resin, urea resin, acrylic resin, phenol resin, polyimide resin, Teflon resin, polyethylene resin, polyester resin, polyamide resin and silicone resin. It is a type of filler that has been polymerized and made into fine particles to the extent possible, or a type that has been crosslinked and made into fine particles.

【００２７】無機フィラーとしては、アルミナ、シリ
カ、マグネシア、フェライトなどの金属酸化物の微粒
子、あるいはタルク、マイカ、カオリン、ゼオライトな
どの珪酸塩類、硫酸バリウム、炭酸カルシウムなどの微
粒子が使用される。As the inorganic filler, fine particles of metal oxides such as alumina, silica, magnesia and ferrite, or fine particles of silicates such as talc, mica, kaolin and zeolite, barium sulfate and calcium carbonate are used.

【００２８】この中で、繊維基材と樹脂から構成された
複合体が好ましく、その中でも、ガラスクロス材にエポ
キシ樹脂、ポリイミド樹脂を含浸してなるガラスエポキ
シ材、ガラスポリイミド材を用いることが特に製造工程
における剛性及び信頼性等の観点から望ましい。Among these, a composite composed of a fiber base material and a resin is preferable. Among them, it is particularly preferable to use a glass epoxy material or a glass polyimide material obtained by impregnating a glass cloth material with an epoxy resin or a polyimide resin. It is desirable from the viewpoint of rigidity and reliability in the manufacturing process.

【００２９】半導体チップ支持基板の一方の面には接着
材を介して半導体チップが搭載されている。本発明の半
導体チップ支持基板の一方の面には、半導体チップの複
数のパッドと接続する領域である複数のインナー接続部
が設けられている。また、同面には、本半導体装置から
外部装置に接続する領域である外部接続部が形成されて
いる。通常、外部接続部には外部装置との連結のための
はんだ等の金属端子が設けられる。A semiconductor chip is mounted on one surface of the semiconductor chip supporting substrate via an adhesive. On one surface of the semiconductor chip supporting substrate of the present invention, a plurality of inner connection portions, which are regions connected to a plurality of pads of the semiconductor chip, are provided. On the same surface, an external connection portion, which is a region connecting the semiconductor device to an external device, is formed. Usually, a metal terminal such as a solder for connection with an external device is provided in the external connection portion.

【００３０】半導体チップ支持基板を構成する配線材料
は銅、アルミニウム、ニッケル、鉄、クロム、銀等の金
属材料や合金等が用いられる。また、必要に応じて配線
表面にはニッケル、金、錫、はんだなどのめっき等によ
る表面処理が施されている。配線は、エッチング法、ア
ディティブ法、セミアディティブ法、配線転写法等で形
成される。特に、上記インナー接続部や外部接続部が構
成されている面に形成された配線は基材内に埋め込まれ
ていることが好ましい。As a wiring material constituting the semiconductor chip supporting substrate, a metal material such as copper, aluminum, nickel, iron, chromium, silver, or an alloy is used. Further, the surface of the wiring is subjected to a surface treatment such as plating of nickel, gold, tin, solder, or the like as necessary. The wiring is formed by an etching method, an additive method, a semi-additive method, a wiring transfer method, or the like. In particular, it is preferable that the wiring formed on the surface on which the inner connection portion and the external connection portion are formed be embedded in the base material.

【００３１】半導体チップ支持基板に半導体チップを搭
載するために用いる接着材は樹脂、または樹脂と有機ま
たは無機フィラーを主成分とした材料である。樹脂の材
質としては、例えば、エポキシ樹脂、メラミン樹脂、尿
素樹脂、アクリル樹脂、フェノール樹脂、ポリイミド樹
脂、テフロン樹脂、ポリエチレン樹脂、ポリエステル樹
脂、ポリアミド樹脂、シリコーン樹脂等がある。The adhesive used to mount the semiconductor chip on the semiconductor chip supporting substrate is a resin or a material mainly composed of a resin and an organic or inorganic filler. Examples of the resin material include an epoxy resin, a melamine resin, a urea resin, an acrylic resin, a phenol resin, a polyimide resin, a Teflon resin, a polyethylene resin, a polyester resin, a polyamide resin, and a silicone resin.

【００３２】有機フィラーとしては、エポキシ樹脂、メ
ラミン樹脂、尿素樹脂、アクリル樹脂、フェノール樹
脂、ポリイミド樹脂、テフロン樹脂、ポリエチレン樹
脂、ポリエステル樹脂、ポリアミド樹脂、シリコーン樹
脂等の樹脂を使用する溶剤に不溶となるまで高分子化し
微粒子化したタイプあるいは、架橋し微粒子化したタイ
プのフィラーである。As the organic filler, an insoluble in a solvent using a resin such as an epoxy resin, a melamine resin, a urea resin, an acrylic resin, a phenol resin, a polyimide resin, a Teflon resin, a polyethylene resin, a polyester resin, a polyamide resin, and a silicone resin. It is a type of filler that has been polymerized and made into fine particles to the extent possible, or a type that has been crosslinked and made into fine particles.

【００３３】無機フィラーとしては、アルミナ、シリ
カ、マグネシア、フェライトなどの金属酸化物の微粒
子、あるいはタルク、マイカ、カオリン、ゼオライトな
どの珪酸塩類、硫酸バリウム、炭酸カルシウムなどの微
粒子を使用する。As the inorganic filler, fine particles of metal oxides such as alumina, silica, magnesia and ferrite, or fine particles of silicates such as talc, mica, kaolin and zeolite, barium sulfate and calcium carbonate are used.

【００３４】上記フィラーは１種または２種以上を混合
して使用する。また、接着材層は必ずしも一層で形成す
る必要はなく、必要に応じて異種または同質の材料を２
層以上に形成してもよい。この接着材層はエラストマ的
性状を示すものを用いることが好ましい。The above fillers may be used alone or in combination of two or more. It is not always necessary to form the adhesive layer as a single layer.
It may be formed in layers or more. It is preferable to use an adhesive layer having an elastomeric property.

【００３５】接着材層及び半導体チップ支持基板には、
搭載されるべき半導体チップの複数のパッドおよびそれ
と接続されるインナー接続部に対応した位置に開口が設
けられており、該開口およびボンディングワイヤーを封
止するための封止材が形成されている。封止材は真空差
圧印刷方法を用いて形成されることが好ましく、前記半
導体チップ支持基板には、真空差圧印刷方法を実施する
ための封止ダム等の部材が設けられている。The adhesive layer and the semiconductor chip supporting substrate include:
An opening is provided at a position corresponding to a plurality of pads of a semiconductor chip to be mounted and an inner connection portion connected to the pad, and a sealing material for sealing the opening and the bonding wire is formed. The sealing material is preferably formed using a vacuum differential pressure printing method, and the semiconductor chip supporting substrate is provided with a member such as a sealing dam for performing the vacuum differential pressure printing method.

【００３６】なお「対応する位置に設ける」とは、半導
体チップの電極パッドと半導体チップ支持基板のインナ
ーボンディング端子とが、この開口を介してボンディン
グワイヤーを用いて接続可能になる位置に設けることを
意味している。The phrase "provided at a corresponding position" means that the electrode pad of the semiconductor chip and the inner bonding terminal of the semiconductor chip supporting substrate are provided at a position where they can be connected to each other by using a bonding wire through this opening. Means.

【００３７】好ましくは、インナー接続部は接着材層に
設けられた開口部より水平方向外側に配置する。これ
は、ワイヤボンディングする際に接着材の開口部がある
とボンディグミスが発生する可能性があるからである。[0037] Preferably, the inner connection portion is disposed horizontally outside of the opening provided in the adhesive layer. This is because there is a possibility that bonding errors may occur if there is an opening of the adhesive during wire bonding.

【００３８】本発明の半導体装置において、開口部の開
口面積はより小さくすることが好ましく、例えばワイヤ
ボンディングの実施に必要最小限の大きさ、あるいは該
最小限の大きさに対応して設定されるものとする。In the semiconductor device of the present invention, it is preferable that the opening area of the opening is smaller, for example, the minimum size required for performing the wire bonding, or set corresponding to the minimum size. Shall be.

【００３９】上記開口部分の形状は長方形状あるいは円
形状とし、その短辺の開口サイズあるいは開口径が０．
１ｍｍ以上１．０ｍｍ以下、より好ましくは０．２ｍｍ
以上０．７ｍｍ以下とする。The shape of the opening is a rectangle or a circle, and the opening size or the opening diameter of the short side is 0.1 mm.
1 mm or more and 1.0 mm or less, more preferably 0.2 mm
At least 0.7 mm.

【００４０】また上記開口部分は、半導体チップの複数
のパッドの各々に対応するよう個別に設けられてもよ
く、また、該複数のパッドのうちの一部あるいは全ての
パッド群に対してそれぞれ設けられる構成としても良
い。The openings may be individually provided so as to correspond to a plurality of pads of the semiconductor chip, respectively, or may be provided for a part or all of the plurality of pads. It is good also as a structure which can be performed.

【００４１】また、本発明による半導体装置では、接着
材層に設けられた開口部がチップ支持基板に設けられた
開口部に比べて大きいものとすることが好ましい。In the semiconductor device according to the present invention, it is preferable that the opening provided in the adhesive layer is larger than the opening provided in the chip supporting substrate.

【００４２】また、本発明においては、接着材層の開口
部およびチップ支持基板の開口部のうち少なくとも一方
はレーザ加工によって形成されるものとすることが好ま
しい。In the present invention, at least one of the opening of the adhesive layer and the opening of the chip supporting substrate is preferably formed by laser processing.

【００４３】ボンディングワイヤーは、材質としては、
導電材料であり、例えば、金、銅線、アルミ線、それら
の樹脂被覆金属線等がある。ボンディングワイヤーの形
態として、独立したワイヤーであることが望ましいが、
半導体チップ支持基板のインナー接続端子を該基板の開
口部まで延長したリードも含んでいる。The bonding wire is made of a material
A conductive material such as gold, copper wire, aluminum wire, or a resin-coated metal wire thereof. As a form of the bonding wire, it is desirable to be an independent wire,
It also includes a lead extending the inner connection terminal of the semiconductor chip support substrate to the opening of the substrate.

【００４４】封止材は樹脂単体または樹脂と有機または
無機フィラーを主成分とした絶縁材料である。樹脂の材
質としては、例えば、エポキシ樹脂、メラミン樹脂、尿
素樹脂、アクリル樹脂、フェノール樹脂、ポリイミド樹
脂、テフロン樹脂、ポリエチレン樹脂、ポリエステル樹
脂、ポリアミド樹脂等がある。The sealing material is a resin alone or an insulating material containing a resin and an organic or inorganic filler as main components. Examples of the resin material include an epoxy resin, a melamine resin, a urea resin, an acrylic resin, a phenol resin, a polyimide resin, a Teflon resin, a polyethylene resin, a polyester resin, and a polyamide resin.

【００４５】有機フィラーとしては、エポキシ樹脂、メ
ラミン樹脂、尿素樹脂、アクリル樹脂、フェノール樹
脂、ポリイミド樹脂、テフロン樹脂、ポリエチレン樹
脂、ポリエステル樹脂、ポリアミド樹脂等の樹脂を使用
する溶剤に不溶となるまで高分子化し微粒子化したタイ
プあるいは、架橋し微粒子化したタイプのフィラーが用
いられる。As the organic filler, a resin such as an epoxy resin, a melamine resin, a urea resin, an acrylic resin, a phenol resin, a polyimide resin, a Teflon resin, a polyethylene resin, a polyester resin, or a polyamide resin is used until it becomes insoluble in a solvent used. A filler of molecular type and fine particle or a type of cross-linked fine particle type is used.

【００４６】無機フィラーとしては、アルミナ、シリ
カ、マグネシア、フェライトなどの金属酸化物の微粒
子、あるいはタルク、マイカ、カオリン、ゼオライトな
どの珪酸塩類、硫酸バリウム、炭酸カルシウムなどの微
粒子を使用する。上記フィラーは１種または２種以上を
混合して使用する。As the inorganic filler, fine particles of a metal oxide such as alumina, silica, magnesia, and ferrite, or silicates such as talc, mica, kaolin, and zeolite, and fine particles such as barium sulfate and calcium carbonate are used. The filler is used alone or in combination of two or more.

【００４７】本発明においては、封止材の形成方式とし
て真空雰囲気で充填する真空差圧印刷方法を用いるもの
とする。In the present invention, a vacuum differential pressure printing method of filling in a vacuum atmosphere is used as a method for forming a sealing material.

【００４８】真空差圧印刷方法とは、複雑な内部構造を
有する印刷部分に気泡が残らないように印刷樹脂を充填
するために考案された方法であり、具体的には特開平１
１−４０５９０号公報に開示された方法がある。The vacuum differential pressure printing method is a method devised to fill a printing portion having a complicated internal structure with a printing resin so that air bubbles do not remain in the printing portion.
There is a method disclosed in JP-A-1-40590.

【００４９】本方法においては印刷部位全体、即ち印刷
装置の一部分又は全部、印刷マスク、液状樹脂封止材及
び被印刷物を真空容器の中に設置し、まず真空容器を高
真空にして１回目の印刷を行う。この状態では印刷部の
細部には樹脂が充填されにくい。そこで、次に真空容器
を中真空状態にすると１回目の印刷で樹脂が充填されな
かった高真空の空洞部分が中真空状態でつぶされ、空洞
がほとんど無くなり、同時に空洞部に充填された樹脂分
だけ樹脂表面に窪みが発生する。その状態で中真空のま
ま２回目の印刷を行い、樹脂表面の窪みを埋めた後、大
気圧に戻し被印刷物を取り出す。In the present method, the entire printing portion, that is, a part or the whole of the printing apparatus, the printing mask, the liquid resin sealing material and the printing object are placed in a vacuum container. Perform printing. In this state, it is difficult for the details of the printing section to be filled with the resin. Then, when the vacuum container is next set to a medium vacuum state, the high vacuum cavity portion, which was not filled with resin in the first printing, is crushed in the medium vacuum state, the cavity is almost eliminated, and at the same time, the resin filled in the cavity portion is removed. Only a depression occurs on the resin surface. In this state, the second printing is performed while maintaining the medium vacuum, and after filling the depressions on the resin surface, the pressure is returned to the atmospheric pressure, and the printing object is taken out.

【００５０】封止材は開口部内に充填されることが好ま
しく、少なくとも半導体チップのパッド周辺に加えて、
ボンディングワイヤー周辺、インナー接続部周辺等にも
配置することがさらに好ましい。The sealing material is preferably filled in the opening, and at least around the pads of the semiconductor chip,
It is more preferable to dispose it also around the bonding wire, the inner connection part, and the like.

【００５１】本発明の第一の実施の形態を図１を用いて
説明する。図１に本実施形態における半導体装置の断面
図を示す。The first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a sectional view of the semiconductor device according to the present embodiment.

【００５２】本実施形態の半導体装置において、配線基
板２の一方の面（Ａ面）９ａに接着材（接着材層）５を
介して半導体チップ３が半導体チップのパッド４を基板
側にして搭載されている。配線基板２の他方の面（Ｂ
面）９ｂには、外部接続部７ｃ及びインナー接続部７ａ
が設けられている。In the semiconductor device of the present embodiment, the semiconductor chip 3 is mounted on one surface (A surface) 9a of the wiring board 2 via an adhesive (adhesive layer) 5 with the pad 4 of the semiconductor chip facing the substrate. Have been. The other surface of the wiring board 2 (B
Surface) 9b has an external connection portion 7c and an inner connection portion 7a.
Is provided.

【００５３】半導体チップ支持基板１及び接着材５に
は、開口部６及び開口部１４が設けられており、これら
開口部６及び開口部１４を介して、半導体チップのパッ
ド４とインナー接続部７ａがボンディングワイヤ１１に
よって接続されている。An opening 6 and an opening 14 are provided in the semiconductor chip supporting substrate 1 and the adhesive 5, and the pad 4 of the semiconductor chip and the inner connecting portion 7 a are provided through the opening 6 and the opening 14. Are connected by bonding wires 11.

【００５４】開口部６の大きさは、使用するワイヤボン
ディング装置に応じて、ワイヤボンディング接合に必要
最小限の大きさ、あるいは、ワイヤボンディング処理の
自動化に支障をきたさない最小限の大きさ、あるいは、
これら最小限の大きさに応じて設定された大きさとす
る。また、接着材５に形成された開口部１４の大きさ
は、開口部６の大きさよりも大きいものとする。The size of the opening 6 depends on the wire bonding apparatus to be used, and is the minimum size necessary for wire bonding, the minimum size that does not hinder the automation of the wire bonding process, or ,
The size is set according to the minimum size. The size of the opening 14 formed in the adhesive 5 is larger than the size of the opening 6.

【００５５】外部接続部７ｃには、はんだボール等の外
部接続端子１０が設けられている。必要に応じて、半導
体チップ支持基板１のＢ面９ｂに封止ダム１３が設けら
れ、真空差圧印刷方法により封止材１２が形成される。
なお、図中の８はマスク樹脂である。The external connection portion 7c is provided with an external connection terminal 10 such as a solder ball. If necessary, a sealing dam 13 is provided on the B surface 9b of the semiconductor chip supporting substrate 1, and the sealing material 12 is formed by a vacuum differential pressure printing method.
Note that reference numeral 8 in the drawing denotes a mask resin.

【００５６】本実施形態によれば、必要最小限の大きさ
を備える開口部６を設けているため、水平方向サイズの
最小化を図ることが可能となる半導体装置を提供するこ
とができる。According to the present embodiment, since the opening 6 having the minimum size is provided, it is possible to provide a semiconductor device capable of minimizing the horizontal size.

【００５７】さらに、本実施形態によれば、開口部６及
び１４の大きさを最小限の大きさとするため、真空差圧
印刷方法を用いて封止材を差圧充填する際の樹脂層破れ
（差圧短絡）によるボイドの発生を防ぐことが可能とな
り、全体として封止材の使用量を減らすだけでなく、形
成された封止材の信頼性を向上させることがことが可能
になる。また、封止材の盛り上がりが小さくなり、より
小さい外部接続端子が形成可能となり、端子の狭ピッチ
化や高さ低減による小型化が実現する。Further, according to the present embodiment, in order to minimize the size of the openings 6 and 14, the resin layer breaks when the sealing material is subjected to the differential pressure filling using the vacuum differential pressure printing method. It is possible to prevent the occurrence of voids due to (differential pressure short-circuit), not only to reduce the amount of the sealing material used as a whole, but also to improve the reliability of the formed sealing material. In addition, the swelling of the sealing material is reduced, and a smaller external connection terminal can be formed, so that miniaturization can be realized by narrowing the pitch of the terminals and reducing the height.

【００５８】本発明の第二の実施の形態を図２を用いて
説明する。図２に本発明の第二の実施の形態の半導体装
置の断面図を示す。A second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

【００５９】本実施形態において上記第一の実施形態と
異なる点は、本実施形態の半導体チップ支持基板１のＢ
面９ｂには配線７が埋め込まれた凹部が形成され、該凹
部内にインナー接続部７ａが形成され、マスク樹脂８は
凹部内の周縁部付近にも設けられている、という点であ
る。The present embodiment is different from the first embodiment in that the semiconductor chip supporting substrate 1 of this embodiment has a B
The surface 9b is formed with a concave portion in which the wiring 7 is embedded, the inner connecting portion 7a is formed in the concave portion, and the mask resin 8 is also provided near the periphery of the concave portion.

【００６０】本実施形態によれば、半導体チップ支持基
板１の一方の面９ｂに凹部が設けられているため、真空
差圧印刷方法により封止材を充填する際に、開口部６の
上方、すなわち該凹部の底部分に集中して封止材を盛り
上げることが容易になるため、より少ない充填量でより
効率的に封止材を形成することができる。また、封止材
の盛り上がりをより小さくできるため、小さな外部接続
端子を形成しても、マザーボード実装時に障害となら
ず、小型化が実現する。According to the present embodiment, since the concave portion is provided on one surface 9b of the semiconductor chip supporting substrate 1, when the sealing material is filled by the vacuum differential pressure printing method, the upper portion of the opening 6 is removed. That is, it is easy to concentrate the sealing material on the bottom of the recess, so that the sealing material can be formed more efficiently with a smaller filling amount. Further, since the swelling of the sealing material can be further reduced, even if a small external connection terminal is formed, it does not hinder the mounting on the motherboard, and the size can be reduced.

【００６１】なお、本実施形態のようにインナー接続部
が凹部内に設けられていても、配線７が埋め込まれてい
ても、マスク樹脂８が凹部内周縁部に設けれていてもそ
れぞれ、本実施形態による効果には差がない。It should be noted that whether the inner connection portion is provided in the concave portion as in this embodiment, the wiring 7 is embedded, or the mask resin 8 is provided in the inner peripheral portion of the concave portion, There is no difference in the effect according to the embodiment.

【００６２】本発明の第三の実施の形態を図３〜５を用
いて説明する。図３に本発明の第三の実施の形態の半導
体装置の断面図を示す。A third embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a sectional view of a semiconductor device according to the third embodiment of the present invention.

【００６３】本実施形態による半導体装置についても、
その基本的構成、開口部の構造などは上述した第一の実
施形態と同様であるが、以下の点が異なる。すなわち、
半導体チップ支持基板１の開口部６ａ、６ｂ及び接着材
５の開口部１４ａ、１４ｂが複数個設けられている、と
いう点である。The semiconductor device according to the present embodiment also
The basic configuration, the structure of the opening, and the like are the same as in the first embodiment described above, but differ in the following points. That is,
The point is that a plurality of openings 6a and 6b of the semiconductor chip support substrate 1 and a plurality of openings 14a and 14b of the adhesive 5 are provided.

【００６４】本実施形態の半導体チップ支持基板１にお
いて開口部６ａ、６ｂは、例えば図４に示すように半導
体チップの電極パッド４ａ、４ｂの各列に対しそれぞれ
設けてもよく、また図５に示すように各個別の電極パッ
ド４ａ、４ｂ…に対応して個別の開口部６ａ、６ｂ…を
設ける構成としても良い。さらにまた、必要に応じて所
定数の電極パッドをグループ化し、各グループ毎に対応
する開口部を設ける構成としても良い。In the semiconductor chip supporting substrate 1 of this embodiment, the openings 6a and 6b may be provided for each row of the electrode pads 4a and 4b of the semiconductor chip as shown in FIG. As shown, individual openings 6a, 6b... May be provided corresponding to the individual electrode pads 4a, 4b. Further, a predetermined number of electrode pads may be grouped as necessary, and a corresponding opening may be provided for each group.

【００６５】これら複数の開口部の孔あけにはレーザ加
工を用いることが好ましい。これは、本発明では開口部
の大きさが必要最小限の大きさとしているため、レーザ
加工による孔あけ処理にかかる時間の短縮やより高精度
な加工が可能となるという効果がある。It is preferable to use laser processing for drilling the plurality of openings. In the present invention, since the size of the opening is set to the minimum necessary size, there is an effect that the time required for the drilling processing by laser processing can be reduced and more accurate processing can be performed.

【００６６】[0066]

【実施例】本発明の詳細な実施例を図６〜１８を用いて
説明する。図６〜１８は、上記図３に示した構造の半導
体装置の製造方法の一例を説明する断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A detailed embodiment of the present invention will be described with reference to FIGS. 6 to 18 are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device having the structure shown in FIG.

【００６７】最初、図６に示すように、銅箔１６ａ（厚
み：１８μｍ）／ガラスクロスエポキシ材１７（厚み：
０．２ｍｍ）／銅箔１６ｂ（厚み：１８μｍ）の三層構
成からなる周知の銅張り積層板１５（日立化成工業株式
会社製、商品名：ＭＣＬ−Ｅ６７９）を用いる。First, as shown in FIG. 6, a copper foil 16a (thickness: 18 μm) / glass cloth epoxy material 17 (thickness:
A well-known copper-clad laminate 15 (manufactured by Hitachi Chemical Co., Ltd., trade name: MCL-E679) having a three-layer structure of 0.2 mm) / copper foil 16b (thickness: 18 μm) is used.

【００６８】周知のフォトリソ法で片面（Ｂ面）２５ｂ
に配線１８を形成し、他面の銅箔はエッチングにより除
去した（図７）。配線の形成では、レジストとして感光
性のエッチング用ドライフィルムレジスト（日立化成工
業株式会社製、商品名：フォテックＨＮ６４０）を用い
た。One side (B side) 25b by a well-known photolithography method
Was formed, and the copper foil on the other surface was removed by etching (FIG. 7). In forming the wiring, a photosensitive dry film resist for etching (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN640) was used as the resist.

【００６９】レジストラミネート条件は、ロール圧力
２．０ｋｇｆ／ｃｍ、ロール温度１００°Ｃ、送り速度
１．０ｍ／ｍｉｎとした。露光はオーク株式会社製の平
行露光機（ＥＸＭ−１６００−Ａ）を使用し、露光量８
０ｍＪ／ｃｍ2で行った。現像は、炭酸ナトリウム水溶
液（液濃度：１．０ｗｔ％、液温：２８°Ｃ）を使用
し、スプレー圧１．５ｋｇｆ／ｃｍ2で行った。エッチ
ング液としてアルカリエッチング液（メルテックス社
製、商品名：Ａプロセス）を用いた。液温度４０°Ｃ、
スプレー圧力を１．２ｋｇｆ／ｃｍ2で行った。The conditions for resist lamination were a roll pressure of 2.0 kgf / cm, a roll temperature of 100 ° C., and a feed speed of 1.0 m / min. Exposure was performed using a parallel exposure machine (EXM-1600-A) manufactured by Oak Co., Ltd.
The test was performed at 0 mJ / cm 2 . The development was performed using a sodium carbonate aqueous solution (liquid concentration: 1.0 wt%, liquid temperature: 28 ° C.) at a spray pressure of 1.5 kgf / cm 2 . As an etching solution, an alkali etching solution (trade name: A process, manufactured by Meltex Co., Ltd.) was used. Liquid temperature 40 ° C,
The spray pressure was 1.2 kgf / cm 2 .

【００７０】次に、配線板に所定の開口部２４ａ、２４
ｂをルータ加工で形成した（図８）。開口部２４ａ、２
４ｂの大きさは、以下で行われるワイヤボンディング工
程で必要とされる最小限の開口面積あるいは該ワイヤボ
ンディング工程の自動化を妨げない最小限の開口面積、
あるいは、これらの開口面積に応じて設定された大きさ
とする。より具体的には、開口部の開口形状が長方形状
または円形状である場合、その短辺の開口サイズまたは
開口径が０．１ｍｍ以上１．０ｍｍ以下、より好ましく
は０．２ｍｍ以上０．７ｍｍ以下とする。Next, predetermined openings 24a, 24a are formed in the wiring board.
b was formed by router processing (FIG. 8). Openings 24a, 2
The size of 4b is the minimum opening area required in the wire bonding step performed below or the minimum opening area which does not hinder the automation of the wire bonding step.
Alternatively, the size is set according to the opening area. More specifically, when the opening shape of the opening is rectangular or circular, the opening size or opening diameter of the short side is 0.1 mm or more and 1.0 mm or less, more preferably 0.2 mm or more and 0.7 mm or less. The following is assumed.

【００７１】なお、本例では開口部を複数個に分割して
設けた例（図４、５参照）を示したが、分割せずに単一
の開口部を設ける場合についても、本実施例の製造方法
と同様の方法を用いることができる。さらに、開口部を
設ける工程は必ずしもこの段階に限定されるものではな
く、前後の工程で設ける構成としてもよい。In this embodiment, an example is shown in which the opening is divided into a plurality of portions (see FIGS. 4 and 5). However, the present embodiment is also applicable to a case where a single opening is provided without being divided. Can be used. Further, the step of providing the opening is not necessarily limited to this stage, and the opening may be provided in the preceding and following steps.

【００７２】次に、外部接続部１８ｃ及びインナー接続
部１８ａを開口させるように、ソルダーレジスト１９を
形成する。液状の感光性ソルダーレジスト（日立化成工
業株式会社製、ＰＳＲ−７０００）を印刷法で必要領域
部に塗布し、フォトリソ法でパターン形成した。印刷マ
スクはシルクスクリーンマスクを用い、レジスト厚み
（硬化後）を２０μｍとなるように形成し、脱泡後、乾
燥（温度８５°Ｃ、時間２５分）し、露光した。露光
は、平行露光機を用い、露光量は５００ｍＪ／ｃｍ2と
した。現像では、現像液に１ｗｔ％炭酸ナトリウム水溶
液を用い、液温度３０°Ｃ、現像時間９０秒、スプレー
圧２ｋｇｆ／ｃｍ2とした。現像後、後加熱（温度１５
０°Ｃ、１時間）を行った。Next, a solder resist 19 is formed so as to open the external connection portion 18c and the inner connection portion 18a. A liquid photosensitive solder resist (manufactured by Hitachi Chemical Co., Ltd., PSR-7000) was applied to a required area by a printing method, and a pattern was formed by a photolithographic method. The print mask was formed using a silk screen mask so that the resist thickness (after curing) was 20 μm, and after defoaming, drying (temperature 85 ° C., time 25 minutes) and exposure. For exposure, a parallel exposure machine was used, and the exposure amount was 500 mJ / cm 2 . In the development, a 1 wt% sodium carbonate aqueous solution was used as a developer, the liquid temperature was 30 ° C., the development time was 90 seconds, and the spray pressure was 2 kgf / cm 2 . After development, post-heating (temperature 15
(0 ° C., 1 hour).

【００７３】本例では、Ｂ面２５ｂのみにソルターレジ
ストを形成した例を示したが、Ａ面にもソルターレジス
ト等の樹脂層を設けてもよい。次に露出しているインナ
ー接続部及び外部接続部にニッケルめっき（厚さ：５μ
ｍ）（不図示）及び金めっき（厚さ：０．７μｍ）（不
図示）を施し、半導体チップ支持基板２７を得た（図
９）。In this embodiment, an example is shown in which a salter resist is formed only on the B side 25b. However, a resin layer such as a sorter resist may be provided on the A side. Next, nickel plating (thickness: 5 μm) is applied to the exposed inner connection portion and external connection portion.
m) (not shown) and gold plating (thickness: 0.7 μm) (not shown) to obtain a semiconductor chip supporting substrate 27 (FIG. 9).

【００７４】次に、接着材層として接着フィルム（日立
化成工業株式会社製、商品名：ＤＦ−３３５）を打抜き
加工で所定の形状に加工した。この打抜き加工した接着
フィルム２１を半導体チップ支持基板２７のＡ面２５ａ
に圧着した（図１０）。接着条件は、温度１６０°Ｃ、
時間５秒、圧力３ｋｇｆ／ｃｍ2とした。Next, an adhesive film (trade name: DF-335, manufactured by Hitachi Chemical Co., Ltd.) was formed into a predetermined shape by punching as an adhesive layer. The punched adhesive film 21 is attached to the A surface 25 a of the semiconductor chip support substrate 27.
(FIG. 10). The bonding conditions were a temperature of 160 ° C,
The time was 5 seconds and the pressure was 3 kgf / cm 2 .

【００７５】次に、半導体チップを所定の位置に接着す
る（図１１）。接着条件は、温度２２０°Ｃ、時間５
秒、圧力３００ｇｆ／ｃｍ2とした。このとき、接着材
の開口部２６ａ、２６ｂの輪郭部分から半導体チップ支
持基板の開口部２４ａ、２４ｂの輪郭部分までの横方向
距離は、１００μｍとなった。Next, the semiconductor chip is bonded to a predetermined position (FIG. 11). The bonding conditions were as follows: temperature 220 ° C., time 5
Second, the pressure was 300 gf / cm 2 . At this time, the lateral distance from the outline of the openings 26a and 26b of the adhesive to the outline of the openings 24a and 24b of the semiconductor chip supporting substrate was 100 μm.

【００７６】次に、市販のワイヤーボンディング装置
（新川株式会社製、装置名：ＵＴＣ−２３０ＢＩ）によ
り、半導体チップのパッド部２８と対応するインナー接
続部１８ａを金線（２５μｍ径）２２を介して電気的に
接続した（図１２）。Next, the inner connection portion 18a corresponding to the pad portion 28 of the semiconductor chip is connected via the gold wire (diameter 25 μm) 22 by a commercially available wire bonding device (device name: UTC-230BI, manufactured by Shinkawa Corporation). It was electrically connected (FIG. 12).

【００７７】次に、半導体チップ３０のパッド部２８、
インナー接続部１８ａ及び金線２２等の周辺を防湿及び
保護する目的で半導体用ポッティング樹脂（日立化成工
業株式会社製、ＨＩＲ３０００）で封止した。封止は、
東レエンジニアリング株式会社製の真空差圧印刷装置
（型番：ＶＤ−１０００）を用い、真空差圧印刷方法を
用いた。Next, the pad portion 28 of the semiconductor chip 30
The periphery of the inner connection portion 18a and the gold wire 22 was sealed with a semiconductor potting resin (HIR3000, manufactured by Hitachi Chemical Co., Ltd.) for the purpose of moisture proof and protection. The seal is
A vacuum differential pressure printing method was used using a vacuum differential pressure printing device (model number: VD-1000) manufactured by Toray Engineering Co., Ltd.

【００７８】真空差圧印刷装置ＶＤ−１０００の真空容
器内に図１３の被封止品、図１３の２３に示すメタル印
刷マスク及び封止樹脂ＨＩＲ−３０００をセットし、５
Ｔｏｒｒに減圧後１回目の印刷を行った。この状態での
断面観察の結果、図１４の２６ａ、２６ｂの周辺に空洞
部が見られた。In the vacuum container of the vacuum differential pressure printing apparatus VD-1000, the article to be sealed in FIG. 13, the metal print mask and the sealing resin HIR-3000 shown in FIG.
The first printing was performed after decompression in Torr. As a result of cross-sectional observation in this state, a cavity was found around 26a and 26b in FIG.

【００７９】次に真空容器を１５０Ｔｏｒｒにして断面
観察したところ、図１５に示すように空洞部は樹脂で埋
まり、３１の印刷した樹脂の表面に窪みが発生した。１
５０Ｔｏｒｒのまま２回目の印刷を行い窪みを埋めた後
（図１６）、大気圧に戻し、メタル印刷マスクを取外
し、被印刷品を真空差圧印刷装置から取りだし、１２０
°C、１８０°Cの乾燥炉で各１時間加熱した。Next, when the cross section of the vacuum vessel was observed at 150 Torr, as shown in FIG. 15, the cavity was filled with the resin, and a depression was generated on the surface of the printed resin 31. 1
After the second printing was performed at 50 Torr to fill the depressions (FIG. 16), the pressure was returned to the atmospheric pressure, the metal print mask was removed, and the article to be printed was removed from the vacuum differential pressure printing apparatus.
Each was heated for 1 hour in a drying furnace at 180 ° C and 180 ° C.

【００８０】乾燥後の製品の断面観察結果は、図１７に
示すように２６ａ、２６ｂを含めて封止内部に空洞、気
泡等が見られず、又、封止樹脂の表面もほぼ平滑で良好
な封止状態が得られていた。As shown in FIG. 17, the cross-sectional observation results of the product after drying include no voids or bubbles inside the sealing including 26a and 26b, and the surface of the sealing resin is almost smooth and good. A good sealing state was obtained.

【００８１】次に外部接続部１８ｃにフラックスをディ
スペンス塗布し、はんだボールを搭載し、窒素雰囲気炉
でボールをリフローさせて外部接続端子２９を形成した
（図１８）。Next, a flux was dispensed to the external connection portion 18c, solder balls were mounted, and the balls were reflowed in a nitrogen atmosphere furnace to form external connection terminals 29 (FIG. 18).

【００８２】本実施例では打抜き加工した接着材単体フ
ィルムを用いたが、他に、接着材のワニスをＰＥＴ（ポ
リエチレンテレフタレート）フィルム、ＯＰＰ（延伸ポ
リプロピレン）フィルム、ＴＰＸ（メチルペンテンコポ
リマ）フィルム等の離型性シート上に塗布し、フィルム
化した２層構成のものを用意し、打抜き加工し、半導体
チップ支持基板に接着し、離型性シートをはく離する方
法でもよい。また、他に接着材のワニスを離型性シート
の所定パターンに印刷により形成し、半導体チップ支持
基板に接着し、離型性シートをはく離する方法でもよ
い。接着材のワニスを直接に半導体チップ支持基板に印
刷し、半硬化させる等の方法を用いてもよい。In this embodiment, a single-piece adhesive material film punched was used. Alternatively, a varnish of an adhesive material such as a PET (polyethylene terephthalate) film, an OPP (stretched polypropylene) film, a TPX (methyl pentene polymer) film, or the like may be used. A method of preparing a two-layered film that is applied on a release sheet and formed into a film, punched, adhered to a semiconductor chip supporting substrate, and peeled off the release sheet may be used. Alternatively, a method of forming a varnish of an adhesive on a predetermined pattern of a release sheet by printing, bonding the varnish to a semiconductor chip supporting substrate, and releasing the release sheet may be used. A method of printing a varnish of the adhesive directly on the semiconductor chip supporting substrate and semi-curing it may be used.

【００８３】これらの方法を用いることによって、半導
体チップ支持基板の開口部に対して精度よく、接着材の
開口部を設けることができる。By using these methods, it is possible to accurately provide an opening for the adhesive with respect to the opening for the semiconductor chip supporting substrate.

【００８４】また、本実施例の説明図では個々のピース
の断面図で説明したが、これらの工程は最終的に複数の
ピースを含む一連のチップ搭載用基板を用意し、最終工
程または途中工程で分離することも可能である。分離に
は、打抜き加工、ウェハー切断に使用されるダイサー、
ルータ加工、レーザ加工等が用いられる。Further, in the explanatory view of this embodiment, a cross-sectional view of each piece has been described. However, in these steps, a series of chip mounting substrates including a plurality of pieces is finally prepared, and the final step or an intermediate step is performed. It is also possible to separate them. For separation, dicing used for punching and wafer cutting,
Router processing, laser processing, or the like is used.

【００８５】本実施例に示した方法で半導体チップと外
部接続端子間の電気接続チェック可能な半導体装置を導
通検査正常品３０ピース作製し、吸湿リフロー試験を実
施した。吸湿（温度８５°Ｃ、湿度８５％ＲＨ、１６８
時間）後、赤外線リフロー（最高温度２４５°Ｃ）によ
り導通異常の発生有無をチェックした。３０ピース全て
の導通を確認し、外観等にも異常を認めなかった。According to the method shown in the present embodiment, 30 pieces of semiconductor devices which can check the electrical connection between the semiconductor chip and the external connection terminals were manufactured as normal continuity test pieces, and the moisture absorption reflow test was performed. Moisture absorption (temperature 85 ° C, humidity 85% RH, 168
After this time, the presence or absence of a conduction abnormality was checked by infrared reflow (at a maximum temperature of 245 ° C.). The conduction of all 30 pieces was confirmed, and no abnormality was observed in the appearance and the like.

【００８６】比較例として、実施例と同じ材料、工程を
用いて接着材の開口部が半導体チップ支持基板の開口部
に比べて小さな半導体装置を３０ピース作製した。ここ
で、両者の開口部の輪郭間の距離は約５０μｍとなるよ
うにした。これについても実施例と同時に試験を実施し
たが、３０ピース中３０ピースに断線不良が発生した。As a comparative example, using the same material and process as in the example, 30 pieces of a semiconductor device in which the opening of the adhesive was smaller than the opening of the semiconductor chip supporting substrate were manufactured. Here, the distance between the contours of both openings was set to be about 50 μm. This was also tested at the same time as the example, but a disconnection failure occurred in 30 pieces out of 30 pieces.

【００８７】[0087]

【発明の効果】本発明によれば、半導体チップ支持基板
の一方の面（Ａ面）に接着材層を介して半導体チップが
搭載されており、前記半導体チップ支持基板及び前記接
着材の前記半導体チップのパッド位置に対応する個所に
複数の開口部が設けられており、前記半導体チップ支持
基板の他方の面（Ｂ面）にインナー接続部及び外部接続
部が設けられており、前記半導体チップのパッドは前記
開口部を経由するボンディングワイヤによりインナー接
続部と接続されており、前記開口部に封止材が充填され
ている半導体装置において、前記開口部をワイヤボンデ
ィング接合に必要最小限の大きさとすることによって、
水平方向のサイズを抑え、より高密度な実装を可能とし
た半導体装置が実現する。According to the present invention, a semiconductor chip is mounted on one surface (A surface) of a semiconductor chip supporting substrate with an adhesive layer interposed therebetween, and the semiconductor chip supporting substrate and the semiconductor of the adhesive are mounted. A plurality of openings are provided at locations corresponding to pad positions of the chip, and an inner connection portion and an external connection portion are provided on the other surface (B surface) of the semiconductor chip support substrate. The pad is connected to the inner connection portion by a bonding wire passing through the opening, and in the semiconductor device in which the opening is filled with a sealing material, the opening has a minimum size necessary for wire bonding. By,
A semiconductor device with a reduced horizontal size and higher-density mounting is realized.

【００８８】さらに、本発明によれば、開口部の開口面
積を削減することで、充填すべき開口空間の体積を減少
させることができるため、該開口部分の封止に必要とな
る封止材の充填量をより少なくすることができる。Further, according to the present invention, since the volume of the opening space to be filled can be reduced by reducing the opening area of the opening, the sealing material necessary for sealing the opening is required. Can be further reduced.

【００８９】さらに、本発明によれば、封止材形成工程
で真空差圧印刷方法を用いることにより、ボンディング
ワイヤー周囲のみならず、接着材の開口部周囲の半導体
チップと半導体チップ支持基板との間隙をボイドなく封
止材を充填させることができるため、より信頼性の高い
樹脂封止が可能となる。Further, according to the present invention, by using the vacuum differential pressure printing method in the encapsulant forming step, not only the periphery of the bonding wire but also the semiconductor chip and the semiconductor chip supporting substrate around the opening of the adhesive are formed. Since the gap can be filled with the sealing material without voids, more reliable resin sealing can be achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施形態における半導体装置の
断面構成を示す断面図である。FIG. 1 is a cross-sectional view illustrating a cross-sectional configuration of a semiconductor device according to a first embodiment of the present invention.

【図２】本発明の第２の実施形態における半導体装置の
断面構成を示す断面図である。FIG. 2 is a cross-sectional view illustrating a cross-sectional configuration of a semiconductor device according to a second embodiment of the present invention.

【図３】本発明の第３の実施形態における半導体装置の
断面構成を示す断面図である。FIG. 3 is a cross-sectional view illustrating a cross-sectional configuration of a semiconductor device according to a third embodiment of the present invention.

【図４】第３の実施形態における半導体装置の開口部の
概略構成の一例を示す上面図である。FIG. 4 is a top view illustrating an example of a schematic configuration of an opening of a semiconductor device according to a third embodiment.

【図５】第３の実施形態における半導体装置の開口部の
概略構成の他の例を示す上面図である。FIG. 5 is a top view illustrating another example of the schematic configuration of the opening of the semiconductor device according to the third embodiment.

【図６】本発明による半導体装置の製造工程における断
面構成例を示す断面図である。FIG. 6 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図７】本発明による半導体装置の製造工程における断
面構成例を示す断面図である。FIG. 7 is a sectional view showing an example of a sectional configuration in a manufacturing process of the semiconductor device according to the present invention.

【図８】本発明による半導体装置の製造工程における断
面構成例を示す断面図である。FIG. 8 is a sectional view showing an example of a sectional configuration in a manufacturing process of the semiconductor device according to the present invention.

【図９】本発明による半導体装置の製造工程における断
面構成例を示す断面図である。FIG. 9 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図１０】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 10 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図１１】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 11 is a sectional view showing an example of a sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図１２】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 12 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図１３】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 13 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図１４】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 14 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing process of a semiconductor device according to the present invention.

【図１５】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 15 is a sectional view showing an example of a sectional configuration in a manufacturing process of the semiconductor device according to the present invention.

【図１６】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 16 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing step of a semiconductor device according to the present invention.

【図１７】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 17 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing step of a semiconductor device according to the present invention.

【図１８】本発明による半導体装置の製造工程における
断面構成例を示す断面図である。FIG. 18 is a cross-sectional view showing an example of a cross-sectional configuration in a manufacturing step of a semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

１…半導体チップ支持基板、２…配線基板、３…半導体
チップ、４…半導体チップのパッド、５…接着材、６…
半導体チップ支持基板の開口部、７…配線、７ａ…イン
ナー接続部、７ｃ…外部接続部、８…マスク樹脂、１０
…外部接続端子、１１…ボンディングワイヤ、１２…封
止材、１３…封止ダム、１４…接着材層の開口部、１５
…銅張り積層板、１６ａ、１６ｂ…銅箔、１７…ガラス
クロスエポキシ材、１８…配線、１８ａ…インナー接続
部、１８ｃ…外部接続部、２２…金線、２３…メタル印
刷マスク、２６ａ、２６ｂ…接着材層に形成された開口
部、２８…半導体チップのパッド部。DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip support substrate, 2 ... Wiring board, 3 ... Semiconductor chip, 4 ... Semiconductor chip pad, 5 ... Adhesive, 6 ...
Opening of semiconductor chip supporting substrate, 7: wiring, 7a: inner connection, 7c: external connection, 8: mask resin, 10
... external connection terminals, 11 ... bonding wires, 12 ... sealing material, 13 ... sealing dam, 14 ... openings in the adhesive layer, 15
... copper-clad laminate, 16a, 16b ... copper foil, 17 ... glass cloth epoxy material, 18 ... wiring, 18a ... inner connection part, 18c ... external connection part, 22 ... gold wire, 23 ... metal print mask, 26a, 26b ... openings formed in the adhesive layer, 28 ... pad portions of the semiconductor chip.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴木 和久 東京都港区芝浦四丁目９番25号 芝浦スク エアビル 日立化成工業株式会社内 Ｆターム(参考） 5F044 AA02 AA05 AA07 JJ03 5F061 AA01 BA04 CA04 CA06  ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazuhisa Suzuki 4-9-1 Shibaura, Minato-ku, Tokyo Shibaura Suku Air Building Hitachi Chemical Co., Ltd. F-term (reference)

Claims (14)

【特許請求の範囲】[Claims] 【請求項１】半導体チップ支持基板の一方の面にインナ
ー接続部及び外部接続部が設けられ、他方の面に複数の
パッドを有する半導体チップが搭載された半導体装置に
おいて、 前記半導体チップのパッド位置に対応する前記半導体チ
ップ支持基板上の個所に複数の開口部が形成され、該複
数の開口部の各々を経由するボンディングワイヤにより
該半導体チップのパッドと前記インナー接続部とが接続
されるものであって、 前記開口部及び前記ボンディングワイヤを含む領域に封
止材が形成されていることを特徴とする半導体装置。1. A semiconductor device in which an inner connection portion and an external connection portion are provided on one surface of a semiconductor chip supporting substrate and a semiconductor chip having a plurality of pads is mounted on the other surface, wherein a pad position of the semiconductor chip is provided. A plurality of openings are formed at locations on the semiconductor chip supporting substrate corresponding to the plurality of semiconductor chips, and pads of the semiconductor chip and the inner connection portions are connected by bonding wires passing through each of the plurality of openings. And a sealing material is formed in a region including the opening and the bonding wire. 【請求項２】前記封止材を真空差圧印刷方法により形成
するための封止ダムとして機能する部材をさらに有する
ことを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, further comprising a member functioning as a sealing dam for forming said sealing material by a vacuum differential pressure printing method. 【請求項３】前記開口部の大きさは、該開口部を経由す
るワイヤボンディング接続を実施するために必要最小限
の大きさ、または、該必要最小限の大きさに対応して設
定された大きさであることを特徴とする請求項１または
２に記載の半導体装置。3. The size of the opening is set to a minimum size necessary for performing a wire bonding connection through the opening, or set in accordance with the minimum size. The semiconductor device according to claim 1, wherein the semiconductor device has a size. 【請求項４】前記開口部は、搭載されるべき半導体チッ
プの複数のパッドの各々にそれぞれ対応するよう個別に
形成されていることを特徴とする請求項１または２に記
載の半導体装置。4. The semiconductor device according to claim 1, wherein said openings are individually formed so as to respectively correspond to a plurality of pads of a semiconductor chip to be mounted. 【請求項５】前記開口部が長方形状で、その短辺の開口
サイズが０．１ｍｍ以上１．０ｍｍ以下であることを特
徴とする請求項１または２に記載の半導体装置。5. The semiconductor device according to claim 1, wherein said opening has a rectangular shape, and an opening size of a short side thereof is 0.1 mm or more and 1.0 mm or less. 【請求項６】前記開口部が円形状で、その開口径が０．
１ｍｍ以上１．０ｍｍ以下であることを特徴とする請求
項１または２に記載の半導体装置。6. The method according to claim 6, wherein the opening has a circular shape and the diameter of the opening is 0.
The semiconductor device according to claim 1, wherein the length is 1 mm or more and 1.0 mm or less. 【請求項７】前記半導体チップ支持基板が繊維基材と樹
脂で構成された複合体を備えて構成されたものであるこ
とを特徴とする請求項１または２に記載の半導体装置。7. The semiconductor device according to claim 1, wherein the semiconductor chip supporting substrate is provided with a composite composed of a fiber base material and a resin. 【請求項８】前記半導体チップ支持基板の一方の面には
凹部が形成されており、該凹部の底部に前記開口部が位
置していることを特徴とする請求項１または２に記載の
半導体装置。8. The semiconductor according to claim 1, wherein a concave portion is formed on one surface of the semiconductor chip supporting substrate, and the opening is located at a bottom of the concave portion. apparatus. 【請求項９】前記半導体チップは前記半導体チップ支持
基板に接着材層を介して搭載されるものであり、 前記半導体チップ支持基板の開口部に対応する前記接着
材層の位置に、該半導体チップ支持基板の開口部よりも
開口面積が大きい開口部が設けられていることを特徴と
する請求項１〜８のいずれかに記載の半導体装置。9. The semiconductor chip is mounted on the semiconductor chip supporting substrate via an adhesive layer, and the semiconductor chip is provided at a position of the adhesive layer corresponding to an opening of the semiconductor chip supporting substrate. The semiconductor device according to claim 1, wherein an opening having an opening area larger than an opening of the support substrate is provided. 【請求項１０】一方の面にインナー接続部及び外部接続
部が設けられ、他方の面に複数のパッドを有する半導体
チップが搭載される半導体チップ支持基板において、 前記搭載されるべき半導体チップのパッドに対応する位
置に、該パッドと前記インナー接続部をワイヤボンディ
ングするための複数の開口部が形成され、 前記開口部を囲む領域に封止材を真空差圧印刷方法で形
成するための封止ダムが形成されていることを特徴とす
る半導体チップ支持基板。10. A semiconductor chip supporting substrate provided with an inner connection portion and an external connection portion on one surface and a semiconductor chip having a plurality of pads on the other surface, wherein the pad of the semiconductor chip to be mounted is provided. A plurality of openings for wire bonding the pad and the inner connection portion are formed at positions corresponding to the above, and sealing for forming a sealing material in a region surrounding the opening by a vacuum differential pressure printing method. A semiconductor chip support substrate, wherein a dam is formed. 【請求項１１】前記開口部の大きさは、該開口部を経由
するワイヤボンディング接続を実施するために必要最小
限の大きさ、または、該必要最小限の大きさに対応して
設定された大きさであることを特徴とする請求項１０に
記載の半導体チップ支持基板。11. The size of the opening is set to a minimum size necessary for performing wire bonding connection through the opening, or set in accordance with the minimum size. The semiconductor chip supporting substrate according to claim 10, wherein the substrate has a size. 【請求項１２】半導体チップ支持基板の一方の面にイン
ナー接続部及び外部接続部が設けられ、他方の面に複数
のパッドを有する半導体チップが搭載された半導体装置
の製造方法において、 前記半導体チップの複数のパッド位置に対応する前記半
導体チップ支持基板の位置に複数の開口部を形成する工
程と、 前記複数の開口部の各々を経由するボンディングワイヤ
により前記半導体チップのパッドと前記インナー接続部
とを接続する工程と、 前記開口部及び前記ボンディングワイヤを含む領域に封
止材を形成する工程とを備え、 前記封止材を充填する工程では、真空差圧印刷方法を用
いて封止材が形成されることを特徴とする半導体装置の
製造方法。12. A method of manufacturing a semiconductor device in which an inner connection portion and an external connection portion are provided on one surface of a semiconductor chip supporting substrate and a semiconductor chip having a plurality of pads is mounted on the other surface. Forming a plurality of openings at positions of the semiconductor chip supporting substrate corresponding to the plurality of pad positions, and bonding the semiconductor chip pads and the inner connection portion with bonding wires passing through each of the plurality of openings. And a step of forming a sealing material in a region including the opening and the bonding wire. In the step of filling the sealing material, the sealing material is formed using a vacuum differential pressure printing method. A method for manufacturing a semiconductor device, characterized by being formed. 【請求項１３】前記開口部の大きさが、該開口部を経由
するワイヤボンディング接続を実施するために必要最小
限の大きさ、または、該必要最小限の大きさに対応して
設定された大きさであることを特徴とする請求項１２に
記載の半導体装置の製造方法。13. The size of the opening is set to a minimum size necessary for performing a wire bonding connection through the opening, or to correspond to the minimum size. 13. The method according to claim 12, wherein the size is a size. 【請求項１４】前記開口部を形成する工程は、レーザ加
工によって開口する工程を含むことを特徴とする請求項
１２に記載の半導体装置の製造方法。14. The method of manufacturing a semiconductor device according to claim 12, wherein the step of forming the opening includes a step of opening by laser processing.
JP28736099A 1999-10-07 1999-10-07 Semiconductor device, semiconductor support substrate which is used for that and manufacturing method of semiconductor device Pending JP2001110838A (en)

Priority Applications (1)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008519426A (en) * 2005-04-12 2008-06-05 シム テック カンパニー リミティッド Window processing method for printed circuit board for semiconductor package
JP4489137B1 (en) * 2009-01-20 2010-06-23 パナソニック株式会社 Circuit module and electronic device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008519426A (en) * 2005-04-12 2008-06-05 シム テック カンパニー リミティッド Window processing method for printed circuit board for semiconductor package
JP4701248B2 (en) * 2005-04-12 2011-06-15 シム テック カンパニー リミティッド Slot processing method for printed circuit board for semiconductor package
JP4489137B1 (en) * 2009-01-20 2010-06-23 パナソニック株式会社 Circuit module and electronic device
JP2010171082A (en) * 2009-01-20 2010-08-05 Panasonic Corp Circuit module and electronic equipment

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