JP2001102447A5 - - Google Patents

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Publication number
JP2001102447A5
JP2001102447A5 JP1999277922A JP27792299A JP2001102447A5 JP 2001102447 A5 JP2001102447 A5 JP 2001102447A5 JP 1999277922 A JP1999277922 A JP 1999277922A JP 27792299 A JP27792299 A JP 27792299A JP 2001102447 A5 JP2001102447 A5 JP 2001102447A5
Authority
JP
Japan
Prior art keywords
interlayer insulating
insulating film
film
metal
wiring groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1999277922A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001102447A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP27792299A priority Critical patent/JP2001102447A/ja
Priority claimed from JP27792299A external-priority patent/JP2001102447A/ja
Priority to US09/663,201 priority patent/US6399424B1/en
Publication of JP2001102447A publication Critical patent/JP2001102447A/ja
Publication of JP2001102447A5 publication Critical patent/JP2001102447A5/ja
Pending legal-status Critical Current

Links

JP27792299A 1999-09-30 1999-09-30 コンタクト構造の製造方法 Pending JP2001102447A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP27792299A JP2001102447A (ja) 1999-09-30 1999-09-30 コンタクト構造の製造方法
US09/663,201 US6399424B1 (en) 1999-09-30 2000-09-18 Method of manufacturing contact structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27792299A JP2001102447A (ja) 1999-09-30 1999-09-30 コンタクト構造の製造方法

Publications (2)

Publication Number Publication Date
JP2001102447A JP2001102447A (ja) 2001-04-13
JP2001102447A5 true JP2001102447A5 (enExample) 2006-10-26

Family

ID=17590164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27792299A Pending JP2001102447A (ja) 1999-09-30 1999-09-30 コンタクト構造の製造方法

Country Status (2)

Country Link
US (1) US6399424B1 (enExample)
JP (1) JP2001102447A (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001308179A (ja) 2000-04-25 2001-11-02 Sharp Corp 半導体装置の製造方法
JP4858895B2 (ja) * 2000-07-21 2012-01-18 富士通セミコンダクター株式会社 半導体装置の製造方法
US6689682B1 (en) * 2000-08-11 2004-02-10 Advanced Micro Devices, Inc. Multilayer anti-reflective coating for semiconductor lithography
US6713874B1 (en) * 2001-03-27 2004-03-30 Advanced Micro Devices, Inc. Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics
US7084070B1 (en) 2001-03-30 2006-08-01 Lam Research Corporation Treatment for corrosion in substrate processing
US20020177321A1 (en) 2001-03-30 2002-11-28 Li Si Yi Plasma etching of silicon carbide
JP5023413B2 (ja) * 2001-05-11 2012-09-12 ソニー株式会社 半導体装置およびその製造方法
US6555467B2 (en) * 2001-09-28 2003-04-29 Sharp Laboratories Of America, Inc. Method of making air gaps copper interconnect
US7226853B2 (en) * 2001-12-26 2007-06-05 Applied Materials, Inc. Method of forming a dual damascene structure utilizing a three layer hard mask structure

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62144342A (ja) 1985-12-19 1987-06-27 Oki Electric Ind Co Ltd 多層配線のコンタクトホ−ル形成方法
JP3348454B2 (ja) * 1993-02-05 2002-11-20 ソニー株式会社 酸化防止方法
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
JP3300643B2 (ja) 1997-09-09 2002-07-08 株式会社東芝 半導体装置の製造方法
JPH11251294A (ja) * 1998-02-27 1999-09-17 Sony Corp 半導体装置の製造方法
US6197696B1 (en) * 1998-03-26 2001-03-06 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
US6194128B1 (en) * 1998-09-17 2001-02-27 Taiwan Semiconductor Manufacturing Company Method of dual damascene etching
US6110648A (en) * 1998-09-17 2000-08-29 Taiwan Semiconductor Manufacturing Company Method of enclosing copper conductor in a dual damascene process
JP3657788B2 (ja) * 1998-10-14 2005-06-08 富士通株式会社 半導体装置及びその製造方法
US6187663B1 (en) * 1999-01-19 2001-02-13 Taiwan Semiconductor Manufacturing Company Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials
US6235653B1 (en) * 1999-06-04 2001-05-22 Taiwan Semiconductor Manufacturing Company Ar-based si-rich oxynitride film for dual damascene and/or contact etch stop layer
US6331479B1 (en) * 1999-09-20 2001-12-18 Chartered Semiconductor Manufacturing Ltd. Method to prevent degradation of low dielectric constant material in copper damascene interconnects

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