JP2000334146A - Game machine control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a high quality random number at random by shifting an initial value by prescribed bits in a prescribed direction through a bit shift means on the basis of an initial value stored in an initial value storage means and finding an exclusive OR on the basis of this shifted value and the initial value. SOLUTION: A game machine control circuit 1 is provided for generating the uniform random numbers of a prescribed probability and is equipped with a random number generation block 1a, a CPU 7 and a frequency dividing circuit 7a, or the like. The random number generation block 1a has a register 2 as an initial value storage means, a bit shifter 3 and an exclusive OR circuit 4. The bit shifter 3 shifts the initial value stored in the initial value storage means 2 by prescribed bits in the prescribed direction and the exclusive OR circuit 4 finds the exclusive OR of the value shifted by the bit shift means 3 and the initial value and obtains a random number as the arithmetic result. During a game, the CPU 7 determines a great success or stop picture pattern by using the generated random number.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a game machine control circuit, and more particularly to a game machine control circuit for generating random numbers used in a game.

[Background of the Invention] In recent years, in gaming machines, for example, pachinko gaming machines, the interest in gaming has been enhanced by a variable display game on a special symbol display device arranged substantially at the center of the gaming area.

[0003] In this variable display game, for example, when a predetermined game condition is satisfied (usually at the time of winning a prize at a starting port).
In general, the symbol displayed in the special symbol display device starts to change display, and the change stops after a predetermined time, and it is general that a case where the symbols at the time of stop are aligned with a specific symbol is a big hit. In such a variable display game, the determination of a jackpot or the design at the time of stopping (hereinafter referred to as a “stop design”) incorporates a stochastic element, and is accompanied by contingency. I have.

For this reason, random numbers (uniformity random numbers and random symbols for determining stop symbols) with uniformity and irregularity are used for determining a jackpot and determining a stop symbol. The random number is generated by the gaming machine control circuit.

[0005]

2. Description of the Related Art Conventionally, as a gaming machine control circuit for generating such a random number, there is a jackpot determination device provided with a digit rising counter as shown in FIG.

FIG. 8 is a diagram for explaining the operation of the jackpot determination device.

The jackpot judging device shown in FIG.
The jackpot is controlled by a digit rising counter in which the values of “〜” to “234” are constantly moving at a high speed one by one at regular intervals. This is the case where the determined winning value is one (in this case, “03”), and as a result, the jackpot probability is 1/25.

[0008] By the way, the timing at which the jackpot determination is made is generally at the time of winning the starting opening of the game ball.
The time required to move one frame of the digit rising counter is as short as 0.004096 seconds, for example, and the cycle time is 0.96256 seconds (= 0.004).
096 × 235), which is sufficiently short, and is used as a random number.

[0009]

A random number is a variable that does not have any regularity in how values change, and its original meaning is a sequence in which the next value cannot be predicted. .

However, the random number generated by the above-mentioned digit rising counter is such that the timing of selecting the value of the counter (for example, at the time of winning the starting opening) is random and the cycle of the counter is short. Therefore, the value generated by the digit-increase counter is used as a random number, and a regular arithmetic sequence having a regular value added by a certain value (one by one in the above example) is added to the value. Strictly speaking, it cannot be called a random number.

That is, it is preferable that the random numbers serving as sources of contingency that excite the interest in the game in the variable display game are statistically independent numbers.

[Purpose] The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine control circuit which can be applied to a gaming machine to generate and store high-quality random numbers.

[0013]

As shown in FIG. 1, the invention described in claim 1 controls a game in a gaming machine and includes a random number generating means for generating a random number used in the game. In the machine control circuit 1, the random number generating means includes an initial value storage means 2 for storing a preset arbitrary value as an initial value, and an initial value stored in the initial value storage means 2 for a predetermined number of bits. A bit shift means 3 for shifting in the direction, and a logical operation means 4 for obtaining an exclusive OR of the value shifted by the bit shift means 3 and the initial value. The random number generating means (step S15) is provided before the winning detection processing means (step S15) for detecting the winning of a game ball to the starting port (first type starting port 15) of the gaming machine as a condition for capturing the random number obtained. 10) to constitute an interrupt processing section (steps S1 to S28), and to execute a series of interrupt processing of the interrupt processing section at predetermined time intervals to generate a new random number. Have achieved.

In this case, in addition to the invention described in claim 1, as described in claim 2, the bit operation by the bit shift means and the logical operation by the logical operation means are paired and performed a plurality of times. It is effective to perform the repetitive processing, and in this case, as described in claim 3,
It is preferable to change the shift direction for each repetition processing by the bit shift means.

Further, in addition to the invention described in claim 1, 2, or 3, the bit shift amount by the bit shift means is generated when the bit shift means shifts to the left. 1/100 of the number of bits required for the random number to be
When shifting to the right by the number of bits obtained by adding 1 to the number of bits of 2, and shifting to the right, it is possible to shift the bit by the number obtained by subtracting 1 from the number of bits required for a random number to be generated. It is valid.

[0016]

According to the first aspect of the present invention, the initial value is shifted by a predetermined number of bits in a predetermined direction by the bit shift means based on the initial value stored in the initial value storage means. The exclusive logic is obtained by the logic operation means based on the value, so that a high-quality random number is generated as compared with the conventional digit rising counter.

The random number generation means is arranged before the prize detection processing means for detecting a prize of a game ball to the starting port of the gaming machine as a condition for taking in the random number obtained as a result of the operation of the logical operation means. To generate a new random number by executing a series of interrupt processing of the interrupt processing unit at predetermined time intervals, so that a new generated random number is generated based on the execution of the interrupt processing unit. The random number can be stored during execution of the interrupt processing unit. In other words, since the random number generated by the execution of the interrupt processing unit is not acquired (stored) at the next execution of the interrupt processing unit, the random number can be acquired in synchronization with the prize winning timing (the random number acquisition timing for the prize) No deviation). In addition, random numbers can be obtained in a high quality state.

In this case, according to the second aspect of the present invention,
The bit operation by the bit shift means and the logical operation by the logical operation means form a pair, and the repetition processing is performed a plurality of times. Is done.

According to the third aspect of the present invention, the shift direction is changed for each repetition processing by the bit shift means.
High quality random numbers are generated.

According to the fourth aspect of the present invention, when the bit shift means shifts to the left, the bit shift amount is one of the number of bits required for a random number to be generated.
The bit is shifted by the number obtained by adding 1 to the bit number of / 2,
In the case of shifting to the right, a bit is shifted by a number obtained by subtracting 1 from the number of bits required for a random number to be generated, thereby adding to the invention according to claim 1, 2 or 3. Thus, a high-quality random number is generated.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to FIGS. 2 to 7
In FIG. 7, the same parts as those in FIG.

First, the configuration of the present embodiment will be described.

FIG. 2 shows a gaming machine control circuit 1 according to the present embodiment.
It is a front view of the game board 10 in the pachinko gaming machine using the game.

As shown in FIG. 2, a guide rail 11 is provided on the surface of the game board 10 of the pachinko game machine according to the present embodiment.
A special symbol display device 13 for performing a variable display game is provided at a substantially central portion of the gaming region 12, and a special symbol display device 1 is provided.
A variable winning device (large winning opening) 14 for causing a special game to be played when a big hit occurs in the variable display game on the special symbol display device 13 is provided below the third symbol 3.

A first-type starting port (starting port) 15 is provided above the variable winning device (large winning port) 14.

The variable display game on the special symbol display device 13 is performed by a game ball launching device (not shown).
On the condition that the game ball guided into 2 wins the first kind starting port 15, three symbols of the left symbol, the middle symbol, and the right symbol, which are displayed in the special symbol display device 13, are changed. At the start, after a predetermined time (after elapse of 5 seconds or more), the left symbol, the right symbol, and the middle symbol stop changing in the order, and when the three symbols are aligned with the specific symbol at the time of the stop, it is a big hit. The determination of the jackpot, the determination of the stop symbol, and the like are performed based on random numbers generated by the gaming machine control circuit 1, thereby incorporating a stochastic element with randomness in the variable display game to enhance the interest in the game. It is.

FIG. 3 is a block diagram showing a main configuration of a pachinko gaming machine including the gaming machine control circuit 1 in the present embodiment.

Referring to FIG. 3, a pachinko gaming machine according to the present embodiment includes a gaming machine control circuit 1, a first-type start switch 21, a continuation switch 22, a count switch 23, a low-pass filter 24, a buffer gate 25, and an output port 2.
6, a driver 27, and a variable winning device (large winning opening) 14. In addition, in FIG. 3, B is a bus.

The gaming machine control circuit 1 is for generating a uniform random number having a predetermined probability (in the present embodiment, a probability of 1/245), and a random number generating block 1a as random number generating means. (Step S10 in FIG. 6), the CPU (Cent
ral Processing Unit) 7, frequency divider 7a, ROM (Re
ad Only Memory) 8, RAM (Random Access Memory)
The random number generation block 1a includes a register 2 as initial value storage means, a bit shifter 3 as bit shift means, and an exclusive OR circuit 4 as logic operation means. In addition, the gaming machine control circuit 1 outputs various information such as winning in the first type start-up port 15, starting a variable display game, and jackpots in the variable display game to the management device of the hall (game store). It also has the function of performing

The register 2 is for storing an initial value for generating a random number in the present embodiment. Specifically, the initial value stored in the register 2 in the present embodiment is a CPU 7 at the time of startup. Drives the counter, the counter value is read at a predetermined timing, and the remainder obtained by dividing the read value by “245” (the value based on the jackpot occurrence probability in the present embodiment) is set as the initial value. It is memorized.

The bit shifter 3 shifts the 8-bit value stored in the register 2 by 5
Bit shift is performed, and "0" is written in the lower 5 bits after the shift. In addition, at the time of digit lowering shift, 3 bits are shifted rightward, and "0" is written in the upper 3 bits after the shift. The shift value is output to the exclusive OR circuit 4.

The exclusive OR circuit 4 comprises an exclusive OR gate 5 and a remainder operation circuit 6. The exclusive OR gate 5 stores the 8-bit shift value input from the bit shifter 3 and the register 2 to store the shift value. An exclusive OR with the 8-bit initial value is calculated.
And outputs the remainder as a random number value by dividing the output value from by a predetermined number (in this case, “245” based on the jackpot probability). This is because the output value from the exclusive OR gate 5 is 8 bits, so that “0” to “25”
Although it is a numerical value up to 5 ", since the jackpot probability in this embodiment is 1/245," 0 "to" 244 "
This is for rounding values from “245” to “255”.

Incidentally, the bit shift processing by the bit shifter 3 and the exclusive OR processing by the exclusive OR gate 5 in the exclusive OR circuit 4 in this embodiment are processed as a pair, and the processing result is stored in the register 2.
, And repeating the bit shift processing and the exclusive OR processing again, it is possible to improve the randomness of the random numbers.

The CPU 7 is an 8-bit microprocessor serving as a center of the gaming machine control circuit 1 for controlling other various circuits, and performs a reset interrupt process (corresponding to an interrupt processing unit) based on a reset signal described later. Various types of program processing are executed based on the program processing procedure stored in the ROM 8 in units of one sequence. When a random number used for a game is required, a random number generation block 1
By controlling a, a random number is obtained.

The frequency dividing circuit 7a divides the frequency of the clock pulse output from the clock oscillator to generate a reset signal every 2 msec, and supplies this reset signal to the CPU 7.

The ROM 8 is a semiconductor memory for storing various control programs and data used by the CPU 7, and the RAM 9 stores program data and the like used during execution of program processing in the CPU 7,
This is a semiconductor memory that temporarily stores data related to a game and is used as a work area.

The variable winning device (large winning opening) 14 is opened at the time of the occurrence of a jackpot of the variable display game based on the winning timing to the first type starting opening 15 to give a player a special game opportunity, Gives many people the opportunity to win prize balls.

The first-type start switch 21 is provided in the first-type start port 15 and detects a winning of a game ball.

Continue switch 22 and count switch 2
Reference numeral 3 denotes a proximity switch provided in a variable winning device (large winning opening) 14.
The counting switch 23 detects a passing ball passing through a specific area (V zone) in the variable winning device (large winning opening) 14. It detects a sphere. Based on the detection signals from these switches 22 and 23, a 10-count fraud prevention process is performed.

The low-pass filter 24 receives output signals from the first-type start switch 21, the continuation switch 22, and the count switch 23, and also outputs from a discharge control circuit (not shown) for controlling discharge of game balls. The buffer gate 25 amplifies the pulse wave shaped by the low-pass filter 24 and outputs the amplified signal to the bus B.

The output port 26 outputs various signals input via the bus B to the driver 27. The driver 27 outputs, for example, a variable winning device based on the various signals input from the output port 26. It outputs a drive control signal for driving the (large winning opening) 14, and also outputs a jackpot signal, a special figure turning signal, a starting opening winning signal, and a special symbol display, for example, to be output to a management device or the like on the hall side. Device 13
And other control signals, such as a data signal, a control code signal, and a strobe signal to be output to a control circuit (not shown), a transmission clock signal, and a prize ball data signal to be output to an ejection control circuit (not shown).

FIG. 4 is a block diagram showing a main configuration of a pachinko gaming machine including a gaming machine control circuit 1 replacing FIG.

That is, in the example shown in FIG. 3, the register 2, the bit shifter 3, and the exclusive OR circuit 4 are independently provided as the random number generation block 1a. However, in the example shown in FIG. As described above, the CPU 7 may be configured to have the functions of the register 2, the bit shifter 3, and the exclusive OR circuit 4, and in this case, the CPU 7
At the time of startup, the internal counter is driven, this counter value is read at a predetermined timing, and the read value is set to “24”.
The remainder obtained by dividing by 5 "is used as an initial value. This initial value is bit-shifted in a predetermined direction, and a value obtained by performing a logical operation process by an exclusive OR of the shift value and the initial value is expressed by" 245 ". A uniform random number is generated by outputting the remainder as a random value.

Next, the operation (operation) of this embodiment will be described.

In the above configuration, first, a game ball fired from a game ball launching device (not shown) by operating a steering wheel is guided by a guide rail 11 and launched into a game area 12 in a game board 10.

The gaming machine control circuit 1 monitors the presence or absence of the input of the first type start switch 21, and when a game ball wins the first type start port 15, the first type start switch 21 controls the game ball. When a winning is detected, chattering of the detection signal is removed, logical conversion, and the like are performed to perform input processing. When a winning of a game ball is detected in the first-type starting port 15, the number of winning game balls up to four is stored in a predetermined storage area (hereinafter referred to as a holding area), The value of the random number at the time of winning used in the variable display game is also temporarily stored in the holding area (step S15 in FIG. 6 as winning detecting processing means). Incidentally, the random number for determining the big hit in the variable display game is generated by the random number generation block 1a in the gaming machine control circuit 1.

Then, the variable display game is started on the special symbol display device 13 based on the storage of the winning of the game ball into the first kind starting port 15, that is, on the data stored in the holding area.

In the variable display game process, the gaming machine control circuit 1 includes, for example, a normal operation process, an automatic stop time end monitoring process, a first symbol stop monitoring process, a second symbol stop monitoring and a reach determination process, The three types of processing, such as symbol stop monitoring processing, symbol determination processing, operation end monitoring processing, losing operation processing, and jackpot operation processing, are executed.

In this case, similarly to the above-described determination of the jackpot, the stop symbol in the variable display game is also determined by the random number generated by the random number generation block 1a in the gaming machine control circuit 1.

FIG. 5 is a view showing each symbol display area A, B, C in the special symbol display device 13.

The above-mentioned holding area is provided in the RAM 9 of the gaming machine control circuit 1, and this holding area is
As shown in (1), as a storage area of the stop symbol corresponding to each of the symbol display areas A, B, C in the special symbol display device 13, it is sequentially updated every reset interrupt. Then, the data of each symbol is determined by the CPU 7 as to whether it is a big hit symbol or a lost symbol. Sometimes the R
It is stored in the loss storage area of AM9.

On the other hand, as described above, the gaming machine control circuit 1 determines whether the game is a hit or a loss based on the random number for determining the big hit, and in the case of a hit, the hit symbol stored in the big hit storage area is used. The stop symbol is determined, and in the case of a loss, the stop symbol is determined based on the loss symbol stored in the loss storage area.

The data relating to the special symbol display device 13 set in the variable display game processing is output to a display control circuit (not shown) by the display control processing.

FIGS. 6 and 7 are flowcharts showing a control processing procedure of the pachinko gaming machine by the gaming machine control circuit 1.

When the control process is started, first, initial information is set (for example, a stack pointer is set, access to the RAM 9 is permitted, a reset signal is cleared, and the like) (step S1). The value is read at a predetermined timing, and the remainder obtained by dividing the counter value by “245” is stored in the register 2 as an initial value.

Next, it is checked whether or not the power of the pachinko gaming machine is turned on for the first time (step S2). Here, when it is detected that power is supplied to the pachinko gaming machine by operating the power switch, the CPU 7 executes the operation. After the registers and RAM 9 to be used are initialized and a wait time, which is a time required to check the contents of the memory at power-on, is set (step S3).
The wait time is updated by the wait time processing (step S4), and the CPU 7 enters a state of waiting for an interrupt.

On the other hand, in the process of step S2,
If power-on is not detected, the memory including the RAM 9 is inspected, that is, the presence or absence of an abnormality in the memory is checked (step S5).
After the processing in steps S3 and S4, the CPU 7 enters a state of waiting for an interrupt.

If no abnormality is detected in the memory in the process of step S5, the gaming machine control circuit 1 controls the prize ball by a communication process regarding the prize ball data with the discharge control circuit (not shown). At the same time (step S6), a probability setting process for setting a jackpot probability in the variable display game is performed (step S7).

Next, it is checked whether or not the wait time at the time of turning on the power set in step S3 has expired (step S8). If the wait time has not expired, the CPU 7 goes through the processing in step S4. Is in a state of waiting for an interrupt, and when the wait time has expired, an output process for outputting the output data set in the various subroutine processes is performed (step S9) to determine a hit / loss in the variable display game. Next, a new random number is generated by the random number generation block 1a based on the initial value stored in the register 2, the random number is updated by a random number update process (step S10), and an input process is performed (step S11).

Hereinafter, a power failure monitoring process for monitoring a power supply voltage such as a lamp power supply or a solenoid power supply (step S12), and a count switch winning monitoring process (step S12).
13), continuation switch winning monitoring processing (step S1)
4) After the special symbol activation switch winning monitoring process (step S15) and the fraud monitoring process (step S16) in the first type starting port 15 are performed, the value of the event counter for efficiently processing each sequence is determined. The branching process is performed based on the result (step S17).

That is, when the counter value is "0", the voice synthesis processing (step S18), when the counter value is "1", the LED editing processing (step S19), and when the counter value is "2", the lamp editing processing is performed. Processing (step S20),
When the counter value is "3", the variable display game process (step S21), when the counter value is "4", the symbol control editing process (step S22), and when the counter value is "5", the data transfer process (step S21). S23) If the counter value is “6”, the external information editing process (step S24)
When the counter value is “7”, the input information control process (Step S25) is performed.

Next, display data setting processing for the display control circuit is performed (step S26), and the random number data used in the processing of step S21 is stored in the register 2 as a new initial value (step S2).
7) A sound editing output process is performed (step S28),
The CPU 7 enters a state of waiting for an interrupt.

Then, based on the above-mentioned reset signal, the CPU 7 returns from the state of waiting for an interrupt.

Hereinafter, generation of a specific random number in this embodiment will be described.

As described above, since the remainder of “245” is stored as the initial value stored in the register 2,
The value is between “0” and “244”.

Here, for example, if "3" (= "00000011B") is stored as the initial value stored in the register 2, the initial value in the register 2 is changed by the bit shifter 3 in the random number generation block 1a. For example, it is shifted leftward by 5 bits to “96” (= “01100
000B "), and the exclusive OR gate 5 in the exclusive OR circuit 4 then shifts the shift value" 01100000B "by the bit shifter 3 and the register 2
The exclusive OR with the initial value “00000011B” is calculated, and “99” (= “011000”) is obtained as the calculation result.
11B ″) is required.

The obtained value is stored in the register 2 again. Next, the operation value in the register 2 is shifted by, for example, three bits to the right by the bit shifter 3 to “1”.
2 "(=" 00001100B "). Then, the exclusive OR gate 5 in the exclusive OR circuit 4 shifts the shift value" 0000011 "by the bit shifter 3.
00B ”and the stored value“ 01100011 ”in the register 2
B ”and an exclusive OR operation is performed, and“ 1 ”is obtained as the operation result.
11 "(=" 01101111B ").

Here, since the value “111” output from the remainder operation circuit 6 via the exclusive OR gate 5 in the exclusive OR circuit 4 is smaller than 245, “1”
11 "is output as it is as a random number.

In the next random number generation, “111” is set as a new initial value, and “1” is first set by the bit shifter 3.
11 ”is shifted leftward by 5 bits to“ 224 ”(=
The exclusive OR gate 5 obtains the shift value “11100000B” by the bit shifter 3 and the initial value “01” in the register 2.
The exclusive OR with “101111B” is calculated, and “143” (= “10001111B”) is obtained as the calculation result.

Then, “143” is stored in the register 2, and “143” is shifted rightward by 3 bits to obtain “17” (= “00010001B”). As a result, an exclusive OR of the shift value “00010001B” by the bit shifter 3 and the stored value “10001111B” in the register 2 is calculated, and “158” (=
“01101111B”) is obtained, and the remainder operation circuit 6
"158" is obtained as it is as a random number output from. Hereinafter, similarly, a random number sequence as shown in [Table 1] is generated.

[Table 1] That is, the random number sequence obtained by the conventional digit rising counter shown in FIG. 8 is a regular arithmetic sequence,
In the present embodiment, a high-quality random number sequence with high randomness can be generated.

As described above, in the present embodiment,
Based on the initial value stored in the register 2, the bit shifter 3 shifts the initial value by a predetermined number of bits (5 or 3 bits in the present embodiment) in a predetermined direction, and based on the shifted value and the initial value. By obtaining exclusive logic by the exclusive OR gate 5, a high-quality random number can be generated as compared with a conventional digit rising counter.

Therefore, in the present embodiment, the probability of randomness in a gaming machine (pachinko gaming machine) can be further increased.

Although the invention made by the inventor has been specifically described based on the preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

For example, in the present embodiment, the bit shift amount by the bit shifter 3 is set to a shift amount of 5 or 3 bits for an 8-bit random value, but is limited to the numerical value in the present embodiment. Instead, it can be set arbitrarily in order to obtain high-quality random numbers.

In the present embodiment, the value obtained by the exclusive OR circuit 4 is used as the initial value of the next random number generation. However, the present invention is not limited to this, and the random number data obtained in the past is stored. In addition, an exclusive OR of a predetermined number of random number data picked up from the held random number data may be used as a new initial value.

Some specific CPUs have a register called a refresh register for refreshing the dynamic memory, and the data held in the refresh register is decremented at predetermined time intervals.

In a CPU having such a refresh register, if it is not necessary to consider the reproducibility of random numbers, the exclusive OR of the value obtained by the exclusive OR circuit 4 and the value of the refresh register is used. May be used as a new initial value.

In the above description, the case where the invention made mainly by the inventor is applied to a game machine control circuit in a pachinko game machine, which is a utilization field as a background, has been described. However, the present invention is not limited to this. Absent.

For example, the present invention can also be applied to the control of a game machine (pachicon) or the like which always keeps the start rate of a pachislot or a variable display game constant.

[0080]

According to the first aspect of the present invention, the initial value is shifted by a predetermined number of bits in a predetermined direction by the bit shift means based on the initial value stored in the initial value storage means.
By obtaining exclusive logic by the logic operation means based on the shift value and the initial value, it is possible to generate a high-quality random number as compared with a conventional digit rising counter.

Further, since the random number generating means is provided before the winning detecting means, the generated new random number can be stored during execution of the interrupt processing part based on the execution of the interrupt processing part. it can. As a result, when applied to a gaming machine, a generated high-quality random number can be held (stored) in that state in response to winning.

In this case, according to the second aspect of the present invention, the bit operation by the bit shift means and the logical operation by the logical operation means are paired to perform the repetitive processing a plurality of times. In addition to the invention, a random number with high randomness can be generated.

According to the third aspect of the present invention, a high-quality random number can be generated in addition to the second aspect of the present invention by changing the shift direction for each repetition processing by the bit shift means. .

Further, in the invention according to claim 4, when the bit shift means shifts to the left, the bit shift amount is １ ／ of the number of bits required for a random number to be generated.
In the case of shifting to the right by the number of bits obtained by adding 1 to the number of bits of the above, the bit is shifted by the number obtained by subtracting 1 from the number of bits of １ ／ of the number of bits required for the random number to be generated. In addition to the first, second, or third aspect of the invention, a high-quality random number can be generated.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a gaming machine control circuit according to the present invention.

FIG. 2 is a front view of a gaming board in a pachinko gaming machine using the gaming machine control circuit of the present embodiment.

FIG. 3 is a block diagram illustrating a main configuration of a pachinko gaming machine including a gaming machine control circuit according to the present embodiment.

FIG. 4 is a block diagram showing a main configuration of a pachinko gaming machine including a gaming machine control circuit replacing FIG. 3;

FIG. 5 is a diagram showing each symbol display area in the special symbol display device.

FIG. 6 is a flowchart showing a control processing procedure of the pachinko gaming machine by the gaming machine control circuit.

FIG. 7 is a flowchart following FIG. 6, showing a control processing procedure of the pachinko gaming machine by the gaming machine control circuit.

FIG. 8 is a block diagram showing the entire configuration of a conventional example.

[Explanation of symbols]

 Reference Signs List 1 gaming machine control circuit 1a random number generation block 2 register (initial value storage means) 3 bit shifter (bit shift means) 4 exclusive OR circuit (logical operation means) 5 exclusive OR gate 6 remainder conversion circuit 7 CPU 7a frequency dividing circuit 8 ROM 9 RAM 10 game board 11 guide rail 12 game area 13 special symbol display device 14 variable winning device (large winning opening) 15 type 1 starting port (starting port) 21 type 1 starting switch 22 continuous switch 23 count switch 24 low pass Filter 25 Buffer gate 26 Output port 27 Driver B bus

Claims (4)

[Claims] 1. A gaming machine control circuit for controlling a game in a gaming machine and having a random number generating means for generating a random number used for the game, wherein the random number generating means sets a predetermined arbitrary value to an initial value. Initial value storage means for storing the initial value stored in the initial value storage means in a predetermined direction by a predetermined number of bits, bit shift means, and a value shifted by the bit shift means and the initial value. Logic operation means for calculating an exclusive OR of the game machine; and An interrupt processing unit is configured by arranging the random number generating unit before the processing unit, and a series of interrupt processing of the interrupt processing unit is executed every predetermined time to generate a new random number. Do Gaming machine control circuit. 2. The gaming machine control circuit according to claim 1, wherein a bit operation by said bit shift means and a logical operation by said logical operation means are paired and a repetition process is performed a plurality of times. 3. A shift direction is changed for each repetition processing by said bit shift means.
A gaming machine control circuit as described. 4. When shifting to the left, the bit shift amount by the bit shift means is shifted by a value obtained by adding 1 to a half of the number of bits required for a random number to be generated, and 2. The method according to claim 1, wherein when shifting in the direction, the bit is shifted by an amount obtained by subtracting 1 from the number of bits required for a random number to be generated.
The gaming machine control circuit according to 2 or 3.