JPH0796069A - Game machine control circuit - Google Patents

Abstract

PURPOSE:To generate a randum number of a high quality by shifting an initial value by a prescribed bit number portion to a prescribed direction, deriving exclusive OR of a shifted value and the initial value, and outputting a result of its operation as the randum number. CONSTITUTION:This circuit is provided with an initial value storage means 2 for storing an arbitrary value set in advance as an initial value, and the initial value stored therein is shifted to a prescribed position by a prescribed bit number portion by a bit shifting means 3, exclusive OR of a shifted value and the initial value is derived by a logical arithmetic means 4, and a result of logical operation is outputted as a random number. In this case, this circuit is constituted so that a bit operation by the bit shifting means 3 and a logical operation by the logical, arithmetic means 4 are processed repeatedly plural times as a pair desirably, and the shift direction is changed at every repeated processing by the bit shifting means 3. Also, the bit shift amount is set as a number obtained by adding or subtracting '1' to or from the number of bits as half a necessary number of bits in accordance with the shift direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine control circuit, and more particularly to a game machine control circuit for generating a random number used in a game.

[Background of the Invention] In recent years, in gaming machines, for example, pachinko gaming machines and the like, amusement of a game has been enhanced by a variable display game with a special symbol display device arranged substantially in the center of a game area.

In this variable display game, for example, when a predetermined game condition is satisfied (usually, when winning a prize at a starting opening).
In addition, while the symbols displayed in the special symbol display device start displaying fluctuations, the fluctuations stop after a predetermined period of time, and it is common to make a big hit when the symbols at the time of stopping are aligned with specific symbols. In such a variable display game, determination of a big hit, determination of a symbol at the time of stop (hereinafter, referred to as a stop symbol), and the like include probabilistic elements and are accompanied by a contingency, so that excitement for a game is raised. There is.

Therefore, a random number with a uniformity and irregularity (random number for determining jackpot, random number for determining stop symbol) is used for determination of jackpot, determination of stop symbol, and the like. The random number is generated by the gaming machine control circuit.

[0005]

2. Description of the Related Art Conventionally, as a game machine control circuit for generating such a random number, there is a jackpot determination device having a digit rising counter as shown in FIG.

FIG. 8 is a diagram for explaining the operation of the jackpot determining device.

The jackpot determining device shown in FIG. 8 is "00".
The big hits are controlled by the counter of the digit rising method in which the values up to “234” are regularly moving one by one at a high speed at all times. The big hit is that the value selected at a predetermined timing is preset. This is a case in which one determined winning value (in this case, “03”) is reached, and as a result, the jackpot probability is 1/235.

Incidentally, the timing of this jackpot determination is generally at the time of winning the starting opening of the game ball,
The time required to move one frame of the digit-up counter is a very short period, for example, 0.004096 seconds, and one cycle is 0.96256 seconds (= 0.004).
Since it is sufficiently short (096 × 235), it is used as a random number.

[0009]

Random numbers are variables that do not have any law in how values are changed, and the original meaning is a sequence whose values cannot be predicted. .

However, the random number generated by the above-described digit-up counter is random in the timing of selecting the value of the counter (for example, at the time of winning of the starting mouth) and the cycle of the counter is short. For this reason, the value generated by the digit-up counter is used as a random number, but is a regular arithmetic sequence that is added at a certain fixed value (added one by one in the above example). Therefore, it cannot be strictly called a random number.

That is, it is preferable that the random numbers, which are the sources of randomness that excite the interest in the game in the variable display game, are statistically independent numbers.

[Object] In view of the above problems, an object of the present invention is to generate a high-quality random number.

[0013]

According to a first aspect of the present invention, as shown in FIG. 1, in a game machine control circuit 1 for controlling a game in a game machine and generating a random number used in the game, Initial value storage means 2 for storing the set arbitrary value as an initial value, bit shift means 3 for shifting the initial value stored in the initial value storage means 2 in a predetermined direction by a predetermined number of bits, and the bit shift The logical operation means 4 for obtaining the exclusive OR of the value shifted by the means 3 and the initial value is provided, and the operation result of the logical operation means 4 is output as a random number to achieve the above object. There is.

In this case, in addition to the invention described in claim 1, as described in claim 2, the bit operation by the bit shift means and the logical operation by the logical operation means are paired and performed a plurality of times. It is effective to perform the repetitive processing, and further, in this case, as described in claim 3,
It is preferable to change the shift direction for each repeated processing by the bit shift means.

Further, in addition to the invention described in claim 1, 2 or 3, as described in claim 4, the bit shift amount by the bit shift means is generated when shifting to the left. 1 / the number of bits required for a random number
When bit-shifting by the number obtained by adding 1 to the number of 2 bits and shifting to the right, it is possible to perform bit-shifting by the number obtained by subtracting 1 from 1/2 the number of bits required for the random number to be generated. It is valid.

[0016]

According to the present invention, the bit shift means shifts the initial value by a predetermined number of bits in the predetermined direction based on the initial value stored in the initial value storage means. By obtaining the exclusive logic by the logic operation means based on the value, a high-quality random random number is generated as compared with the conventional digit-up counter.

In this case, according to the invention of claim 2,
The random number having high randomness is generated in addition to the invention according to claim 1, wherein the bit operation by the bit shift unit and the logical operation by the logical operation unit are paired and a plurality of repeated processes are performed. To be done.

According to the invention of claim 3, in addition to the invention of claim 2, the shift direction is changed every time the bit shift means repeats the processing.
A high-quality random number is generated.

Further, according to the invention described in claim 4, when the bit shift amount by the bit shift means is shifted to the left, 1 is the number of bits required for the random number to be generated.
Bit shift by the number obtained by adding 1 to the bit number of / 2,
When shifting in the right direction, in addition to the invention according to claim 1, 2 or 3, by bit-shifting by a number obtained by subtracting 1 from 1/2 of the number of bits required for a random number to be generated. As a result, high-quality random numbers are generated.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to FIGS.
Will be described with reference to. 2 to 7, in FIG.
The same reference numerals are given to the same portions as.

First, the configuration of this embodiment will be described.

FIG. 2 is a front view of the game board 10 in the pachinko gaming machine using the gaming machine control circuit 1 of this embodiment.

As shown in FIG. 2, a game area 12 surrounded by guide rails 11 is formed on the surface of the game board 10 of the pachinko game machine in this embodiment, and the game area 12 is located at a substantially central position. A special symbol display device 13 for performing a variable display game is provided, and in a position below the special symbol display device 13, in a variable display game on the special symbol display device 13, a variation for performing a special game when a big hit occurs. A winning device (big winning opening) 14 is provided.

A first-type starting port 15 is provided above the variable winning device (large winning port) 14.

The variable display game on the special symbol display device 13 is a game area 1 by a game ball launching device (not shown).
On condition that the game ball guided in 2 wins the first type starting opening 15, the three symbols of the left symbol, the middle symbol, and the right symbol displayed in the special symbol display device 13 are displayed in a variable display. With the start, after a predetermined time (after 5 seconds or more), the left symbol, the right symbol, the variation of the medium symbol stops in order, and when the three symbols are aligned with the specific symbol at the time of stop, it is a big hit. The jackpot decision, the stop symbol decision, etc. are performed based on the random number generated by the gaming machine control circuit 1, so that the variable display game includes a stochastic element accompanied by contingency, and excites the interest of the game. Is.

FIG. 3 is a block diagram showing a main configuration of a pachinko gaming machine including the gaming machine control circuit 1 in this embodiment.

In FIG. 3, the pachinko gaming machine in this embodiment is a gaming machine control circuit 1 and a first type starting switch 2
1, continuous switch 22, count switch 23, low-pass filter 24, buffer gate 25, output port 2
6, a driver 27 and a variable winning device (big winning opening) 14 are provided. In FIG. 3, B is a bus.

The gaming machine control circuit 1 is for generating uniform random numbers with a predetermined probability (in the case of this embodiment, a probability of 1/245), a random number generation block 1a, a CPU (Ce
ntral Processing Unit) 7, frequency divider 7a, ROM
(Read Only Memory) 8, RAM (Random Access Memo)
ry) 9 and the random number generation block 1a is
The register 2 is an initial value storage means, the bit shifter 3 is a bit shift means, and the exclusive OR circuit 4 is a logical operation means. Also, game machine control circuit 1
Has a function of outputting various information to the management device of the hall (game shop), for example, winning of the first-type starting opening 15, start of the variable display game, and jackpot in the variable display game. .

The register 2 is for storing an initial value for random number generation in this embodiment. Specifically, as the initial value stored in the register 2 in this embodiment, the counter is counted by the CPU 7 at startup. Is driven, this counter value is read at a predetermined timing,
The remainder obtained by dividing the read value by "245" (a value based on the jackpot occurrence probability in this embodiment) is stored as an initial value.

The bit shifter 3 shifts the 8-bit value stored in the register 2 to the left by 5 when shifting up by a digit.
Bit shift is performed, and "0" is written in the lower 5 bits after the shift. Also, when digit shift is performed, 3 bits are shifted to the right, and "0" is written in the upper 3 bits after the shift. Yes, the shift value is output to the exclusive OR circuit 4.

The exclusive OR circuit 4 is composed of an exclusive OR gate 5 and a remainder operation circuit 6, and the exclusive OR gate 5 is stored in the register 2 and the 8-bit shift value input from the bit shifter 3. The exclusive OR of the exclusive OR gate 5 is used to calculate the exclusive OR with the 8-bit initial value.
The output value from is divided by a predetermined number (in this case, "245" based on the jackpot probability), and the remainder is output as a random number value. This is because the output value from the exclusive OR gate 5 is 8 bits, so "0" to "25".
However, since the jackpot probability in the present embodiment is 1/245, a value from "0" to "244" is required, and a value from "245" to "255" is rounded. Is.

By the way, the bit shift processing by the bit shifter 3 and the exclusive OR processing by the exclusive OR gate 5 in the exclusive OR circuit 4 in this embodiment are processed as a pair, and the processing result is stored in the register 2. By repeating the bit shift processing and the exclusive OR processing again, the randomness of the random numbers can be enhanced.

The CPU 7 is an 8-bit microprocessor which is the center of the gaming machine control circuit 1 for controlling various other circuits, and is stored in the ROM 8 in one sequence unit by a reset interrupt process based on a reset signal described later. Various program processes are executed based on the stored program process procedure. When a random number used in the game is required, the random number generation block 1a is controlled to obtain the random number.

The frequency divider circuit 7a divides the clock pulse output from the clock oscillator to generate a reset signal every 2 msec and supplies the reset signal to the CPU 7.

The ROM 8 is a semiconductor memory for storing various control programs and data used by the CPU 7, and the RAM 9 stores program data and the like used during execution of program processing by the CPU 7.
It is a semiconductor memory that temporarily stores data related to games and is used as a work area.

The variable winning device (major winning opening) 14 is opened when a big hit occurs in the variable display game based on the winning timing of the first-class starting opening 15, giving the player a chance of a special game and playing a game. This gives the player many opportunities to win prize balls.

The first type starting switch 21 is a switch which is provided in the first type starting port 15 and detects the winning of a game ball.

Continuation switch 22 and count switch 2
3 is a proximity switch provided in the variable winning device (big winning opening) 14, and the continuation switch 22 is
The count switch 23 detects a passing ball that passes through a specific area (V zone) in the variable winning device (big winning opening) 14, and the count switch 23 wins all the winnings in the variable winning device (big winning opening) 14. It detects a sphere. The 10-count fraud prevention processing is performed based on the detection signals from the switches 22 and 23.

The low-pass filter 24 receives the output signals from the first type starting switch 21, the continuation switch 22 and the count switch 23, and also outputs from a discharge control circuit (not shown) which controls the discharge of the game balls. Request signal is input, and each of these signals is shaped and output as a pulse wave, and the buffer gate 25 amplifies the pulse wave shaped by the low-pass filter 24 and outputs the amplified pulse wave to the bus B.

The output port 26 outputs various signals input via the bus B to the driver 27. The driver 27 is based on the various signals input from the output port 26. (Winning prize) Output a drive control signal for driving 14, or, for example, a jackpot signal, a special figure rotation signal, a starting mouth winning signal, or a special symbol display to be output to a management device on the hall side. Device 13
Other control signals such as a data signal, a control code signal, and a strobe signal to be output to the control circuit, a transmission clock signal to be output to the discharge control circuit (not shown), and a prize ball data signal.

FIG. 4 is a block diagram showing a main configuration of a pachinko gaming machine including a gaming machine control circuit 1 which replaces that shown in FIG.

That is, in the example shown in FIG. 3, the random number generation block 1a has a configuration in which the register 2, the bit shifter 3, and the exclusive OR circuit 4 are independently provided, but in the example shown in FIG. As described above, the CPU 7 may be configured to have the functions of the register 2, the bit shifter 3, and the exclusive OR circuit 4. In this case, the CPU 7
At startup, the internal counter is driven, this counter value is read at a predetermined timing, and the read value is "24
The remainder obtained by dividing by 5 "is used as an initial value, a bit shift is performed in a predetermined direction with respect to this initial value, and a value obtained by performing logical operation processing by exclusive OR of the shift value and the initial value is set as" 245 ". A uniform random number is generated by outputting the remainder of division as a random number value.

Next, the operation (action) of this embodiment will be described.

In the above structure, first, the game ball launched from the game ball launching device (not shown) by the handle operation is guided by the guide rail 11 and launched into the game area 12 in the game board 10.

In the gaming machine control circuit 1, the presence or absence of the input of the first type starting switch 21 is monitored, and when the game ball wins the first type starting port 15, the first type starting switch 21 turns on the game ball. When a winning is detected, chattering of the detection signal is removed, logic conversion is performed, and input processing is performed. In addition, when the winning of the game sphere is detected in the first type starting opening 15, the number of the game spheres that won the prize is stored in a predetermined storage area (hereinafter referred to as a reserve area) up to four, and The value of the random number at the time of winning used in the variable display game is also temporarily stored in the holding area. By the way, the random number for determining the jackpot in the variable display game is
It is generated by the random number generation block 1a in the gaming machine control circuit 1.

Then, the variable display game is started in the special symbol display device 13 based on the memory of the winning of the game ball to the first type starting opening 15, that is, based on the data stored in the reserved area.

In the variable display game process, the gaming machine control circuit 1, for example, the normal operation process, the automatic stop time end monitoring process, the first symbol stop monitoring process, the second symbol stop monitoring and reach determination process, Each process such as three symbol stop monitoring process, symbol determination process, motion end monitoring process, losing motion process, and jackpot motion process is executed.

In this case, the stop symbol in the variable display game is also determined by the random number generated by the random number generation block 1a in the gaming machine control circuit 1, similarly to the above jackpot determination.

FIG. 5 is a diagram showing each symbol display area A, B, C in the special symbol display device 13.

The aforementioned holding area is provided in the RAM 9 of the gaming machine control circuit 1, and this holding area is shown in FIG.
As shown in, as a storage area of the stop symbol corresponding to each symbol display area A, B, C in the special symbol display device 13, it is sequentially updated every reset interrupt. Then, the data of each symbol is judged by the CPU 7 whether it is a big hit symbol or a lost symbol, and when it is judged as a big hit symbol, it is stored in the big hit storage area of the RAM 9 and is a lost symbol. R in some cases
It is stored in the lost storage area of AM9.

On the other hand, in the gaming machine control circuit 1, as described above, based on the random number for determining the big hit, it is judged whether it is a hit or not, and in the case of a hit, by the hit symbol stored in the big hit storage area. The stop symbol is determined, and in the case of a loss, the stop symbol is determined by the loss symbol stored in the loss storage area.

The data relating to the special symbol display device 13 set in the variable display game process is adapted to be output to a display control circuit (not shown) by the display control process.

6 and 7 are flow charts showing the control processing procedure of the pachinko gaming machine by the gaming machine control circuit 1.

When the control processing is started, first, initial information is set (for example, stack pointer setting, RAM 9 access permission, reset signal clearing, etc.) (step S1), and the CPU 7 sets the internal counter. The value is read at a predetermined timing, and the remainder obtained by dividing this counter value by “245” is stored in the register 2 as an initial value.

Next, it is checked whether or not the power is turned on for the first time for the pachinko gaming machine (step S2), and when it is detected that the pachinko gaming machine is supplied with power by the operation of the power switch, the CPU 7 causes the CPU 7 to operate. After the registers used and the RAM 9 are initialized and the wait time which is the time required to confirm the memory contents at power-on is set (step S3),
The wait time is updated by the wait time processing (step S4), and the CPU 7 waits for an interrupt.

On the other hand, in the processing of step S2,
If the power-on is not detected, the memory including the RAM 9 is inspected, that is, the presence or absence of abnormality in the memory is checked (step S5), and if the abnormality is detected in the memory,
After the processes of steps S3 and S4, the CPU 7 is in a state of waiting for an interrupt.

When no abnormality is detected in the memory in the processing of step S5, the gaming machine control circuit 1 performs prize ball control by communication processing relating to prize ball data with the discharge control circuit (not shown). While being performed (step S6), probability setting processing for setting the jackpot probability in the variable display game is performed (step S7).

Then, it is checked whether or not the power-on wait time set in step S3 has ended (step S8). If the wait time has not ended, the CPU 7 goes through the process of step S4. Waits for an interrupt, and when the wait time is over, output processing for outputting the output data set in various subroutine processing is performed (step S9) to determine the hit / miss in the variable display game. Then, a new random number is generated by the random number generation block 1a based on the initial value stored in the register 2, the random number is updated by the random number update process (step S10), and the input process is performed (step S11).

Hereinafter, a power fail monitoring process (step S12) for monitoring the power source voltage of the lamp power source, the solenoid power source, etc., and a count switch winning prize monitoring process (step S)
13), continuation switch winning a prize monitoring process (step S1)
4), after the special symbol operation switch prize monitoring process (step S15) in the first type starting port 15 and fraud monitoring process (step S16) are performed, the value of the event counter for efficiently processing each sequence is set. Based on this, branching processing is performed (step S17).

That is, when the counter value is "0", the voice synthesis processing (step S18), when the counter value is "1", the LED editing processing (step S19), and when the counter value is "2", the lamp editing processing is performed. Processing (step S20),
If the counter value is "3", the variable display game process (step S21), if the counter value is "4", the symbol control editing process (step S22), if the counter value is "5", the data transfer process (step) S23), if the counter value is "6", the external information editing process (step S24),
When the counter value is "7", the input information control process (step S25) is performed.

Next, the display data setting process for the display control circuit is performed (step S26), and the random number data used in the process of step S21 is stored in the register 2 as a new initial value (step S2).
7), the sound edit output process is performed (step S28),
The CPU 7 is in an interrupt waiting state.

Then, based on the above-mentioned reset signal, the CPU 7 is designed to recover from the state of waiting for an interrupt.

The generation of a specific random number in this embodiment will be described below.

As described above, since the remainder of "245" is stored as the initial value stored in the register 2,
The value is between "0" and "244".

Here, for example, if "3" (= "00000011B") is stored as the initial value stored in the register 2, the initial value in the register 2 in the random number generation block 1a is changed by the bit shifter 3. For example, 5 bits are shifted to the left by “96” (= “01100
000B ″) is obtained, and then the exclusive OR gate 5 in the exclusive OR circuit 4 shifts the shift value “01100000B” by the bit shifter 3 and the register 2
The exclusive OR with the initial value "00000011B" in the above is calculated, and the result of the operation is "99" (= "011000").
11B ″) is required.

The obtained value is stored again in the register 2, and then the operation value in the register 2 is shifted to the right by, for example, 3 bits by the bit shifter 3 to be "1".
2 ”(=“ 00001100B ”) is obtained, and then the exclusive OR gate 5 in the exclusive OR circuit 4 shifts the shift value“ 000011 ”by the bit shifter 3.
00B ”and the stored value“ 01100011 ”in the register 2.
The exclusive OR with "B" is calculated and the result is "1".
11 ”(=“ 01101111B ”) is obtained.

Here, the value "111" output from the remainder operation circuit 6 via the exclusive OR gate 5 in the exclusive OR circuit 4 is smaller than 245, so that "1" is set.
11 "is directly output as a random number.

In the next random number generation, "111" is set as a new initial value, and the bit shifter 3 first sets "1".
11 "is shifted to the left by 5 bits and becomes" 224 "(=
"11100000B") is obtained, and the exclusive OR gate 5 shifts the shift value "11100000B" by the bit shifter 3 and the initial value "01" in the register 2.
The exclusive OR with 101111B "is calculated, and" 143 "(=" 10001111B ") is obtained as the calculation result.

Then, "143" is stored in the register 2, and "143" is shifted to the right by 3 bits to obtain "17" (= "00010001B"). Next, the exclusive OR gate 5 Performs an exclusive OR between the shift value “00010001B” by the bit shifter 3 and the storage value “10001111B” in the register 2, and the result of the operation is “158” (=
“01101111B”) is obtained, and the remainder operation circuit 6
As a random number output from, "158" is obtained as it is. In the same manner, a random number sequence as shown in [Table 1] is generated.

[0070]

[Table 1]

That is, the random number sequence obtained by the conventional digit-up counter shown in FIG. 8 is a regular arithmetic sequence, but in the present embodiment, a high-quality and highly random number sequence is used. Can be generated.

As described above, in this embodiment, the bit shifter 3 is based on the initial value stored in the register 2.
The initial value is shifted by a predetermined number of bits (in this embodiment, 5 or 3 bits) in a predetermined direction by, and the exclusive OR gate 5 obtains an exclusive logic based on the shift value and the initial value. It is possible to generate a high-quality random random number as compared with the digit-up counter.

Therefore, in this embodiment, it is possible to further increase the probability of probability in a gaming machine (pachinko gaming machine).

Although the invention made by the present inventor has been specifically described based on the preferred embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the bit shift amount by the bit shifter 3 is set to 5 or 3 bits for the 8-bit random number value in this embodiment, but it is not limited to the numerical value in this embodiment. , It can be set arbitrarily to obtain high-quality random numbers.

Further, in this embodiment, the exclusive OR circuit 4
The value obtained by was used as the initial value for the next random number generation, but not limited to this, the random number data obtained in the past is held and a predetermined number of random numbers picked up from the held random number data. The exclusive OR of data may be used as a new initial value.

Some specific CPUs have a register called a refresh register for refreshing the dynamic memory, and the data held in this refresh register is decremented every predetermined time.

In a CPU having such a refresh register, if it is not necessary to consider the reproducibility of random numbers, the exclusive OR of the value obtained by the exclusive OR circuit 4 and the value of the refresh register. May be used as a new initial value.

In the above description, the invention mainly made by the inventor is applied to the gaming machine control circuit in the pachinko gaming machine, which is the field of application of the background, but the invention is not limited thereto. Absent.

For example, the present invention can be applied to the control of a game machine (pachi-con) or the like which keeps the starting rate of the pachi-slot and the variable display game always constant.

[0081]

According to the first aspect of the invention, the initial value is shifted by the predetermined number of bits in the predetermined direction by the bit shift means based on the initial value stored in the initial value storage means.
By obtaining the exclusive logic by the logical operation means based on the shift value and the initial value, it is possible to generate a high-quality random random number as compared with the conventional digit-up counter.

In this case, in the invention described in claim 2, the bit operation by the bit shift means and the logical operation by the logical operation means are paired to perform repeated processing a plurality of times. In addition to the above invention, it is possible to generate a random number with high randomness.

Further, in the invention described in claim 3, by changing the shift direction for each iterative process by the bit shift means, in addition to the invention described in claim 2, it is possible to generate a high-quality random number. .

Further, in the invention of claim 4, the bit shift amount by the bit shift means is 1/2 of the number of bits required for the random number to be generated when shifting to the left.
When bit-shifting by the number obtained by adding 1 to the number of bits of, and shifting to the right, by bit-shifting by the number obtained by subtracting 1 from the number of bits required for the random number to be generated, In addition to the invention described in claim 1, 2 or 3, it is possible to generate a high-quality random number.

[Brief description of drawings]

FIG. 1 is a principle diagram of a gaming machine control circuit according to the present invention.

FIG. 2 is a front view of a gaming board in a pachinko gaming machine using the gaming machine control circuit of this embodiment.

FIG. 3 is a block diagram showing a main configuration of a pachinko gaming machine including a gaming machine control circuit according to the present embodiment.

FIG. 4 is a block diagram showing a main configuration of a pachinko gaming machine including a gaming machine control circuit replacing the one shown in FIG. 3;

FIG. 5 is a diagram showing each symbol display area in the special symbol display device.

FIG. 6 is a flowchart showing a control processing procedure of a pachinko gaming machine by a gaming machine control circuit.

7 is a flow chart showing a control processing procedure of the pachinko gaming machine by the gaming machine control circuit, following FIG.

FIG. 8 is a block diagram showing an overall configuration of a conventional example.

[Explanation of symbols]

 1 Gaming Machine Control Circuit 1a Random Number Generation Block 2 Register (Initial Value Storage Means) 3 Bit Shifter (Bit Shift Means) 4 Exclusive OR Circuit (Logic Operation Means) 5 Exclusive OR Gate 6 Residue Conversion Circuit 7 CPU 7a Dividing Circuit 8 ROM 9 RAM 10 game board 11 guide rail 12 game area 13 special symbol display device 14 variable winning a prize device (large winning hole) 15 first type starting port 21 first type starting switch 22 continuation switch 23 count switch 24 low pass filter 25 buffer gate 26 output port 27 driver B bus

Claims (4)

[Claims] 1. Controlling a game on a gaming machine,
In a gaming machine control circuit for generating a random number used in the game, an initial value storage means for storing a preset arbitrary value as an initial value, and an initial value stored in the initial value storage means for a predetermined number of bits. A bit shift means for shifting in the direction, and a logical operation means for obtaining an exclusive OR of the value shifted by the bit shift means and the initial value, and outputs the operation result of the logical operation means as a random number. A gaming machine control circuit characterized by the above. 2. A gaming machine control circuit according to claim 1, wherein a bit operation by said bit shift means and a logical operation by said logical operation means are paired to perform a plurality of repeated processes. 3. The gaming machine control circuit according to claim 2, wherein the shift direction is changed for each repetitive processing by the bit shift means. 4. When shifting to the left, the bit shift amount by the bit shift means is bit-shifted by a number obtained by adding 1 to 1/2 of the number of bits required for a random number to be generated, and right shifting. 3. When shifting in the direction, bit shifting is performed by a number obtained by subtracting 1 from the number of bits required for a random number to be generated by 1/2.
Alternatively, the gaming machine control circuit described in 3.