JP2000126403A - Game controller for pachinko machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent erroneosly receiving a prize winning detection signals. SOLUTION: A microcomputer 1 drives a series of process on a game by reset interruption signals from a reset interruption circuit 1e at, for instance, every 4 msec cycle, executes a plural number of input reading processes to a prize winning ball detecting signal from a detecting switch 7 by a timer interruption signal inputted from a timer interruption generating circuit 1f, and executes an input discrimination process to the prize winning ball detecting signal between the next one game processing cycle until the first timer interruption signal input.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer in which a series of processes relating to a game are repeatedly executed at each cycle, and a game ball fired by a player's operation wins a winning opening provided in a game board. Accordingly, the present invention relates to a game control device of a pachinko machine in which a microcomputer executes a game process corresponding to the winning.

[0002]

2. Description of the Related Art In a game control device for a pachinko machine disclosed in Japanese Patent No. 2556954, a CPU of a microcomputer uses a ROM of the microcomputer in response to a reset interrupt signal periodically input from a reset interrupt generating circuit. Using the RAM stored in the microcomputer as a storage means in the processing process, a series of processings relating to a game such as input processing and output processing are repeatedly executed from the beginning of the program.

[0003]

However, in the conventional game control device for a pachinko machine, in one game processing cycle from one reset interrupt signal to the next reset interrupt signal, the CPU is set to one. When performing one game process corresponding to one prize, if the effective time of the prize ball detection signal is not longer than the game processing cycle, the CPU may miss the prize ball detection signal. When the CPU misses the winning ball detection signal, the CPU does not execute the game process corresponding to the missed winning ball detection signal, so that the quality reliability of the pachinko machine is inevitably lacking. Also, in order to increase the fun of the game, the capacity of the program is increased,
When the game processing time of U becomes long, the effective time of the winning ball detection signal becomes shorter than one game processing cycle, and the signal is often missed.

[0004] Therefore, an object of the present invention is to provide a control device for a gaming machine with high quality reliability by preventing a winning ball detection signal from being missed.

[0005]

According to the first aspect of the present invention, a microcomputer mounted on a pachinko machine and executing a series of processing relating to a game at each cycle is input from a detection switch mounted on the pachinko machine. In the game control device of the pachinko machine which starts the game processing corresponding to the winning ball detection signal in response to the winning ball detection signal, the search for the winning ball detection signal during one game processing cycle is carried out by validating the winning ball detection signal. An input signal monitoring unit that performs a plurality of times each time shorter than the time is provided. According to a second aspect of the present invention, the input monitoring means according to the first aspect includes a certain one.
A plurality of input reading processes are performed in one game processing cycle, and one input determination process is performed in the next game processing cycle based on the plurality of input reading processes. Claim 3
In the present invention, the interval of the input reading process described in claim 2 is constant from the start of the game processing cycle. The invention according to claim 4 is characterized in that the interval of the input reading process according to claim 2 is generated by a timer interrupt.

[0006]

1 to 8 show an embodiment of the present invention. FIG. 1 shows the overall configuration, FIG. 2 shows the timing of a game processing cycle and an input signal monitoring cycle, and FIG. FIG. 4 illustrates an input reading process of the main control unit, FIG. 5 illustrates a structure of an input buffer and an input result flag, and FIG. 6 illustrates an input determination process of the main control unit. 7 shows an input determination pattern, and FIG. 8 shows timings of an input reading process and an input determination process.

Referring to FIG. 1, a game control device for a pachinko machine will be described. The control device of the pachinko machine is divided into functions such as a main control unit 1, a special symbol control unit 2, an indicator light control unit 3, a sound effect control unit 4, a prize ball payout control unit 5, a ball launch control unit 6, and the like. . These control units 1 to 5 are a CPU and a ROM.
And a RAM individually comprising a RAM.

The microcomputer 1a of the main control unit 1
When a winning ball detection signal from various detection switches 7 is input via wiring and an input interface, CP
U1b stores the program set in ROM1c in RAM1
Using d as storage means of the processing process, the game processing of the entire game shown in FIGS. 3, 4 and 6 is executed, and a command as a game processing result with respect to the winning ball detection signal is output via the output interface and the wiring. It outputs to the special symbol control unit 2, the indicator light control unit 3, the sound effect control unit 4, the prize ball payout control unit 5, and the ball launch control unit 6 in one direction.

In the case of this embodiment, the detection switch 7 is a starting port switch 7 for changing a special symbol.
a, a count switch 7b for counting the number of balls winning the special winning opening, a V switch 7c for a condition for continuously opening the special winning opening, a first winning opening switch 7d as a natural winning opening, a left sleeve Second prize port switch 7e as a prize port switch, third prize port switch 7 as a right sleeve prize port switch
f, a fourth winning opening switch 7g serving as a left-winning opening, a fifth winning opening switch 7h serving as a right-winning opening, and the like.

The program of the microcomputer 1a starts a series of processings relating to the game shown in FIG. 3 by the reset interrupt signal input to the CPU 1b from the reset interrupt generating circuit 1e at intervals of, for example, 4 msec. Further, in one game processing cycle, the CPU 1b receives the prize ball detection signal from the timer interrupt signal input to the CPU 1b from the timer interrupt generation circuit 1f every time shorter than the valid time of the prize ball detection signal. Execute the search process multiple times. Thus, the microcomputer 1a constitutes a winning monitor. The process of searching for the winning ball detection signal is divided into an input reading process shown in FIG. 4 and an input determining process shown in FIG.

The reset interrupt generating circuit 1e and the timer interrupt generating circuit 1f are formed by a timer set in the microcomputer 1a. The timer interrupt flag 1g is set in the timer interrupt generation circuit 1f, is set each time the timer expires, and outputs a timer interrupt signal to the CPU 1b.

In the RAM 1d, a timer interrupt flag 1g, an interrupt counter 1h, a zeroth input buffer 1i, a first input buffer 1
j, the second input buffer 1k, the input result flag 1m, the bit counter 1n, and the bit confirmation flag 1p are each set in one byte. The interrupt counter 1h is a counter for determining the number of winning ball detection signal search in one game processing cycle.

The 0th to 2nd input buffers 1i to 1k detect that the winning ball detection signal from the detection switch 7 has been input to the input port of the CPU 1b in one game processing cycle and the next one. This is a memory that stores the game processing cycle and the number of times of the search processing of the winning ball detection signal is one more. In the case of this embodiment, since the number of times of the search processing of the winning sphere detection signal in one game processing cycle is two, the input buffer is the 0th byte constituted by 1 byte.
To 2nd input buffers 1i to 1k.

In the input reading process, the CPU 1
b stores the first port input read result (switch input read result) in the first input buffer 1j, and stores the second port input read result in the second input buffer 1k. 2
Before the result of the second port input read is stored in the second input buffer 1k, in order to confirm the input of the first input buffer 1j, the CPU 1b executes the second input buffer which is the result of the port input read in the previous game processing cycle. The 1k data is stored in the 0th input buffer 1i and saved.

The input result flag 1m is a flag for storing an input determination result in the input determination process of determining whether or not a winning ball detection signal from the detection switch 7 has been input to the input port of the CPU 1b based on the input read result in the input read process. It is. The bit counter 1n is a counter that indicates which bit of the input result flag 1m is to be determined in the input determination process. The bit confirmation flag 1p is set to the 0th to the second input buffer 1 indicated by the bit counter 1n.
This flag stores that the value of the bit in i to 1k is “1”, and is “FF” in the case of setting (set).
H ”is written, and in the case of erasing (clearing),“ 00H ”is written.

When the command from the output interface of the main control unit 1 is input via the wiring and the input interface, the microcomputer of the special symbol control unit 2
Liquid crystal, LED or CRT provided as a center role of pachinko machine by executing display control processing by program
Alternatively, the display 8 such as a plasma display is electrically driven via an output driver. When a command from the output interface of the main control unit 1 is input via the wiring and the input interface, the microcomputer of the indicator light control unit 3 executes a lighting control process by a program, and executes a side lamp, a top lamp or a lamp of the pachinko machine. An indicator light 9 such as a windmill or a prize ball lamp is electrically turned on and off via an output driver. When a command from the output interface of the main control unit 1 is input through the wiring and the input interface, the microcomputer of the sound effect control unit 4 executes a process of sound effect control by a program, and the sound source IC is stored in the ROM by the execution result. Is converted into a sound effect signal from the sound effect data set in step (1), and the amplifier amplifies the sound effect signal to electrically drive the speaker 10. When the command from the output interface of the main control unit 1 is input via the wiring and the input interface, the microcomputer of the winning ball payout control unit 5
The processing of the prize ball payout control and the firing control by the program is executed, and an actuator such as the prize ball payout solenoid of the prize ball payout mechanism 11 is electrically driven. Ball launch control unit 6
The microcomputer of the present embodiment controls the input state via the input interface from the stop switch provided on the handle of the ball launching mechanism 12 operated by the player, and the touch detection circuit of the ball launching mechanism 12 from the touch lever provided on the handle. For launching the ball in the ball launching mechanism 12 onto the game board in accordance with the input situation through the game and the input state based on the launch permission signal (launch permission command) from the prize ball payout controller 5 via the input interface. The firing solenoid, which is the actuator, is electrically driven via the output interface with the power level adjusted by the handle volume. Reference numeral 13 denotes a special winning opening solenoid as an actuator for opening and closing a special winning opening provided as a variable winning opening in a pachinko machine, and reference numeral 14 denotes a hall computer installed in a pachinko parlor for business management. The hall computer 14 collects information from a plurality of pachinko machines installed in a pachinko parlor and totals the information.

Referring to FIG. 2, the timing of the game processing cycle and the input signal search processing will be described. The timer interrupt time t is set at a constant interval within one game processing cycle T between the time when one reset interrupt signal R1 rises and the time when the next reset interrupt signal R2 rises. Instead, by setting the values of the different times t1 and t2 for generating the timer interrupt signal from the rising edge of the reset interrupt signal R1 in the program of the main control unit 1, the timer interrupt time t can be reduced. It is set to be always constant (t = t2−t1) from the start of the processing cycle T. By setting the timer interrupt time t in this way, the interval of the input reading process started by the timer interrupt signals S1 and S2 becomes constant, and the prize ball detection signal input from the detection switch 7 to the input port of the CPU 1b is set. If the valid time is equal to or longer than the time from one timer interrupt signal S1 to the next timer interrupt signal S2, the CPU 1b can surely search for the winning ball detection signal. That is, the detection switch 7 sets the CPU
The valid time of the winning ball detection signal input to the input port 1b can be easily managed.

With reference to FIG. 3, a game process executed by the main control unit 1 in response to a reset interrupt signal will be described. Step S1 is a process of determining when the power is initially turned on. Since the data in the RAM 1d immediately after the power is initially turned on is undefined, the power on is determined based on the presence or absence of specific data in a specific area of the RAM 1d. If there is no specific data, it is determined that the power has just been turned on, and the process proceeds to step S5. If there is specific data, it is determined that the game processing is to be repeated, and the process proceeds to step S2. Step S2 is the setting of the timer interrupt, and the time t1 and t2 and the setting of the permission of the interrupt in FIG. 2 are set, and the interrupt counter 1h is cleared. Step S3 is an input determination process, which determines whether or not a winning ball detection signal from the detection switch 7 is present at the input port of the CPU 1b based on the result of the input reading in the input reading process. Step S4 is a game process generally performed in the pachinko machine, for example, a start winning waiting process, a symbol change start process, a symbol stop process, a big hit determination process, a big hit start process, a big win opening process, a big win. Mouth opening wait processing, update processing such as jackpot determination random numbers and symbol random numbers, sound effect generation processing, display processing with symbols and indicator lights, prize ball payout control processing, external information processing, port output processing, etc. It is not limited, and is appropriately configured according to the specifications of the gaming machine. Commands as the results of these game processes are output from the main control unit 1 to the special symbol control unit 2, the indicator light control unit 3, the sound effect control unit 4, the prize ball payout control unit 5, the ball launch control unit 6, and the like. Step S
Reference numeral 5 denotes an initialization process which clears the RAM 1d and sets initial data at the start of the game in the RAM 1d. And
After the processing of steps S1 to S5 is completed, the CPU 1b waits for the next reset interrupt signal without performing any processing (empty loop).

The input reading process will be described with reference to FIG. This input reading process is a process of storing the read result of the port input in the 0th to 2nd input buffers 1i to 1k, and is started by a timer interrupt signal generated at each of the times t1 and t2 set in step S2. I do. This input reading process is executed twice during one game process in FIG. Step S301 is a process for clearing the timer interrupt flag 1g that has been made significant by the timer interrupt generation circuit 1f. When the CPU 1b clears the timer interrupt flag 1g, the input reading process is performed for one timer interrupt signal.
Execute it twice. If the timer interrupt flag 1g is not cleared due to a processing abnormality such as a noise or a power supply abnormality, the subsequent processing is interrupted, and the generation of the next timer interrupt signal is awaited. Step S302 is processing to count up the interrupt counter 1h. This interrupt counter 1h is cleared in step S2 of FIG. Step S303
Is a port input process, which acquires the state of the input port in the CPU 1b. Step S304 is a branch judgment based on the value of the interrupt counter 1h. Since the value of the interrupt counter 1h is "1", the first input reading process in the one game process in FIG. 3 is executed. If so, step S3
The process proceeds to S <b> 306, and when the value of the interrupt counter 1 h is “other than 1”, the process proceeds to step S <b> 306 when executing the second input reading process. Step S305 is a process of storing the first data in the first input buffer 1j. The input port information acquired in step S303 in the first input reading process is stored in the first input buffer 1j as a result of the first input reading. I do. Step S306 is processing for saving the value of the second input buffer 1k to the 0th input buffer 1i, and step S307 is processing for storing the second data in the second input buffer 1k. The input port information acquired in step S303 is stored in the second input buffer 1k as a second input read result.

Referring to FIG. 5, the 0th to second input buffers 1
The structure of i to 1k and the input result flag will be described.
The least significant bit D0 of each of the 0th to the 2nd input buffers 1i to 1k stores the input read result corresponding to the starting port switch 7a, and the first bit D1 is the count switch 7b.
And the second-order bit D2 stores the input read result corresponding to the V switch 7c, and the third bit D2 stores the input read result corresponding to the V switch 7c.
The input reading result corresponding to the first winning opening switch 7d is stored in the place bit D3, the input reading result corresponding to the second winning opening switch 7e is stored in the fourth place bit D4, and the fifth bit D5 is stored in the fifth place bit D5. Stores an input read result corresponding to the third winning opening switch 7f, stores an input reading result corresponding to the fourth winning opening switch 7g in the sixth bit D6, and stores a fifth winning opening in the most significant bit D7. The input read result corresponding to the switch 7h is stored. 0th to 2nd input buffers 1i to 1k
When each bit data in “1” is “1”, it indicates that the corresponding detection switch 7 is off, and when each bit data is “0”, it indicates that the corresponding detection switch 7 is on.

The least significant bit D0 of the input result flag 1m stores the input determination result corresponding to the starting port switch 7a, the first bit D1 stores the input determination result corresponding to the count switch 7b, and the second bit D1 stores the input determination result corresponding to the count switch 7b. The bit D2 stores the input determination result corresponding to the V switch 7c, the third bit D3 stores the input determination result corresponding to the first winning opening switch 7d, and the fourth bit D4 stores the second winning opening. The input determination result corresponding to the switch 7e is stored and the fifth bit D
5 stores the input reading determination result corresponding to the third winning opening switch 7f, the sixth position bit D6 stores the input reading determination result corresponding to the fourth winning opening switch 7g, and the most significant bit D7 stores The input determination result corresponding to the fifth winning opening switch 7h is stored. The process of determining whether or not a prize ball detection signal has been input from the detection switch 7 to the input port of the CPU 1b is performed by comparing the 0th input buffer 1i for each bit with the first input buffer 1j, the first input buffer for each bit, 1
In the comparison between j and the second input buffer 1k, if the bit data changes from "1" to "0", it is determined that there is an input, and "1" is stored in the corresponding bit of the input result flag 1m. Then, when there is a change in bit data other than the above, it is determined that there is no input, and "0" is stored in the corresponding bit of the input result flag 1m.

Referring to FIG. 6, the input determining process will be described. In this input determination process, based on the input reading result in the input reading process of FIG.
1b is determined, and the result of the input determination is stored in the input result flag 1m. Input result flag 1m
Are used in step S4 of FIG. Step S40
Reference numeral 1 denotes a process for clearing the input result flag 1m and the bit counter 1n. The bit counter 1n is cleared and the input result flag 1m is cleared in order to determine the input of the 0th bit. Step S402 is a branch judgment based on the value of the bit counter 1n.
Is greater than or equal to "8", it is determined that all the bytes (all the detection switches 7) have been determined, and the input determination processing ends. If the value of the bit counter 1n is equal to or smaller than "7", the flow shifts to step S403 to perform input determination processing. Step S403 is a branch determination based on the bit value of the 0th input buffer 1i designated by the bit counter 1n.
When the bit value of the input buffer 1i is "1", the process proceeds to step S404, and when the bit value is "0", the process proceeds to step S405. Step S404 is a process for setting the bit confirmation flag 1p, and the bit counter 1n
The bit value of the 0-th input buffer 1i designated by "1" is "1".
Bit confirmation flag 1p
Is set. Step S405 is for bit confirmation flag 1
This is a process for clearing p. In order to store that the bit value of the 0th input buffer 1i indicated by the bit counter 1n is “0”, the bit confirmation flag 1p is cleared. Step S406 is branch determination based on the bit value of the first input buffer 1j designated by the bit counter 1n, and the bit value of the first input buffer 1j is "1".
In the case of, the process moves to step S407, and the bit value is
In the case of, the process moves to step S408. Step S40
Reference numeral 7 denotes a process for setting a bit confirmation flag 1p. The bit confirmation flag 1p is set to store that the bit value of the first input buffer 1j designated by the bit counter 1n is "1". Step S408 is a branch determination based on the state of the bit confirmation flag 1p. If the bit confirmation flag 1p is set, step S408 is executed.
The flow shifts to 409, and if the bit confirmation flag 1p is cleared, the flow shifts to step S411. Step S4
Step 09 sets the bit of the input result flag 1m designated by the bit counter 1n.
8, the 0th input buffer 1i is “1” because the bit confirmation flag 1p is a set judgment, and
Since the first input buffer 1j is "0" in step S406, the CPU 1b determines that there is an input, and sets the bit of the input result flag 1m indicated by the bit counter 1n. Step S410 is a process of clearing the bit confirmation flag 1p. In order to store that the bit value of the first input buffer 1j indicated by the bit counter 1n is "0", the bit confirmation flag 1p is cleared. . Step S411 is a branch determination based on the bit value of the second input buffer 1k indicated by the bit counter 1n. If the bit value of the second input buffer 1k is "1", the flow shifts to step S414, where the bit value is " If “0”, the process moves to step S412. Step S412 is a branch determination based on the state of the bit confirmation flag 1p. When the bit confirmation flag 1p is set, the process proceeds to step S413, and when the bit confirmation flag 1p is cleared, the process proceeds to step S414.
Step S413 is a process of setting the bit of the input result flag 1m designated by the bit counter 1n. Since the bit confirmation flag 1p is a determination of the setting in step S412, the first input buffer 1j is "1". In addition, since the second input buffer 1k is "0" in step S411, the CPU 1b determines that there is an input, and sets the bit of the input result flag 1m indicated by the bit counter 1n. Step S414 is a process for incrementing the bit counter 1n. In order to determine the input of the next bit (next detection switch), the bit counter 1n is incremented.

Referring to FIG. 7, steps S403 to S403 in FIG.
A pattern of processing for determining whether or not a winning ball detection signal has been input from the detection switch 7 to the input port of the CPU 1b from the detection switch 7 will be described. The input determination process of this embodiment is performed in the 0th mode that indicates “1” or “0” for each bit.
Since the second to third input buffers 1i to 1k are used, the input determination patterns are eight patterns (No. 1 to No. 8), which are 2 to the third power. Then, in the comparison between the 0th input buffer 1i and the first input buffer 1j for each bit and the comparison between the first input buffer 1j and the second input buffer 1k for each bit, the bit data is changed from “1” to “0”. This is a processing mode in which it is determined that there is an input when there is a change to "". For this reason, the 0th to the 2nd input buffers 1i to
The signal form of each bit of No. 1k is surrounded by a dotted line. 3,
No. 5, no. 6, no. 7 are the results of the determination that there is an input, and the corresponding input result flag 1m
"1" is stored in the bit of. No. other than the above. 1,
No. 2, No. 4, no. 8 are the determination results of no input, and the corresponding input result flag 1m
"0" is stored in the bit of.

Referring to FIG. 8, the input reading process of FIG.
The timing with the input determination process will be described. One game processing cycle T1 between the time when one reset interrupt signal R1 rises and the time when the next reset interrupt signal R2 rises
, The port input information P1 is stored in the first input buffer 1j in response to the first timer interrupt signal S1.
It is stored as 1. The data D00 of the second input buffer 1k is transferred to the zeroth input buffer 1i by the second timer interrupt signal S2, and after the second input buffer 1k becomes empty, the port input information P2 is transferred to the second input buffer 1k. It is stored as data D12. The data D00 is 1
The port input information P0 stored in the second input buffer 1k by the second timer interrupt signal S0 in the previous game processing cycle T0. And the next game processing cycle T
2, between the reset interrupt signal R2 and the first timer interrupt signal S3, the CPU 1b uses the input determination signal H1 generated by a program to generate the 0th to 2nd buffers 1i to
Input determination processing is performed based on the values of the 1k data D00, D11, and D12. Also, the data D11 of the first input buffer 1j
Is updated to the port input information P3 by the first timer interrupt signal S3 in the next game cycle T2, and the data D00 of the 0th input buffer 1i becomes 2 in the game cycle T2.
The second timer interrupt signal in the game period T1
The data is updated to the data D12 of the input buffer 1k, and the port input information is stored in the second input buffer 1k by the second timer interrupt signal in the game cycle T2. In short, the data D00 of the second input buffer 1k in the immediately preceding game cycle T0 and the first and second data in the current game cycle T1.
The data D11 and D12 of the input buffers 1j and 1k are
It is used for input determination processing before the first timer interrupt signal S3 in the next game cycle T2.

In the above embodiment, the number of the detection switches 7 is eight, and the 0th to the second input buffers 1i to 1k are each composed of one byte. Information corresponding to the switch may be allocated from the least significant bits of the 1st to 2nd input buffers 1i to 1k, which are 1 byte, and the most significant bits may be left empty. If the number of the detection switches 7 is nine or more, the 0th to the second input buffers 1i to 1k and the input result flag 1m are increased by one byte, and the information corresponding to the ninth or more detection switches 7 is two bytes. Allocate from the least significant bit of the eye and leave the most significant bit empty. That is, the number of the detection switches 7 is not limited to eight, and one or more and seven or less or nine or more can be applied.

The bit confirmation flag 1p may be provided for each of the 0th to the 2nd input buffers 1i to 1k. However, as in the above embodiment, one bit confirmation flag 1p is set for the 0th to the 2nd input buffers 1i to 1k. If shared, the memory area of the RAM 1d can be allocated to other game processes.

The number of times of searching for an input signal during one game processing cycle may be three or more. For example, when the search for the winning ball detection signal is performed three times, the 0th to the 2nd input buffers 1i to 1k
In addition to the above, one third input buffer is provided, and the time t shown in FIG.
A time t3 is provided in addition to the time t1, t2, and the timer interrupt time t =
The times t1, t2, and t3 from the reset interrupt signal are set so that t2-t1 = t3-t2, and in a certain game processing cycle, the port input information is changed by the first timer interrupt signal. The port input information is stored in the first input buffer 1j, and the port input information is received by the second timer interrupt signal.
And the port information is stored in the third input buffer after the data of the third input buffer is transferred to the zeroth input buffer 1i by the third timer interrupt signal. Then, based on the input determination signal H1 generated between the start of the next game cycle and before the input of the first timer interrupt signal, a comparison between the 0th input buffer 1i and the 1st input buffer 1j for each bit,
In the comparison between the first input buffer 1j and the second input buffer 1k for each bit and the comparison between the second input buffer 1k and the third input buffer for each bit, the bit data is changed from "1" to "0". When there is a change, it is determined that there is an input.

[0028]

As described above, according to the first aspect of the present invention, during a game processing cycle in which one reset interrupt signal is processed once, a prize ball detected from the detection switch is input to the microcomputer. Since the signal search is performed a plurality of times each time shorter than the effective time of the winning ball detection signal, even if the content of the program assigned to the main control unit increases and the game processing cycle increases, Even if is shorter than the game processing cycle, the microcomputer can accurately acquire the winning ball detection signal, prevent the winning ball detection signal from being missed, and improve the quality reliability of the pachinko machine. According to the second aspect of the present invention, a plurality of input reading processes are performed in one game processing cycle, and one input determination process is performed in the next game processing cycle based on the plurality of input reading processes. The processing time taken by the main control unit can be shortened as compared with the case where the input reading process and the input determining process are performed in a pair in one game processing cycle. According to the third aspect of the present invention, since the interval of the input reading process is constant from the start of the game processing cycle, the interval of the input reading process is constant, and the valid time of the winning ball detection signal is longer than the input reading process interval. For example, the microcomputer can more reliably detect the winning ball detection signal, and can easily manage the effective time of the winning ball detection signal. According to the invention of claim 4, since the interval of the input reading process is generated by the timer interrupt, it is not necessary to perform time management by software, and software development is facilitated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a timing chart of a game processing cycle and an input signal monitoring cycle of the embodiment.

FIG. 3 is an exemplary flowchart showing a game process of a main control unit of the embodiment.

FIG. 4 is an exemplary flowchart illustrating an input reading process of the main control unit according to the embodiment.

FIG. 5 is a structural diagram of an input buffer and an input result flag according to the embodiment;

FIG. 6 is an exemplary flowchart illustrating an input determination process of the main control unit according to the embodiment.

FIG. 7 is a table showing an input determination pattern according to the embodiment;

FIG. 8 is a timing chart of an input reading process and an input determining process according to the embodiment;

[Explanation of symbols]

 1 main controller 1a microcomputer (input monitoring means)

Claims (4)

[Claims] 1. A microcomputer which is mounted on a pachinko machine and executes a series of processing relating to a game at each cycle,
A game control device of a pachinko machine that starts a game process corresponding to a winning ball detection signal in response to a winning ball detection signal input from a detection switch mounted on the pachinko machine.
A game control device for a pachinko machine, comprising: input signal monitoring means for performing a search for a winning ball detection signal a plurality of times each time shorter than the effective time of the winning ball detection signal during a single game processing cycle. 2. An input monitoring unit performs a plurality of input reading processes in one game processing cycle, and performs one input determination process based on the plurality of input reading processes in a next game processing cycle. The game control device for a pachinko machine according to claim 1, wherein: 3. The game control device for a pachinko machine according to claim 2, wherein the interval of the input reading process is constant from the start of the game processing cycle. 4. The game control device for a pachinko machine according to claim 2, wherein the interval of the input reading process is generated by a timer interrupt.