JP2000332717A5 - - Google Patents

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Publication number
JP2000332717A5
JP2000332717A5 JP2000117870A JP2000117870A JP2000332717A5 JP 2000332717 A5 JP2000332717 A5 JP 2000332717A5 JP 2000117870 A JP2000117870 A JP 2000117870A JP 2000117870 A JP2000117870 A JP 2000117870A JP 2000332717 A5 JP2000332717 A5 JP 2000332717A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2000117870A
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JP4416268B2 (ja
JP2000332717A (ja
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Priority claimed from US09/307,812 external-priority patent/US6522671B1/en
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Publication of JP2000332717A publication Critical patent/JP2000332717A/ja
Publication of JP2000332717A5 publication Critical patent/JP2000332717A5/ja
Application granted granted Critical
Publication of JP4416268B2 publication Critical patent/JP4416268B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2000117870A 1999-05-10 2000-04-19 マルチプレクサ、デマルチプレクサおよびインターフェース装置 Expired - Lifetime JP4416268B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/307,812 US6522671B1 (en) 1999-05-10 1999-05-10 Protocol independent sub-rate device
US09/307812 1999-05-10

Publications (3)

Publication Number Publication Date
JP2000332717A JP2000332717A (ja) 2000-11-30
JP2000332717A5 true JP2000332717A5 (ja) 2007-03-08
JP4416268B2 JP4416268B2 (ja) 2010-02-17

Family

ID=23191261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000117870A Expired - Lifetime JP4416268B2 (ja) 1999-05-10 2000-04-19 マルチプレクサ、デマルチプレクサおよびインターフェース装置

Country Status (4)

Country Link
US (2) US6522671B1 (ja)
EP (1) EP1052794B1 (ja)
JP (1) JP4416268B2 (ja)
CA (1) CA2304118C (ja)

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US8595538B2 (en) * 2008-03-03 2013-11-26 Quintic Holdings Single-clock-based multiple-clock frequency generator
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JP5993776B2 (ja) * 2013-03-29 2016-09-14 株式会社日立製作所 データ伝送システム及び受信装置

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