JP2000305815A - Duplex information processor, memory dumping method and computer readable recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high speed and sure memory dumping by a small quantity of hardware. SOLUTION: A register part 7 can read out or write data from/in a required register or flip flop to which a specific address of a memory space is previously allocated by using a command and an address obtained from a processor 2 or a bus part 6. A dump control part 9 controls data transfer operation between a memory on a CPU board 1a of a duplexed party and its own memory 3 through a system bus 13 by using the register part 7. A memory control part 4 controls the reading/writing data from/in the memory 3 by an instruction from the processor 2 or the dump control part 9. When a processor control part 5 is set up to the master side, the control part 5 interrupts the processor 2 by an error signal or at the end of data transfer operation, and when set up to the slave side, suppresses the processor 2 so as not to write data in its memory by an error signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant information processing system, and more particularly to a redundant information processing apparatus with an online memory dump function and a memory dump method.

[0002]

2. Description of the Related Art When a failure occurs in a CPU subsystem system, the CPU subsystem system is disconnected.
Therefore, the contents of the memory of the CPU subsystem cannot be directly confirmed. In such a case, in a redundant information processing system that is redundant for improving reliability, a function of copying the memory contents of the separated CPU subsystem to the memory of another CPU subsystem that is operating normally, That is, the memory dump function makes it possible to collect necessary information and to store the collected data in a file device or the like. At this time, it is desirable to dump and collect the contents of the memory at the time of failure occurrence online without stopping the operation of the memory for failure analysis.

An example of this kind of prior art is disclosed in Japanese Unexamined Patent Publication No.
No. 82326, “On-line memory dump device”
It is described as. This dump device enables a memory dump to be collected online, and implements a memory dump method that does not lose continuity of the dump data even if a memory rewrite operation by operation data occurs during the dump. It is intended to be. For this reason, this conventional method is configured to function as a duplicated memory during normal operation, execute a disconnection command from software when an abnormality is detected, and separate the duplicated memory into an operation memory and a dump memory. Further, the operation memory and the dump memory are distinguished by using the most significant bit of the address, the dump memory is designated by the most significant bit, and a memory dump is collected.

Another example of this kind of prior art is described as a "memory dump system" in Japanese Patent Application Laid-Open No. 9-16441. In this memory dump system, a redundant (at least three-fold) information processing device subsystem including a CPU, a memory, and an input / output control device is connected to a bus interface device. Take a majority vote on data from the system.

[0005] Each of the input / output control devices includes instruction means for instructing the start and end of a memory dump for transferring the contents of the memory of the own system to the memory of the other system. A memory dump control unit for sequentially reading out the contents of the self-system memory and sending out the contents to the bus interface device.

Further, the bus interface device has transmission control means for sequentially controlling the contents of the memory transmitted from the input / output control device to another system memory.

[0007]

However, the first problem of the conventional system described in Japanese Patent Application Laid-Open No. 2-82326 is that a separate command must be executed, so that an event requiring data analysis occurs. In other words, the processor executes another instruction in the time until the software detects the abnormality and executes the command, and the contents of the memory are rewritten.

Further, the second problem is that in this method,
Since the operation memory and the chip select of the dump memory are switched by designating the most significant bit of the address, only one half of the usable memory space can be used as the operation memory. 1/2 of available memory space
Disabling the system for the dump function hinders effective use of system resources, and has a great effect on the system.

Further, the prior art described in Japanese Patent Application Laid-Open No. 9-16441 described above has a configuration in which the contents of a memory are temporarily read out to a bus interface device and then transferred to a memory of another system in order to perform a memory dump. Because
There is a first problem that hardware such as a bus interface device is required.

[0010] Further, a second extra time is required for the transmission control time in the bus interface device.
There is a problem.

A first object of the present invention is to provide a dual information processing apparatus which can use a small amount of hardware, reliably prevent memory rewriting at the time of occurrence of a failure, and can collect a memory dump. It is to provide a memory dump method.

A second object of the present invention is to provide a dual information processing apparatus which can effectively utilize memory resources without using a small amount of hardware and allocating a specific address for a dump memory at high speed. It is to provide a dump system.

[0013]

According to a first aspect of the present invention, there is provided a dual information processing apparatus in which two CPU subsystems operating in a dual mode are connected by a system bus. Detects the failure, inhibits writing to the memory of one of the CPU subsystems, retains the data at the time of the failure occurrence in the memory, and causes the other CPU subsystem to store the retained data via the system bus. And read
It is characterized in that a memory dump can be collected.

According to a second aspect of the present invention, there is provided a dual information processing apparatus in which a master side and a slave side CPU subsystem operating in a dual system are connected by a system bus. Failure detection means for outputting an error signal when an abnormality of the duplicated information processing apparatus is detected; processor control means for generating a processor reset signal in response to the error signal; and inhibiting writing of the memory by the processor reset signal A master CPU
The subsystem includes a failure detecting unit that outputs an error signal when detecting an abnormality in the redundant information processing device, a first storage unit that stores a dump address of a memory, and a second storage unit that stores a memory read command executed at the time of a memory dump. A third storage means for storing a buffer address of the memory;
Storage means for storing a memory write command, and an address of the first storage means and a read command for the second storage means are output to the system bus in response to the error signal. And the slave CPU
Control means for reading the dump data from the subsystem and storing the dump data in a memory buffer designated by the third storage means by a write command of the fourth storage means, wherein the memory dump operation is performed independently of the processor operation. Is performed.

According to a third aspect of the present invention, there is provided a dual information processing apparatus in which CPU boards each including a processor and a memory are connected via a system bus and perform the same operation at the same time. A register unit that includes a plurality of registers and flip-flops to which specific addresses of a memory space are assigned in advance, and that can read or write a desired register or flip-flop according to a command and an address from the processor or the system bus; A dump control unit that controls a data transfer operation between the memory on the CPU board of the duplication partner and the own memory via the system bus by using the register unit according to the instruction; and the processor or the dump control unit. Read and write the memory according to instructions from A memory control unit for controlling, a failure detection unit for outputting an error signal when an abnormality of the redundant information processing device is detected, and the processor when the error signal or the data transfer operation is completed when set to the master side. A processor control unit that suppresses the writing of the memory to the processor by the error signal when the slave side is set,
When the processor set on the master side receives an interrupt due to the error signal, it executes a dump start program for setting the register to perform the data transfer operation, and terminates the data transfer of one memory block. A dump end program that executes a dump program that outputs data of the memory block to the outside when an interrupt is received by the CPU, and releases a write inhibition of the memory set on the slave side when an interrupt is received by the completion of the data transfer. Is performed.

According to the memory dump method of the present invention, there are provided two CPUs on a master side and a slave side operating in a dual system.
In a memory dump method in a redundant information processing device in which subsystems are connected by a system bus, the slave CPU subsystem generates a processor reset signal in response to the error signal when detecting an abnormality of the redundant information processing device. And a procedure for inhibiting the writing of the memory by the processor reset signal, wherein the master-side CPU subsystem outputs a memory dump address error signal when detecting an abnormality of the redundant information processing apparatus; A procedure for storing a memory dump address, a memory read command to be executed at the time of memory dump, a memory buffer address, and a memory write command; and outputting the dump address and the read command to the system bus in response to the error signal. The system bus And having a step of reading the dump data from the CPU subsystem of the slave side, and a procedure for storing the dump data to said memory buffer by said write command to.

More specifically, according to the present invention, the processor and the memory are configured on the same CPU board, and
The PU boards are duplicated to form a redundant configuration. When a system bus failure or a failure that causes the system to become unresponsive occurs on a duplicated CPU board in a system in which these CPU boards operate simultaneously at the same time, the redundant configuration is used. Both CPU boards detect the failure, inhibit writing to the memory of one CPU board, retain the data at the time of failure occurrence on that memory, read the retained data from the other CPU board, and collect a memory dump .

[0018] Of the CPU boards of the duplex configuration, the CPU board from which dump data is read out when a failure occurs is designated as the master side C.
Called PU. The other CPU that suppresses writing to the memory and retains data is referred to as a slave CPU. In FIG. 1, when the CPU board is the master-side CPU, the processor control unit 5 generates an interrupt to the processor 2 upon receiving an error signal, and starts the dump program. Upon receiving the interrupt, the processor 2 instructs the dump control unit 9 about the dump address, the dump data capacity, the address of the buffer on the memory of the own CPU board, and the buffer capacity. The dump control unit 9 reads the dump data from the memory on the CPU board on the slave side via the system bus and writes the dump data into the memory 3 of the own CPU board.

When the CPU board is a slave-side CPU board, the processor control unit 5 resets the processor 2 upon receiving an error signal from the fault detection unit 8. The memory control unit 4 suppresses the writing of the memory by the signal of the processor reset. As a result, data at the time of occurrence of the failure is held in the memory of the slave CPU.

[0020]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. This embodiment is a dual information processing system with an online memory printer, and has two CPs.
The U boards 1 and 1a are connected via a system 13 to an input / output control device 10 that controls a disk device 11 and a console 12. CPU boards 1 and 1a
Is a processor system of the same configuration that performs the same processing at the same time by the dual system, and has a memory dump function.

In the following description, the master and slave of the redundant CPU are determined by the mounting position of the CPU board.
The CPU board 1 is a master CPU, and the CPU board 1a is a slave CPU. CPU board 1a
Are the same as the components of the CPU board 1 and are distinguished by adding a suffix “a” to the reference numbers of the components of the CPU board 1.
The description of the components is omitted.

The CPU board 1 includes a processor 2, a memory 3, a memory control unit 4 for controlling the memory 3, a processor control unit 5 for outputting a control signal including a processor reset signal and an error interrupt signal to the processor 2, A bus unit 6, a register unit 7, a failure detection unit 8 that detects an abnormality in the system and outputs an error signal to the processor control unit 5, and transfers data between the memory 3 a and the memory 3 according to an instruction from the processor 2. A dump control unit 9 for controlling an operation (memory dump).

The processor 2 is connected to the memory 3 via a bidirectional bus line, and outputs a control signal to the memory control unit 4. This control signal includes a memory address and a memory read / write command, and inputs and outputs memory data via a bus line. Further, the processor 2 is connected to a register unit 7 described later by a bidirectional signal line, and is connected to the dump control unit 9 by a signal line. A signal line between the processor 2 and the register unit includes a read / write command for accessing the register, a register address and register data.

The memory control section 4 is a control section for reading and writing the memory 3 and outputs a memory address and a memory read signal or a memory write signal to the memory 3.

The processor control unit 5 outputs a control signal to the processor 2. This control signal includes a processor reset signal and an error interrupt signal, and the processor reset signal is also output to the memory control unit 4.

The bus unit 6 is connected to the system bus 13 and executes a transaction of the system bus 13. The bus unit 6 includes a processor 2, a memory 3, a memory control unit 4, a register unit 7, a dump control unit 9, and a signal line. Connected by A signal line from the bus unit 6 to the memory control unit 4 includes a memory access command and an address received from the system bus 13. A signal line between the bus unit 6 and the register unit 7 includes a register address, a register access command and data received from the system bus 13, and outputs an address to be output to the system bus 13 and a read / write signal. Contains commands and data.

The register section 7 includes a plurality of registers and storage means for flip-flops (hereinafter, referred to as "F / F"). These registers and F / F are provided in the memory space of the system. A specific address is assigned in advance. The register unit 7 is connected to the processor 2 and the bus unit 6 by bidirectional signal lines, and reads a desired register or F / F by designating a register address and a read / write command from the signal lines. And can light. Further, it is connected to the processor control unit 5 by a signal line, and outputs a control signal required for processor control. The control signal includes a master signal indicating that the CPU board 1 is a master board having a redundant configuration, and a reset release signal for releasing the reset state of the processor 2.

The failure detecting section 8 detects a system abnormality and outputs an error signal to the processor control section 5. The error signal monitors the state of the system bus and outputs a signal indicating that a bus error of the system bus 13 has been detected. The error signal also includes monitoring of the execution time of the program of the processor 2 and output of detection of an infinite loop of the program. Error signal.

The dump control unit 9 is responsive to an instruction from the processor 2 to store data in the memory 3a on the CPU board 1a of the duplication partner.
This is a circuit for controlling a data transfer operation (dump) between the CPU 2 and the memory 3 of the own CPU board 1, and is connected to the processor 2, the memory control unit 4, the bus unit 6, and the processor control unit 5 by signal lines. Dump control unit 9 and memory control unit 4
And a signal line to and from the bus unit 6 include the addresses of the dump source and the dump destination, and read / write commands. The signal lines of the dump control unit 9 and the processor control unit 5 include signals indicating the end of transfer and the completion of dump for each block.

The input / output control device 10 is connected to the system bus 13 and is connected to the magnetic disk device 11 and the console device 1.
2 is a device for controlling input / output to / from the device.

Next, details of the memory control unit 4, the processor control unit 5, the register unit 7, and the dump control unit 9 will be described.
This will be described with reference to FIGS. 2, 3, 4, and 5, respectively.

FIG. 2 is a diagram showing one embodiment of the memory control unit 4 of FIG. Referring to FIG.
Is a circuit for storing a read or write command for the memory 3, and receives an output of a later-described selection circuit 204 and outputs it to the decoder 203. The register 202 is a circuit that receives the output of the selection circuit 204 and stores a memory address, and outputs the memory address to an address line to the memory 3. The decoder 203 is a circuit that decodes a command and generates a write signal and a read signal. The selection circuit 204 receives an address and a command from each of the processor 2, the bus unit 6, and the dump control unit 9, and selects an address and a command from one of them. The decoder 205 receives the control signals from the processor 2 and the dump control unit 9 and decodes them to output a selection signal to the selection circuit 204. When the decoder 205 receives a processor reset signal from the processor control unit 5, the decoding result Is invalidated, and the selection circuit 204 selects the bus unit 7.

FIG. 3 is a diagram showing one embodiment of the processor control 5 of FIG. In FIG. 3, an AND circuit 301
Receives the error signal from the failure detection unit 8 and the master signal from the register unit 7, performs a logical product operation, and outputs the result to the interrupt circuit 305. Inverter circuit 302
Is a circuit that outputs the above-mentioned inversion result of the master signal to the AND circuit 303. The AND circuit 303 performs an AND operation on the above-mentioned error signal and the inversion result of the master signal from the inverter circuit 302, and outputs the result to F / This is a circuit for outputting to F304. The F / F 304 is a circuit that is set in response to a logical product of the AND circuit 303 and is reset by a reset release signal from the register unit 7. F / F
The output of 304 is output as a processor reset signal on a signal line to the processor 2 and the memory control unit 4.

FIG. 4 is a diagram showing one embodiment of the register section 7. As shown in FIG. In FIG. 4, a selection circuit 401 is connected to each signal line from the processor 2 and the bus unit 6, selects one of them, and outputs a register access command and a register address on the signal line to the registers 402 and 403. . The register 402 stores a register read or register write access command, and the register 403 stores a register address. The address determination circuit 404 is a circuit that decodes the register address of the register 403 and determines whether or not the register address is a register address, and determines whether or not the register of the corresponding address exists in the CPU board 1. When the corresponding register exists in the CPU board 1, an operation corresponding to the register and the command of the register 402 is executed. As shown in FIG. 6, the registers 502 to 50 in the dump controller 9
7 is also included. The selection circuit 405 selects one of the register 403 and the register 402 and outputs it to a signal line to the bus unit 6. The F / F 406 is a circuit indicating whether the CPU board 1 is a master or a slave of a duplicated CPU board, and outputs a master signal here. Note that the F / F 406 is set by the slot mounting number of the CPU board 1 on the system bus at the time of startup. For example, when the CPU board 1 is mounted at an even-numbered slot position, the F / F 406 is set as a master and a master signal is output. F / F407 is
This is a circuit that indicates reset release of the processor 2 and is set by data on a signal line from the bus unit 6.

FIG. 5 is a diagram showing an embodiment of the dump control unit 9. In FIG. 5, a control circuit 501 is a circuit for controlling a dump operation, and includes six registers 502 to 502.
Reference numeral 507 stores the output of the selection circuit 508. The register 502 stores a count value of the number of data transferred to and from the memory 3a of the CPU board 1a, which is a duplication partner, and the count value is output to the control circuit 501. Register 503
Stores a read or write command to the memory 3a, and this command is output to the control circuit 501 and the bus unit 6. The register 504 stores the memory address of the memory 3a, and this address is output to the control circuit 501 and the bus unit 6. Further, the register 505 is provided in the memory 3
And stores the count value of the number of data transferred to the control circuit 501. Register 506 is
Stores a read or write command to the memory 3,
This command is output to the control circuit 501 and the memory control unit 4. The register 507 stores a memory address of the memory 3, and this address is output to the control circuit 501 and the memory control unit 4. The selection circuit 508 is a processor 2
Alternatively, the count / address / command from any one of the control circuits 501 is selected.

FIG. 6 shows the F / F on the CPU board 1.
FIG. 3 is a diagram showing addresses pre-assigned to registers. F / Fs 406 to 407 each have an address A
0 to A1 are assigned to the registers 502 to 50
7 are assigned addresses A2 to A7, respectively. By designating these addresses, the address determination circuit 404 in FIG. 4 individually identifies the registers and reads or writes the corresponding registers.

Next, the operation of the above-described embodiment will be described with reference to the drawings.

In FIG. 1, during normal operation, the CPU board 1 and the CPU board 1a are in a duplicated state, and they are performing the same operation at the same time. As mentioned earlier,
It is assumed that the CPU board 1 is a master board and the CPU board 1a is a slave board. Input / output operations to / from the magnetic disk device 11 and the console device 12 are executed via the input / output control device 10. The same programs such as the OS program and the business program are executed simultaneously by the processor 2 and the processor 2a. As a result, the contents of the memory 3 and the contents of the memory 3a are kept in the same state.

In this state, it is assumed that some abnormality occurs in the present system, for example, an error occurs on the system bus 13. At this time, the failure detection unit 8 of the CPU board 1 and the failure detection unit 8a of the CPU board 1a simultaneously detect a failure and output an error signal.

The operation of the processor control unit 5 in the CPU board 1 will be described with reference to FIG. When receiving the error signal from the failure detection unit 8, the AND circuit 301 calculates the logical product of the error signal and the master signal from the register unit 7 and outputs the logical product to the interrupt circuit 305. Where C
Since the PU board 1 is a master board, the master signal is o
n, the output of the AND circuit 301 is turned on, and the interrupt circuit 305 outputs an error interrupt signal to the processor 2. Upon receiving the error interrupt signal, the processor 2 activates a dump program as described later.

On the other hand, the operation of the CPU 1a at this time will be described with reference to the drawings. In the processor control unit 5a of the CPU board 1a, the master signal received from the register unit 7a is in the off state since the CPU board 1a is a slave board. The logical product of the AND circuit 301a becomes an off signal, and the error interrupt signal is not output to the processor 2a. On the other hand, the output of the inverter 302a, which is the inversion of the master signal, is an on signal,
The logical product of the D circuit 303a becomes an on signal, and outputs a processor reset signal to the processor 2a and the memory control 4a. Upon receiving the processor reset signal, the processor 2a enters a reset state and stops executing the program.

In the memory control unit 4a having the same configuration as that of FIG.
Reference numeral 5a outputs a signal for selecting the bus unit 6a to the selection circuit 204a regardless of other input signals. As a result, since the selection circuit 204a continues to select the bus unit 6a, the address and command from the processor 2a are not executed, and the contents of the memory 3a are protected. As a result, the slave side C
In the PU board 1a, when a failure is detected, the processor 2a is instantaneously reset to stop the execution of the program, and at the same time, writing to the memory 3a is suppressed, and valid dump data is held in the memory 3a. You.

Next, the CPU board 1 as the master board
The operation at the time of execution of the dump program started by the above will be described.

As described above, when a failure is detected in the CPU board 1, an error interrupt is output to the processor 2 and the dump program is started. Here, the dump program is a dump start program shown in FIGS.
It consists of a dump program and a dump end program.

FIG. 7 is a flowchart of the dump start program. In FIG. 7, first, the address A2 is designated, and the dump data capacity is written into the partner CPU / memory transfer count register (register 502 of the dump control unit 9) ( Step S701), designating the address A3, and
A read command is written into the PU memory access command register (register 503 of the dump control unit 9) (step S702), an address A4 is designated, and the other CPU memory address register (the dump control unit 9) is specified.
In the dump start address (0 for explanation)
Is written (step S703).

Next, address A5 is designated, and the CPU
The data capacity of the buffer prepared in the memory 3 is written into the memory transfer count register (register 505 of the dump control unit 9) (step S704), the address A6 is designated, and the own CPU / memory access command register (dump control unit) The write command is written into the register 506) (step S705), the address A7 is designated, and the head address of the buffer is written into the own CPU / memory address register (register 507 of the dump control unit 9) (step S706).

The operation of the CPU board 1 and the CPU board 1a when executing the above steps S701 to S706 will be described with reference to the drawings.

First, the operation of the CPU board 1 when executing step S701 will be described with reference to FIGS. 1, 4 and 5. When the processor 2 specifies the address A2 and executes the write command to the register 502,
The register address A2 and the write instruction are output on the signal line from the processor 2 to the register unit 7, and the dump data capacity as the write data is output on the signal line from the processor 2 to the dump control unit 9.

The selection circuit 401 of the register unit 7 selects the processor 2 when executing the processor instruction.
The address A2 from the processor 2 is stored in the register 403, and subsequently, the write instruction is stored in the register 402. The address determination circuit 404 decodes the address A2 of the register 403, and decodes the address A2 of the register
Instructs data storage. At this time, the selection circuit 508 of the dump control unit has selected the processor side, the dump data capacity on the signal line of the processor 2 is written into the register 502, and the operation in step S701 ends.

Next, the operation when step S702 is executed will be described. Processor 2 specifies address A3,
When a write command to the register 503 is executed, a register address A3 and a write instruction are output on a signal line from the processor 2 to the register unit 7, and read data as write data is written on a signal line from the processor 2 to the dump control unit 9. The command is output. As in step S701, the address A3 is stored in the register 403 of FIG. 4, and a read command is stored in the register 503 of FIG.

Similarly, when the step S703 is executed, the dump start address is stored in the register 504 of FIG. 5, and when the step S704 is executed, the memory 3 is stored in the register 505 of FIG.
Buffer command prepared in step S705, a write command to the register 506 in FIG.
At the time of execution of 06, the head address of the buffer is sequentially stored in the register 507 of FIG.

The execution of step S706 causes the register 5
When the buffer head address is stored in 07, the control circuit 501 starts operating. The read command of the register 503 and the dump start address (memory address 0) of the register 504 are output to the bus unit 6. The bus part 6
The read command and the dump start address are output on the system bus 13 to request a memory read at the memory address 0.

When the CPU board 1a receives a read command and an address from the system bus 13, it starts a memory read operation. Next, the operation of the CPU board 1a will be described.

In FIG. 1, the bus unit 6a outputs a read command received from the system bus 13 and a memory address 0 to the memory control unit 4a. In the memory control unit 4a, as described above, the selection circuit 204a selects the bus unit 6a by the processor reset signal from the processor control unit 5a, and the read command from the bus unit 6a via the selection circuit 204a is stored in the register. At 201a, the memory address 0 is stored in the register 202a.

Further, the memory control unit 4 a
03a and the address 0 of the memory from the register 202a in the memory 3a.
To read the data at address 0 of the memory 3a.

The data at address 0 read from the memory 3a is output to the system bus 13 via the bus section 6a. When the data of the address 0 appears on the system bus 13, the CPU board 1 inputs the data to the memory 3 via the bus unit 6. At this time, the dump control unit 9 outputs the write command of the register 506 and the buffer start address of the register 507 to the memory control unit 4 and instructs writing.

In the memory control unit 4, when the above-described instruction signal from the dump control unit 9 is received by the decoder 205,
The selection circuit 204 selects the dump control unit side, and stores the write command in the register 201 and the buffer start address in the register 202. Further, a write signal is output from the decoder 203 to the memory 3, and address 0 data from the bus unit 6 is written to the buffer start address of the memory 3.

After writing data to the memory 3, in the dump control unit 9, the control circuit 501 subtracts the count values of the registers 502 and 505, adds the respective addresses of the registers 504 and 507, and selects the selection circuit. Write back via 508. Then, the command of the register 503 and the dump address of the register 504 are output to the bus unit 6 again, the data is read from the memory 3a of the CPU board 1a, and the buffer indicated by the register 507 of the memory 3 in the same manner as the operation described above. Write to address. Thereafter, this operation is repeated until the count value of the register 505 becomes "0", and the dump data is sequentially stored in the buffer of the memory 3.

When the count value of the register 505 becomes "0", it means that the data transfer of one block has been completed, and the control circuit 501 outputs a buffer transfer end signal to the processor control unit 5. Processor control unit 5
When receiving this signal, the interrupt circuit 305 generates an interrupt to the processor 2. The processor 2 executes the dump program illustrated in FIG. 8 by interruption.

In FIG. 8, the dump data stored in the buffer of the memory 3 is output to the disk device 11 or the console 12 (step S801). This output is performed via the input / output control device 10 and is performed by a method such as direct memory access between a normal memory and the input / output device. Next, the address A5 is designated, the data capacity of the buffer is written to the own CPU / memory transfer count register (register 505 of the dump control unit 9) (step S802), and the address A7 is designated, Start address of own CPU
The data is written to the memory address register (register 507 of dump control unit 9) (step S803).

When the address is set in the register 507 by the execution of step S803, the dump control unit 9 starts the operation. The read command of the register 503 and the dump address of the register 504 are output to the system bus 13 via the bus unit 6, and the dump data is read from the CPU board 1a and stored in the buffer address indicated by the register 507. Then, the count value of the register 505 is subtracted, and dumps are sequentially collected from the CPU board 1a.

The count value of the register 505 becomes "0" again.
At this time, an interrupt to end the buffer transfer is generated from the processor control unit 5 to the processor 2, and the dump collection is continued by executing the dump program of FIG.

When the count value of the register 502 for counting the dump capacity during dump collection becomes “0”,
Since the data transfer of all blocks to be dumped has been completed, the control circuit 501 outputs a signal indicating the end of the dump transfer to the processor control unit 5. Processor control unit 5
Receives this signal, generates an interrupt signal from the interrupt circuit 305, and interrupts the processor 2. Upon receiving this interrupt, the processor executes the dump end program shown in FIG.

In FIG. 9, the dump data stored in the buffer is transferred to the disk device 11 or the console 12.
(Step S901). This operation is the same as step S801 in FIG.

Next, when the processor 2 designates the address A1 and executes a write instruction for setting the reset release F / F (F / F407) (step S902), the address A1 is stored in the register 403 of the register section 7. A write command is written to the register 402. At this time, when address detection circuit 404 detects address A1, F / F
At the same time as setting F407, a write command and an address A1 are output to the bus unit 6 via the selection circuit 405. The bus unit 6 stores the write command and the address A
1 is output to the system bus 13.

When a write command and an address A1 appear on the system bus 13, the CPU board 1a fetches them into the bus unit 6a and outputs them to the register unit 7a. The register section 7a selects the bus section side of the selection circuit 401a, and writes a write command to the register 403a.
Address A1 is taken into 2a. Then, the address determination circuit 404a detects that the address is A1, executes a write command, and sets the F / F 407a. The reset release signal from the F / F 407a is output to the processor control unit 5a.

When receiving the reset release signal, the processor control section 5a resets the F / F 304a. As a result, the processor reset signal to the processor 2a disappears, and the processor 2a becomes operable. FIG.
In the memory control unit 4a, when the processor reset signal disappears, the decoder 205a becomes valid, decodes the input signal, and outputs the result to the selection circuit 204.

With the above, the dump operation shown in FIGS. 7 to 9 is completed. In the above description, the CPU board 1 is connected to the master side CP.
U and the CPU board 1a are described as slave CPUs, but since these CPU boards have the same configuration,
The same operation is performed when the U board 1 is the slave CPU and the CPU board 1a is the master CPU.

Next, another embodiment of the present invention will be described.

In FIG. 5, register 5 of the dump control unit
02 to 607 can be set by the processor, and are set by the processor when executing the programs in FIGS. 8 and 9. However, the initial values of the registers 502 to 507 may be set to predetermined values, and the dump operation may be started upon receiving an error signal from the processor control unit 5. With such a configuration, the dump start program in FIG. 7 becomes unnecessary, and there is also an effect that dump collection can be started immediately when a failure occurs.

[0072]

According to the present invention, there is a first effect that when a failure is detected, the processor can be reliably reset and the writing of the memory can be suppressed at a high speed with a small amount of hardware. . That is, a failure detection unit (the failure detection unit 8 in FIG. 1), a processor control unit that generates a processor reset signal in response to the error signal (the processor control unit 5 in FIG. 1), and writing of the memory by the processor reset signal. This is because a memory control unit (the memory control unit 4 in FIG. 1) for suppressing is provided.

Further, there is a second effect that all memories usable in the system can be used as operation memories without allocating a dedicated address in the memory space for the memory to be dumped. First storage means (register 504 in FIG. 5) for storing a dump address of a memory, second storage means (register 503 in FIG. 5) for storing a memory read command to be executed at the time of dumping, and a buffer address of an online memory , A fourth storage means (register 506 in FIG. 5) for storing a memory write command, and an address of the first storage means and a second And a control means (control circuit 501 in FIG. 5) for outputting the read command of the storage means, reading the dump data from the slave CPU 1a, and storing the dump data in the memory buffer designated by the third storage means. .

Further, by executing the dump operation on the dump controller 9, the third effect that the operation load on the processor 2 related to the dump operation is reduced, the system performance is prevented from deteriorating, and the system resources can be effectively used. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a detailed diagram of a memory control unit in FIG. 1;

FIG. 3 is a detailed diagram of a processor control unit in FIG. 1;

FIG. 4 is a detailed view of a register unit in FIG. 1;

FIG. 5 is a detailed view of a dump control unit in FIG. 1;

FIG. 6 is a diagram showing address allocation of F / Fs and registers in the embodiment shown in FIG. 1;

FIG. 7 is a flowchart of a dump start program in the embodiment shown in FIG. 1;

8 is a flowchart of a dump program in the embodiment shown in FIG.

FIG. 9 is a flowchart of a dump end program in the embodiment shown in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU board 1a CPU board 2 Processor 3 Memory 4 Memory control unit 5 Processor control unit 6 Bus unit 7 Register unit 8 Failure detection unit 9 Dump control unit 10 Input / output control unit 11 Disk device 12 Console 13 System bus 201 Register 202 Register 203 Decoder 204 selection circuit 205 decoder 301 AND circuit 302 inverter circuit 303 AND circuit 304 flip-flop (F / F) 305 interrupt circuit 401 selection circuit 402 register 403 register 404 address determination circuit 405 selection circuit 406 flip-flop (F / F) 407 flip-flop (F / F) 501 Control circuit 502 Register 503 Register 504 Register 505 Register 506 Register 507 Register 508 Select A road

Claims (6)

[Claims] In a redundant information processing apparatus in which two CPU subsystems operating in a dual system are connected by a system bus, when a failure occurs, both CPU subsystems detect the failure and write data to one CPU subsystem memory. And a memory for holding the data at the time of the occurrence of the failure, and allowing the other CPU subsystem to read the held data via the system bus and collect a memory dump. Information processing device. 2. A dual information processing apparatus in which two master subsystems and a slave side CPU subsystem operating in a dual system are connected by a system bus, wherein the slave side CPU subsystem detects an abnormality of the redundant information processing apparatus. A master detecting unit comprising: a fault detecting unit that outputs an error signal; a processor controlling unit that generates a processor reset signal in response to the error signal; and a memory controlling unit that suppresses writing to the memory by the processor reset signal. The subsystem includes: a failure detection unit that outputs an error signal when detecting an abnormality of the redundant information processing apparatus; a first storage unit that stores a dump address of a memory; and a second storage unit that stores a memory read command executed at the time of a memory dump. Storage means for storing the buffer address of the memory A third storage unit, a fourth storage unit for storing a memory write command, and an address of the first storage unit and a read command of the second storage unit to the system bus in response to the error signal. Control means for outputting dump data from the CPU subsystem on the slave side and storing the dump data in a memory buffer designated by the third storage means by a write command of the fourth storage means. A dual information processing apparatus for executing a memory dump operation irrespective of a processor operation. 3. C, each including a processor and a memory.
In a redundant information processing device in which a PU board is connected via a system bus and performs the same operation at the same time, each of the CPU boards includes a plurality of registers and flip-flops to which specific addresses in a memory space are assigned in advance, and the processor or A register unit that can read or write a desired register or flip-flop according to a command and an address from the system bus; and a memory on a CPU board of a duplication partner and its own memory using the register unit according to an instruction from the processor. A dump control unit that controls a data transfer operation via the system bus between the processor and the memory control unit that controls reading and writing of the memory in accordance with an instruction from the processor or the dump control unit. Outputs an error signal when detected A failure detection unit that interrupts the processor upon completion of the data transfer operation if the error signal or the data transfer operation is set on the master side; A processor control unit that suppresses writing of memory, wherein the processor set on the master side executes a dump start-up program that sets the register to perform the data transfer operation when interrupted by the error signal. Run,
Also, when an interrupt due to the end of the data transfer of one memory block is received, a dump program for outputting the data of the memory block to the outside is executed. A duplicated information processing apparatus for executing a dump end program for canceling write inhibition of a memory. 4. A register set for performing the data transfer, wherein a necessary value is set in advance as an initial value, and the dump start program is made unnecessary. The duplicated information processing apparatus according to the above. 5. A memory dump method in a dual information processing device in which two CPU subsystems, a master side and a slave side, operating in a dual system are connected by a system bus, wherein the slave side CPU subsystem comprises: A procedure for generating a processor reset signal in response to the error signal upon detecting an error in the memory, and a procedure for inhibiting writing of the memory by the processor reset signal. A procedure for outputting a memory dump address error signal upon detection of a device abnormality; a procedure for storing a memory dump address, a memory read command to be executed at the time of memory dump, a memory buffer address and a memory write command; In response, the system A step of outputting the dump address and the read command to the slave bus and reading the dump data from the CPU subsystem on the slave side via the system bus; and a step of storing the dump data in the memory buffer by the write command. A memory dump method comprising: 6. A memory dump method in a redundant information processing device in which two CPU subsystems of a master side and a slave side operating in a dual system are connected by a system bus, wherein the slave side CPU subsystem includes the redundant information. When detecting an abnormality of the processing device, the master CPU subsystem includes a procedure of generating a processor reset signal in response to the error signal, and a procedure of inhibiting writing of the memory by the processor reset signal. A procedure for outputting a memory dump address error signal when detecting an abnormality in the redundant information processing apparatus; a procedure for storing a memory dump address, a memory read command to be executed at the time of memory dump, a memory buffer address, and a memory write command; In response to an error signal, A procedure for outputting the dump address and the read command to the system bus and reading dump data from the CPU subsystem on the slave side via the system bus; and a procedure for storing the dump data in the memory buffer by the write command. A computer-readable recording medium storing a program for causing a computer to execute a memory dump method characterized by having a computer-readable recording medium.