JP3168973B2 - Redundant memory system with memory dump function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplicated memory system with a memory dump function for separating a duplicated memory when a failure occurs and collecting dump data.

[0002]

2. Description of the Related Art A conventional online memory dump method is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-82326. The purpose of this is to dump the memory status at the time of the failure without stopping the operation of the memory for failure analysis. Data continuity is not lost. FIG. 9 is an explanatory view showing such a conventional online memory dump method. In FIG. 9A, reference numeral 901 denotes an operation memory, and 902 denotes a dump memory. In operation, the memory is duplicated as shown in FIG. 9B. Function as a memory. When a disconnection command is input, one functions as the operation memory 901 and the other functions as the dump memory 902 as shown in FIGS. 9C and 9D. The dump memory 902 functions as a read-only memory.

FIG. 10 shows a dump device for realizing the above-mentioned online memory dump method. In FIG. 10, reference numeral 903 denotes a chip select signal * of the operation memory 901.
An exclusive OR circuit as a separate circuit for detecting a match / mismatch between CS (* indicates negative logic) and the separate command signal, and a reference numeral 904 as a read suppression circuit for obtaining a logical product of the separate command signal and the read signal RD It is an AND circuit. The separate command signal becomes “1” when a separate command is generated by the D flip-flop 965. Reference numeral 906 denotes an ACK output circuit, which is an AND circuit 961 or 962 that receives the separate command signal and the chip select signal * CS of the operation memory 901 or the dump memory 902, and a chip select signal of the operation memory 901 and the dump memory 902. An AND circuit 963 having * CS as an input, and these AND circuits 961 and 9
And an OR circuit 964 having the outputs of the L.62 and 963 as inputs.

Next, the operation will be described. First, in a normal operation state not at the time of the separate command, when the most significant bit “A11” of the address of the operation memory 901 is “0”, the operation memory 901 outputs the chip select signal * CS
Indicates a chip select state, and enables data writing and data reading to the operation memory 901. At this time, since the output of the separate circuit 903 also becomes “0”, the chip select signal * CS of the dump memory 902 also becomes “0” and the chip is selected. Therefore, the same data as the operation memory 901 is written to the same address in the dump memory 902.

[0005] Thereafter, when only the operation memory 901 is used for operation, a separate command is executed and the separate command signal is set to "1". When the most significant bit “A11” of the address is set to “0” and the operation memory 901 is chip-selected, the output of the separate circuit 903 is set to “1” and the dump memory 902 is not chip-selected. Therefore, the operation can be performed only with the operation memory 901. Further, when a dump operation is desired, the contents of the dump memory 902 can be read by setting the most significant bit of the address to “1”.

[0006]

However, in such a conventional online memory dump method, a separate command must be executed when the operation memory 901 is operated, so that an event necessary for data analysis occurs. However, there is a problem in that the processor executes another instruction and rewrites the contents of the memory until the software detects the abnormality and executes the separate command. In the conventional dump method, the operation memory 901 and the dump memory 9 are designated by designating the most significant bit of the address.
Since the chip select of No. 02 is switched, only １ ／ of the available memory space can be used as the operation memory, and there is a problem that the effective utilization of system resources is hindered.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and it is possible to collect dump data by separating a duplicated memory without executing a separate command from software when a failure occurs, and to collect dump data. Therefore, it is an object of the present invention to obtain a redundant memory system with a memory dump function, in which an address of a memory space is not allocated for the purpose, and all memories usable in the system can be used as operation memories.

[0008]

According to the first aspect of the present invention, a processor and a memory are identical.
It is configured on a CPU board, and the CPU board is duplicated.
With a memory dump function that is
Detects system errors in redundant memory systems
Failure detection means, and the failure detection means outputs when an abnormality is detected
Processor operation in response to an error signal
Processor system that generates a processor reset signal
Control means and a processor reset from the processor control means.
A write signal to the memory,
The processor and the system.
Register address and bus address to the bus connected to the bus
Read by specifying read and write / write commands
And writable registers and flip-flops
And a control signal required for controlling the processor.
A register unit for outputting to the processor control unit is connected.
It is characterized by having.

The invention according to claim 2 is a processor.
The server and the memory are configured on the same CPU board, and
The CPU board is redundant and has a redundant configuration.
In a redundant memory system with a memory dump function,
Fault detecting means for detecting an abnormality of the stem;
The step responds to an error signal output when the stage detects an abnormality.
A processor reset signal that stops the operation of the processor
Processor control means for generating and processor control means
Receiving the processor reset signal from the
Memory control means for suppressing writing to be performed,
Between the processor and the bus connected to the system bus
Register address and read / write command
Registers that can be read and written by specifying
And a flip-flop, and the processor
Outputting a control signal required for control to the processor control unit.
Register section is connected, and the register section is
Storage means for storing a dump address of the memory
And a second memory for storing a memory command to be executed at the time of dumping.
Storage means, and a third storage for reading the dump data.
Storage means and a dump in the first storage means when the dump is executed.
Address and a memory command to the second storage means.
Set each and read the data of the third storage means
In doing so, the CPU of the duplication partner is connected via the system bus.
The data is read from the memory on the board and the third
And control means for storing the data in a storage means.
You.

[0010] Further, the invention according to claim 3 is based on claim 1.
In the invention described in the above, the error output by the failure detecting means is output.
The error signal is a bus error detection signal of the system bus.
And the infinite number of program executions by the processor
It is a loop detection signal.

The invention described in claim 4 is the same as the claim 2.
In the invention described in the above, the error output by the failure detecting means is output.
The error signal is a bus error detection signal of the system bus.
And the infinite number of program executions by the processor
It is a loop detection signal.

The invention described in claim 5 is the first invention.
In the invention described in the above item, necessary for controlling the processor.
The control signal is a signal indicating that the CPU board is a master having a redundant configuration.
A master signal indicating that the board is a board, and the CPU
A signal indicating that memory data is being copied between boards
It is characterized by being a number.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 denotes a central processing unit (hereinafter, referred to as a CPU) board, which is a processor 2.
And a board on which the memory 3 is mounted, and is connected to the system bus B via the bus unit 7. Although not shown, the CPU board 1a has the same configuration, and the CPU board 1 and the CPU board 1a have a duplicated redundant configuration. The processor 2 is connected to the memory 3 by a bidirectional bus line, and outputs a control signal to the selection circuit 6. This control signal includes a memory address and a memory read / write command, and inputs and outputs memory data via a bus line.

The processor 2 is connected to a register section 8 to be described later by a bidirectional information line. The information line includes a read / write command for register access, a register address, and register data. . 4
Denotes a memory control unit, which controls read / write of the memory 3 and receives a control signal from the selection circuit 6 and
To output a memory address and a memory read signal or a memory write signal. Reference numeral 5 denotes a processor control unit, which outputs a control signal to the processor 2. This control signal includes a processor reset and error interrupt signal. Of these, the processor reset signal is also output to the memory control unit 4.

The selection circuit 6 receives a control signal from the processor 2 and a control signal from the bus unit 7, selects one of them, and outputs it to the memory control unit 4. The bus unit 7 includes:
A circuit that is connected to the system bus B and executes a transcushion of the system bus B. The circuit is connected to the memory 3 by a bus line, is connected to the selection circuit 6 by a control signal line, and is connected to a register unit 8 described later and an information line. Connected by A control signal line from the bus section 7 to the selection circuit 6 includes a memory access command and an address received from the system bus B. The information line from the bus section 7 to the register section 8 includes the address of the register received from the system bus B, the register access command and data, and the address output to the system bus B and the read / write command and data. Have been.

The register section 8 includes a plurality of registers and storage means for flip-flops (hereinafter, referred to as F / Fs). These registers and F / Fs store specific addresses in a memory space of the system. Are assigned in advance. The register unit 8 is connected to the processor 2 and the bus unit 7 via bidirectional information lines. By specifying a register address and a read / write command from these information lines, a desired register or F /
F can be read and written. The register unit 8 is connected to the processor control unit 5 by a signal line, and outputs a control signal necessary for controlling the processor. The control signal includes a master signal indicating that the CPU board 1 is a master board having a redundant configuration and a copy signal indicating that memory data is being copied between the CPU boards 1 and 1a.

Reference numeral 9 denotes a failure detection unit as failure detection means, which detects a system abnormality and outputs an error signal to the processor control unit 5. The error signal includes a signal that monitors the state of the system bus B and outputs when a bus error of the system bus B is detected, an error that monitors the execution time of the program of the processor 2 and outputs when an infinite loop of the program is detected. Signal is included. Reference numeral 10 denotes an input / output control unit, which is connected to the system bus B and controls input / output to / from the magnetic disk device 11 and the console device 12.

FIG. 2 is a block diagram showing details of the memory control unit 4. As shown in FIG. In the figure, a command register 20 receives a control signal from the selection circuit 6, stores a memory access command on the control signal, and outputs the memory access command to the decoder 203. Reference numeral 202 denotes an address register, which also receives a control signal from the selection circuit 6, stores a memory address on the control signal, and outputs it to an address line to the memory 3. The decoder 203
Decodes a command and generates a write signal and a read signal. An inverter 204 inverts a processor reset signal on a control signal line of the processor control unit 5. Reference numeral 205 denotes an AND circuit, which takes the logical product of the output of the inverter 204 and the write signal of the decoder 203 and outputs the result as a write signal of the memory 3.

FIG. 3 is a block diagram showing the details of the processor control unit 5. In FIG. 3, reference numeral 301 denotes an AND circuit, which receives an error signal received from the failure detection unit 9 and a master signal on the information line from the register unit 8. The logical product with the signal is output on a control signal line to the processor 2 as an error interrupt signal. An inverter 302 outputs an inverted result of the master signal to an AND circuit 303. This A
The ND circuit 303 is connected to the error signal and the inverter circuit 30.
The logical product of 2 is output to the F / F 304. This F / F30
4 is set in response to the logical product of the AND circuit 303 and reset by a copy signal on the information line from the register unit 8. The output of the F / F 304 is output as a processor reset signal on a control signal line to the processor 2 and the memory control unit 5.

FIG. 4 is a block diagram showing the details of the bus section 7. Reference numeral 401 denotes a register which stores a command from the register section 8 and outputs it to the system bus B. 40
Reference numeral 2 denotes a register which stores a command received from the system bus B and outputs the command to the selection circuit 406. Also, 40
Reference numeral 3 denotes a register which stores an address or data of a selection circuit 405 described later and outputs it to the system bus B.
Reference numeral 404 denotes a register which stores the address or data received from the system bus B, and outputs it to the selection circuit 406.

The selection circuit 405 selects one of the outputs of the register section 8 and the memory 3 and outputs it to the register 403. When an information line from the register section 8 is selected, an address and data on the information line are output, and when a bus line of the memory 3 is selected, memory data is output. The selection circuit 406 selects one of the outputs of the register 402 and the register 404 and outputs the selected output to the bus line of the memory 3, the control signal line of the memory control unit 4, and the information line of the register unit 8. Reference numerals 407 and 408 denote drivers / receivers, which register registers 401 to 404 to the system bus B.
Connect with

FIG. 5 is a block diagram showing details of the register section 8. As shown in FIG. In the figure, reference numeral 501 denotes a selection circuit.
This is connected to the processor 2 and the bus unit 7 via each information line, and outputs a register access command and a register address on one of the information lines to the registers 502 and 503. The register 502 is a selection circuit 5
01 stores a register read or register write access command, and a register 503 stores a register address output from the selection circuit 501. 504
Is an address determination circuit which decodes the register address of the register 503 and determines whether or not it is a register address.
It is determined whether or not it exists within. Here, when the corresponding register exists in the CPU board 1, the operation according to the command of the register and the register 502 is executed.

The address held in the register 503 is stored in the register section 8 and each of the F / Fs 505 to 50
7 and a specific address in the memory space individually allocated to the registers 508 and 509 in advance.
According to the decoding result by the address determination circuit 504, F
/ F or a register is specified. Here, F / F50
Reference numeral 5 indicates whether the duplicated CPU boards 1 and 1a are masters or slaves, and outputs a master signal. Also, the CPU on the system bus B at startup
The F / F 505 is set according to the slot mounting position of the board 1. For example, when the CPU board 1 is mounted at the even-numbered slot position, the CPU board 1 becomes a master, the F / F 505 is set, and a master signal is output.

The F / F 506 is a duplicated CPU.
Indicates that the board 1a is copying data in the memory, and is set by data on the information line from the bus unit 7. The data copy of the memory is performed by, for example, the CPU on the master side.
The memory data of the board 1 is transferred to the CPU board 1 on the slave side.
This is carried out by copying the data to the memory 3a of a. A register 507 as a first storage means is a register for setting a memory address of the memory 3a of the CPU board 1a, which is a duplication partner, for example, and is set by data on an information line from the processor 2. A register 508 serving as a second storage unit stores an access command (memory read or memory write) to the memory 3a of the CPU board 1a.
Is set by data on the information line of the processor 2.

Further, a register 509 as a third storage means is a register for storing write data for writing to the memory 3a of the CPU board 1a or data read from the memory 3a, and stores an output of the selection circuit 511. I do. The selection circuit 510 selects one of the registers 507 to 509 or the F / Fs 505 and 506 of the register unit 8 according to an instruction of the address determination circuit 504 as control means, and outputs data to an information line to the processor 2. .

The selection circuit 511 selects one of the data from the processor 2 and the data from the bus unit 7 and outputs the selected data to the register 509. At the time of writing data of the output of the processor 2 to the register 509, the processor 2
Is selected. Reference numeral 512 denotes a selection circuit which is a register 507 to 509 of the register unit 8 or an F / F
One of the address determination circuits 5 and 506
04 is selected according to the instruction, and output as data on the information line to the bus unit 7.

FIG. 6 shows the F / F in the register section 8 of FIG.
FIG. 5 is a diagram showing addresses pre-assigned to F505 and 506 and registers 507 to 509. F / F5
05 and 506 are assigned addresses A0 and A1, respectively, and registers 507 to 509 are assigned addresses A2 to A5, respectively. By designating these addresses, the address determination unit 504 individually identifies registers and reads or writes the corresponding registers.

Next, the operation will be described. In FIG. 1, during normal operation, the CPU boards 1 and 1a are duplicated, and perform the same operation. Now, it is assumed that the CPU board 1 is a master board and the CPU board 1a is a slave board. Input / output operations to / from the magnetic disk device 11 and the console device 12 are executed by the input / output control device 10. In addition, the same program is simultaneously executed by the processor 2 and the processor 2a as software such as an OS program and a business program.
As a result, the contents of the memory 3 and the contents of the memory 3a are kept in agreement.

Now, it is assumed that when some abnormality occurs in the system, for example, an error occurs in the system bus B. At this time, the failure detection unit 9 of the CPU board 1 and the CPU
The failure detection unit 9a of the board 1a simultaneously detects the failure and outputs an error signal. Therefore, as shown in FIG. 3, the processor controller 5 receives the error signal from the fault detector 9, and the AND circuit 301
From the master signal. Since the CPU board 1 is a master board, the master signal is turned on. Therefore, the output of the AND circuit 301 is turned on, and an error interrupt signal is output to the processor 2.
Upon receiving the error interrupt signal, the processor 2 starts a dump program described later.

At this time, the CPU board 1a operates as follows. Since all the components of the CPU board 1a are the same as those of the CPU board 1 side, C
Each block on the PU board 1a side will be described with a suffix [a]. Processor controller 5a of CPU board 1a
Since the CPU board 1a is a slave board, the master signal received from the register section 8a is in the off state. Therefore, the logical product of the AND circuit 301a becomes an off signal, and the error interrupt signal is not output to the processor 2a. On the other hand, the output of the inverter 302a that inputs the master signal is an on signal,
The logical product of the D circuit 303a becomes an on signal, and outputs a processor reset signal to the processor 2a and the memory control unit 4a. Upon receiving the processor reset signal, the processor 2a enters a reset state and stops executing the program.

A memory control unit 4a having the same configuration as that of FIG.
In the above, upon receiving the processor reset signal, the inverter 204a inverts the processor reset signal to make it an off signal and outputs the signal to the AND circuit 205a. AN
Since one of the input signals is an off signal, the D circuit 205a turns off the logical product output regardless of the write signal of the decoder 203 and invalidates the write signal output to the memory 3a. As a result, in the CPU board 1a on the slave CPU side, when a failure is detected, the processor 2a is immediately reset, the execution of the program is stopped, and at the same time, the writing to the memory 3a is suppressed. Valid dump data is retained.

Next, the CPU board 1 as the master board
The operation at the time of execution of the dump program started by the above will be described. When a failure is detected in the CPU board 1, an error interrupt is output to the processor 2, and the dump program is started. This dump program is executed as shown in FIG. First, in step S701, the processor 2 specifies the address A2 and specifies the address A2, that is, the register 507 of the register unit 8.
The dump start address (for example, address 0) is written in. Next, in step S702, the address A3 is designated, and the partner memory access code register,
The read command is written to the register 508 of the register section 8.

Subsequently, in step S703, the address A4 is designated to specify the other memory data register, that is, the address A4.
Data is read from the register 509 of the register section 8,
In step S704, the read data is written to the console device 12 or the magnetic disk device 11. Next, it is determined in step S705 whether data has been read up to the last memory address. If the data has not been read yet, in step S706, the next memory address is written to the register 507 of the register address A2. Write by instruction. Therefore, in step S703, the memory data of the next address is read, and in step S70
Output at 4. The dump program is executed by repeating the processing of steps S703 and S704 until all memory addresses are specified. On the other hand, if the data has been read up to the last memory address, the F / F 506 of the address A1 is set (step S70).
7).

Next, the CPU board 1 at the time of executing each step
The operation of the CPU board 1a will be described. First, the operation of the CPU board 1 when executing step S701 will be described with reference to FIGS. When the processor 2 specifies the address A2 and executes the write instruction of the register 507, the register address A2, the write instruction, and the memory address 0 which is the write data are output on the information line from the processor 2 to the register section 8. Selection circuit 5
01 selects the processor 2 when executing the processor instruction, and the address A2 from the processor 2 is stored in the register 5
03, and then the write instruction is stored in the register 502. The address determination circuit 504 is a register 503
, And issues a data storage instruction to the register 507. The register 507 stores the memory address 0 output on the information line from the processor 2, and the operation in step S701 ends.

Next, in step S702, the processor 2
Specifies the address A3 and executes the write instruction of the register 508, the register address A3, the write instruction, and the read command which is the write data are output on the information line from the processor 2 to the register section 8. At this time, the address A3 is stored in the register 503 of FIG. 5 as in step S701, and a read command is stored in the register 508 in accordance with an instruction from the address determination circuit 504. Then, in step S703, the processor 2 sets the address A
4 and the read instruction of the register 509 is executed, a read instruction is output from the processor 2 to the register address A4 on the information line to the register section 8.

In the register section 8, the address A4 from the processor 2 is stored in the register 503, and the read instruction is subsequently stored in the register 502. The address determination circuit 504 decodes the address A4, and
9 and the selection circuit 512
Is sequentially switched to the register 507 and the register 508 to output a memory 0 address and a read command on the information line to the bus unit 7.

In the bus section 7 of FIG. 4, when a read command on the information line from the register section 8 is received, it is stored in the register 401 and output to the system bus B via the driver / receiver circuit 407. The selection circuit 405 selects this processor at the time of executing an instruction from the processor 2, and upon receiving an address 0, it selects this processor.
5, and is output to the system bus B via the driver / receiver circuit 408. Then, a memory read of memory address 0 is requested to the system bus B.

Next, the operation of the CPU board 1a when step S703 is executed will be described. In FIG. 4, the bus section 7a
Indicates the read command received from the system bus B to the register 402a, and the memory address 0 to the register 404a.
Respectively. CPU board 1 is system bus B
, The memory read operation is started. Selection circuit 406a
Is the read command of the register 402a and the register 40
4a are sequentially selected and the selection circuit 6
Output to a. The selection circuit 6a selects the control signal line of the bus section 7a during the memory read operation, and selects the bus section 7a.
From the memory controller 4a and the read command from the memory controller 4a.

For this reason, the memory control unit 4 a
The read command from a is stored in the register 201, and the memory address 0 is stored in the register 202. Further, it outputs the read request signal of the decoding result of the decoder 203 and the address 0 of the register 202 to the memory 3a. Therefore, the memory 3a receives the output from the memory control unit 4a and outputs the data at the address 0 to the data bus line. In FIG. 4, when the bus unit 7a receives the memory data on the bus line, it stores it in the register 403 via the selection circuit 405a. Then, the data of the register 403 is output to the system bus B and returned to the CPU board 1. As a result, the CPU board 1a ends the memory read operation of the address 0 of the memory received from the system bus B.

Next, as described above, 0 is placed on the system bus B.
When the data of the address is returned, the CPU board 1 stores the address 0 data in the register 404 of the bus unit 7 in FIG. Further, the data is output to the register section 8 via the selection circuit 406. When the register unit 8 receives the address 0 data from the bus unit 7, the selection circuit 511 selects the address 0 data of the bus unit 7 and stores it in the register 509. The selection circuit 510 selects the register 509 and returns the address 0 data to the processor 2 as read data. Here, during execution of the register read instruction of the register 509, the selection circuit 511
Selects the data of the bus unit 7, and the selection circuit 510 selects the register 509. This allows register 50
9 is completed.

On the other hand, in step S704, the processor 2 designates a predetermined output buffer address in the console device 12 or an output buffer address of the magnetic disk device 11, and executes a write command of address 0 data. Therefore, the address of the output buffer, the write instruction, and the address 0 data are output on the information line from the processor 2 to the register unit 8. Therefore, the register 50 shown in FIG.
2, the write instruction is stored in the register 503, and the address determination circuit 504 determines the address of the output buffer.

The address judging circuit 504 outputs the output buffer address to the register in the register section 8 and the F / F
Since the address is different from the address assigned to the data, the selection circuit 512 switches the register 502, the register 503, and the data from the processor 2 in this order, and outputs a write command, an output buffer address, and address 0 data to the bus unit 7.

In the bus section 7, the write command from the register section 8 is stored in the register 401, and the output buffer address is stored in the register 403. Then, a write command and an output buffer address are output to the system bus B, address 0 data is subsequently output, and a write operation to the system bus B is executed. When the input / output control device 10 receives the output buffer address and the write command from the system bus B, the input / output control device 10
2 or the address of the magnetic disk drive 11, the address 0 data is fetched from the system bus B, and is written to the output buffer of the subordinate console device 12 or the magnetic disk drive 11. Thus, the operation in step S704 is completed.

Next, the operation in step S705 will be described. The processor 2 determines whether the read address of the memory is the last address of the memory. Since the address 0 is different from the last address, the processor 2 executes the process of step S706. In this step S706, the next memory address is written to the address A2 in the same manner as the operation in the above-described step S701. Thereafter, the processor 2 dumps and outputs the memory address to be written to the register 507 in step S706 to the console device 12 or the magnetic disk device 11 in step S704 until the last address of the memory is detected in step S705.

After the end of the dump of the last address, the process of step S707 is executed. In this step S707, the processor 2 specifies the address A1 and the copy F /
When a write instruction for setting the F / F 506 as the F is executed, a register address A1, a write instruction, and F / F set data are output from the processor 2 to an information line from the processor 2 to the register unit 8. As in step S701, FIG.
The address A3 is stored in the register 503, and the set data is stored in the F / F 506 according to the instruction of the address determination circuit 504. Thus, the CPU board 1 is in a memory copy operation.

Further, after the writing of the F / F 506 is performed, the selection of the selection circuit 512 is sequentially switched to the register 502, the register 503, and the F / F 506 to output the write command, the address A1, and the F / F 506 to the bus unit 7. I do. 4, the write command from the register unit 8 is stored in the register 401, and the address A1 is stored in the register 403. Then, a write command and an address A1 are output to the system bus B.
The data of F506 is output, and the write operation of the system bus B is executed.

Next, the operation of step S707 in the CPU board 1a will be described. In FIG. 4, the bus section 7a
Stores the write command received from the system bus B in the register 402a and the address A1 in the register 404a. Upon receiving the write command and the address A1 from the system bus B, the CPU
The board 1a starts the register write operation. The selection circuit 406a sequentially selects the write command of the register 402a and the address A1 of the register 404a, and outputs them to the register 8a. Further, from system bus B to F / F5
06 is stored in the register 404a.
06a to the register section 8a.

In FIG. 5, the selection circuit 501a selects the bus section 7a when executing the register access from the bus section 7a.
The data is stored in the register 503a via the first register 01a. Further, the address determination circuit 504a determines the address A1 of the register 503a, and issues to the F / F 506a an instruction to capture the data of the F / F 506 received from the bus unit 7a. F / F5
06a takes in the data of the F / F 506 and enters the set state. The copy signal of the F / F 506a is output to a control signal line to the processor control unit 5a.

In the processor control unit 5a of FIG.
Upon receiving the copy signal, the F / F 304a is reset, and the processor reset signal output to the processor 2a is released. This processor reset signal is also output to the memory control unit 4a. As a result, the processor 2a exits the reset state and restarts after initialization. Also,
The memory control unit 4a of FIG. 2 receives the reset signal, inverts the reset signal by the inverter 204,
One input of the D circuit 205 is turned on. As a result, suppression of the write signal by the AND circuit 205 (of
f) is released, and the memory 3a becomes writable. Thus, the operation at the time of executing the dump program in FIG. 7 is completed.

Next, a copy operation for duplicating the memory again will be described. In the CPU board 1a,
When the copy F / F 506a is set, the processor 2
a, the copy F / F 506a is executed.
Is set, the copy program of FIG. 8 is started. When comparing the copy program of FIG. 8 with the dump program of FIG. 7, steps S704 and S804, and steps S707 and S807
Only the remaining steps S701, S702, S
703, S705, S706 and steps S801, S8
02, S803, S805, and S806 correspond to each other and are the same instruction. The only difference is that the dump program is executed on the CPU board 1 and the copy program is executed on the CPU board 1a.
The operation as a PU board is the same.

Steps S707 and S80
Reference numeral 7 denotes a difference between setting or resetting the copy F / F. The same operation is performed except that data to be written to the F / F 506 or the F / F 506a is different. Therefore, steps S801, S802, S803, S805, S
The description of the operations of 806 and S807 is omitted, and step S80
Only the operation No. 4 will be described. In FIG. 1, processor 2
a outputs a copy destination address of the memory 3a and a write command, and outputs this through the selection circuit 6a to the memory controller 4a.
Output to Further, it outputs the copy data to the bus line between the memory 3a. Here, during the memory access from the processor 2a, the selection circuit 6a selects the processor 2a side.

In the memory control section 4a of FIG. 2, the write signal generated by the decoder 203 is
5 to the memory 3a. Also, register 2
The copy address 02 is output to the memory 3a as a memory address. When the memory 3a receives the write signal and the copy address from the memory control unit 4a in this manner,
Write the copy data output on the data line.
With the above operation, the operation in step S804 ends.

Subsequently, steps S806, S803, and S804 are performed until the last address is reached in step S805.
Are sequentially repeated, so that the CPU board 1
The data of all memories is copied to the U board 1a.
If the last address has not been reached, step S80
7, the address A1 is designated, and data for resetting the copy F / F 506a is written.
The same operation as that described above is executed. As a result, the CPU board 1
a, the F / F 506a of the register section 8a and the F / F 506 of the CPU board 1 and the register section 8 are both reset. As a result, both CPU boards 1 and 1a can recognize that the copying operation has been completed, and the duplication operation can be performed.

[0054]

As described above, according to the present invention, when the failure detecting means detects a failure, an error signal is output to the processor control means, and a processor reset signal of the slave CPU board is generated. This was output to the processor and memory controller, and at the same time to stop the operation of the processor, to suppress the write operation of the memory, processor and Shi
Register address between the bus section connected to the stem bus
Address and read / write commands
Readable and writable registers and flip-flops
Control signal having a hop and necessary for controlling the processor
Is connected to the processor control unit, so that even if there is no memory disconnection command by software from the processor, the CP on the slave side is connected.
The effect is obtained that the memory on the U board is separated and dump data can be collected immediately from this.

Further, according to the present invention, when executing a dump program, dump data can be obtained by writing a dump address in one register, a memory read command in another register, and reading another register. Therefore, it is not necessary to allocate a dedicated address in the memory space for the dump memory, and all the memory available in the system can be used as the operation memory.
The effect is obtained that a memory dump can be collected only by executing access to these registers.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a redundant memory system with a memory dump function according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating details of a memory control unit in FIG. 1;

FIG. 3 is a block diagram illustrating details of a processor control unit in FIG. 1;

FIG. 4 is a block diagram illustrating details of a bus unit in FIG. 1;

FIG. 5 is a block diagram illustrating details of a register unit in FIG. 1;

FIG. 6 is an explanatory diagram showing an example of register address allocation in the register unit of FIG. 5;

FIG. 7 is a flowchart showing an execution procedure of a dump program according to the present invention.

FIG. 8 is a flowchart showing another execution procedure of the dump program according to the present invention.

FIG. 9 is an explanatory diagram showing a conventional dump system.

FIG. 10 is a block diagram showing a conventional dump device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 1a CPU board 2 Processor 3 Memory 4 Memory control part (memory control means) 5 Processor control part (processor control means) 7 Bus part 8 Register part 9 Fault detection part (Fault detection means) 504 Address judgment circuit (Control means) 505, 506 F / F (flip-flop) 507 register (first storage means) 508 register (second storage means) 509 register (third storage means)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/28-11/36 G06F 12/16 G06F 11/20

Claims (5)

(57) [Claims] 1. A redundant memory system with a memory dump function in which a processor and a memory are configured on the same CPU board, and the CPU board is duplicated to have a redundant configuration. A processor control unit for generating a processor reset signal for stopping the operation of the processor in response to an error signal output by the failure detection unit when an abnormality is detected; and receiving a processor reset signal from the processor control unit to control the memory. Memory control means for inhibiting writing , wherein the processor and a bus unit connected to a system bus
In between, register address and read / write command
Registers that can be read and written by specifying the
And a processor having a flip-flop and a flip-flop.
Output a control signal required for controlling the processor to the processor control unit
A dual memory system with a memory dump function, wherein a register unit is connected . 2. A processor and a memory having the same CPU module.
And the CPU board is duplicated.
Redundant memo with memory dump function that is redundant
In the system, a failure detecting means for detecting a system abnormality and an error signal output from the failure detecting means when the abnormality is detected.
A processor resource that stops the operation of the processor in response
A processor control means for generating a set signal; and a memory control means for receiving a processor reset signal from the processor control means to inhibit writing to the memory .
In between, register address and read / write command
Registers that can be read and written by specifying the
And a processor having a flip-flop and a flip-flop.
Output a control signal required for controlling the processor to the processor control unit
Register unit which is connected, wherein the register unit, first memory means for storing the dump address of said memory
And a second memory for storing a memory command to be executed at the time of dumping.
Storage means, a third storage means for reading dump data, and a dump address in the first storage means at the time of execution of the dump.
Are respectively set in the second storage means.
When reading data from the third storage means,
On the duplicated CPU board via the system bus
The data is read from the memory and stored in the third storage means.
Memory dump function redundant memory system characterized by having a pay controlling means. 3. The error signal output by the fault detecting means is a bus error detection signal of the system bus and a detection signal of an infinite loop of program execution by the processor. Dual memory system with memory dump function. 4. The system according to claim 2 , wherein the error signals output by the fault detecting means are a bus error detection signal of the system bus and a detection signal of an infinite loop of program execution by the processor. Dual memory system with memory dump function. 5. A control signal required for controlling the processor includes a master signal indicating that the CPU board is a master board having a duplex configuration, and a signal indicating that memory data is being copied between the CPU boards. The dual memory system with a memory dump function according to claim 1 , wherein: