JPH0772882B2 - Common memory protection method - Google Patents

Description

DETAILED DESCRIPTION [Outline] A protected area is provided for a common memory that can be accessed by a plurality of processors using the same access instruction as that for its own main memory, and a DM between the main memory and the common memory is provided.
A A simple data protection is provided by setting a data access restriction that prohibits other than transfer.

[Industrial application field]

The present invention relates to a memory protection method, and more particularly to a protection method for a common memory in a duplex system connected via a common memory.

[Conventional technology]

An example of a conventional duplex system having a common memory is shown in FIG.

The system shown in FIG. 3 constitutes a duplex system in which two systems, 0 system and 1 system, are connected via a common memory. For example, each system is operated in double parallel or The other system is in standby while the other system is operating, and even if one system fails during operation, the other normal system continues execution, avoiding a complete system down The reliability of is improved.

In the figure, 1 and 2 are CPUs, 3 and 4 are buses, 5 and 6 are main memories, 7 is common memory, 7a-0 and 7a-1 are common memory control adapters, and 8 and 9 are C
HUs (channel devices), 8a and 9a are I / O devices.

FIG. 4 exemplifies the configuration of the address space of the memory of each system of the redundant system. As shown, 0 system and 1
In each address space of the system, a main memory area and a common memory area are respectively allocated, and the CPU or CHU of each system can similarly access the respective main memory area and common memory area.

The 0-system common memory area and the 1-system common memory area physically exist on one common memory 7 having two ports.

This enables data transfer between the 0-system and the 1-system via the common memory 7.

Generally, the main memory is accessed by issuing a main memory reference instruction (READ / WRITE) for a small amount of data (referred to as a program mode), and is accessed by DMA for a large amount of data (DMA. Called mode).

Access to common memory is also possible in program mode and DM
Enabled with A mode.

In the program mode, the CPU in each system issues a main instruction reference instruction (READ / WRITE) to refer to the common memory. On the other hand, in the DMA mode, when the activation command is issued to the common memory or CHU in each system and the common memory is activated, the DMA control function of the common memory performs the DMA transfer between the common memory and the main memory. When the CHU is executed and the CHU is started, the CHU is connected between the common memory and the I / O device.
Execute DMA transfer. By the way, since the common memory is used as a relay means for delivering important data, such as being used for transfer of control information between systems in the case of a duplex system, some kind of protection is required. However, at present, the same memory protection method as the main memory is used,
Either it is not protected at all.

[Problems to be solved by the invention]

The main memory and the common memory are allocated to different address areas in the address space of each system of the duplicated system and are accessed using the same level of address.

Therefore, the common memory has the same memory protection method as the main memory,
For example, when the key protection method is applied, the amount of hardware increases considerably, and the burden on software also increases, resulting in higher costs.

On the other hand, common memory access rights are often provided to the user in their entirety, which is common in certain individual systems such as duplex systems. Therefore, rather than giving the OS a storage protection function for the common memory,
Providing in bare form without memory protection gives more flexibility in the development of individual systems, and from this perspective, it is desirable not to protect common memory.

Therefore, although there is a need to protect the common memory, there has been a problem that a conventional memory protection function has not been provided at a low cost and in an appropriate form.

[Means for solving problems]

In general, data transferred between systems is often particularly important data such as status information for synchronization in a redundant system, and since the amount of such data is relatively large, main memory-common memory. It is common to use DMA transfer between. The present invention is realized by a simple hardware circuit by limiting the memory protection in such a case.

Therefore, an area with storage protection and an area without storage protection are provided in the common memory, and for the area with storage protection, memory protection is performed by permitting only access by DMA transfer from the main memory. The function is provided by a hardware circuit regardless of the OS.

The principle of the present invention will be described with reference to FIG.

In FIG. 1, 11 is a main memory.

12 is a common memory.

12a is a protection area set in the common memory 12.

13 is a common memory control adapter, which has the functions of program mode control, main memory-common memory DMA control, and common memory storage protection.

Reference numeral 14 is a transfer circuit for address and write or read data.

Reference numeral 15 denotes a common memory storage protection circuit, which detects whether or not the access address is in the protection area 12a and whether or not the access is other than the main memory-common memory DMA, and both conditions are determined. When both are established, the transfer operation of the transfer circuit 14 is prohibited.

The CPU (not shown) can similarly request access to the main memory or the common memory in the program mode by using the main memory reference instruction.

[Action]

According to the configuration of the present invention shown in FIG. 1, the storage protection of the common memory 12 is performed only in the protected area 12a set in the common memory 12, and the main area is protected. All accesses other than the access by the memory-common memory DMA are prohibited, and free access is permitted in other areas.

Common memory storage protection circuit 15 of common memory control adapter 13
Determines whether or not the access address falls within the range of the protection area 12a by comparing with the protection area address. If the access address falls within the range of the protection area 12a, it determines that the common memory control adapter 13 It is prohibited except when the access is based on the DMA command between main memory and common memory.

That is, the access address from the CPU in the program mode is protected by the program runaway or bug.
If the inside of 12a is indicated, the transfer prohibition instruction signal is transmitted to the transfer circuit 1
4, the access address and data are blocked by the transfer circuit 14 and are not passed to the common memory 12. That is, access is prohibited.

Similarly, when the access address is in the protected area 12a and the access is in the DMA mode, unless it is a DMA transfer between the main memory and the common memory based on the command instruction from the CPU, The transfer circuit 14 blocks the access address and the data.

〔Example〕

 FIG. 2 shows the configuration of one embodiment of the present invention.

In FIG. 2, 10 is a main memory, 12 is a common memory, 12a is a protection area, 13 is a common memory control adapter, 14 is a transfer circuit, and 15
Is a common memory storage protection circuit, 16 is a command control circuit, 17 is
DMA control circuit, 18 is a program mode control circuit, 19 is a protection area detection circuit, 20 is an inverter, 21 and 22 are AND circuits, 23
Is an OR circuit, 24 is a CPU, and 25 is a bus.

The command control circuit 16 instructs the DMA control circuit 17 to perform main memory-common memory DMA transfer control in response to a DMA command instruction from the CPU 24 to the common memory control adapter 13. During command execution, the command execution signal (ON) is output.

The DMA control circuit 17 is a method normally used between the main memory 10 and the common memory 12 based on the start address and the data length of each data transfer area according to the command instruction given to the command control circuit 16. The bus 25 is exclusively used to execute DMA transfer control while continuously updating addresses. Also DMA
The DMA transfer in-progress signal (ON) is output during transfer control execution.

The program mode control circuit 18 is
The access operation of the common memory 12 by the CPU 24 is controlled.
During this operation, the transfer instruction signal (ON) is output.

Next, the operation of the common memory storage protection circuit 15 will be described. The protection area detection circuit 19 is a common memory supplied from the bus 25.
It is detected whether the access address to 12 is within the range of the protection area 12a, and when it is within the range, the area detection signal is sent.
Supply to AND circuits 21 and 22.

The other input of the AND circuit 21 is supplied with the transfer instruction signal output from the program mode control circuit 18 during the access operation of the common memory in the program mode, and when both inputs are ON, the transfer prohibition instruction is given. Generate a signal, O
It is applied to the transfer circuit 14 via the R circuit 23. At this time, the transfer circuit 14 blocks transfer of address and data between the bus 25 and the common memory 12.

The AND circuit 22 operates when the area detection signal is ON, the command control circuit 16 is not executing a command, and the command execution signal to be output is OFF, that is, when the output of the inverter 20 is ON and the DMA control circuit is ON. When the DMA transfer in progress signal output from 17 is on, a transfer prohibition instruction signal is generated and
It is applied to the transfer circuit 14 via the R circuit 23 to block transfer of address and data.

In this way, the AND circuit 21 makes no response to the request to access the protected area 12a of the common memory 12 in the program mode, and abnormally terminates the access instruction. The AND circuit 22 determines that the access request in the DMA mode is for the protected area 12a and
Between main memory and common memory based on command instructions from
If it is not a DMA transfer, there is no response to the access,
Abend the command.

〔The invention's effect〕

According to the present invention, the minimum required memory protection can be given to the common memory of the duplicated system by adding a very simple hardware circuit without depending on the OS, and the flexibility of software development is also sufficient. Held in.

The users of the redundant system having such a common memory generally have a fairly high technical level, and it is considered that there is a relatively low possibility that a structural error will occur in software development. It can function effectively even at various levels of memory protection.

[Brief description of drawings]

1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram of a conventional duplex system having a common memory, and FIG. 4 is a memory block diagram of the duplex system. Is. In Fig. 1, 10, 11: Main memory 12: Common memory 12a: Protected area 13: Common memory control adapter 14: Transfer circuit 15: Common memory storage protection circuit

Continuation of the front page (56) References JP-A-59-2297 (JP, A) JP-A-61-121146 (JP, A)

Claims (1)

[Claims] 1. A common memory (12) which is accessed by the same access means as that for the main memory (10, 11), and a common memory control adapter (13) for controlling access to the common memory (12). In the redundant system, a protection area (12a) is provided in the common memory (12), and access to the protection area (12a) is performed by the common memory (12) based on the DMA command instruction given to the common memory control adapter (13). Between main memory and main memory (10,11)
A common memory protection method characterized in that the memory protection control is performed by a hardware circuit in the common memory control adapter (13) so that only the one by MA transfer is permitted.