JPS63165951A - Common memory protecting system - Google Patents

Abstract

PURPOSE:To simplify the structure of a protecting circuit by securing the minimum necessary protection of storage for a common memory of a duplex system with addition of a hardware circuit and with no dependence on an OS. CONSTITUTION:The protection of storage covers an entire area of a common memory 12. A common memory storage protecting circuit 15 of a common memory control adaptor 13 decides whether an access address covers or not the range of a protecting area 12a via the comparison with the address of the area 12a. If so, the accesses are totally inhibited excluding an access given by a DMA command produced between a main memory and the memory 12 against the adaptor 13.

Description

[Detailed Description of the Invention] [Summary] With respect to a common memory that can be accessed by multiple processors using the same access instructions as those for their own main memory, DMA transfer data access restrictions are set between the main memory and the common memory. , performs easy memory protection.

[Industrial application field]

The present invention relates to a memory protection method.

In particular, we will focus on protection schemes for common memory in duplex systems connected via common memory.

[Conventional technology]

An example of a conventional duplex system having a common memory is shown in FIG.

The system in Figure 3 has two systems, the O system and the 1 system.
It constitutes a duplex system connected via a common memory, and for example, each unit may be operated in double parallel mode, or one system may be in operation while the other system is on standby.
Even if a failure occurs in one system during operation, the other normal system continues to operate, thereby avoiding a complete system failure and increasing the reliability of the system.

In the figure, 1.2 is a CPU, 3.4 is a bus, 5.6 is a main memory, 7 is a common memory, 8.9 is a CHU (channel unit), and 8a and 9a are I10 devices.

FIG. 4 shows an example of the structure of the address space of each group of memory in the duplex system.As shown in FIG. 0, each address space of the O system and the 1 system.

A main memory 'pMMU' and a common memory 'pMM are respectively allocated, and each group's CPU or C) (U is.

Each main memory area and the common memory area can be accessed in the same way.

The θ-system common memory area and the 1-system common memory area physically exist on one common memory 7 having two ports.

This allows data transfer between the O system and the 1 system via the common memory 7.

Generally, access to main memory is performed using a main memory reference instruction (READ/WT?ITE) for a small amount of data.
) (called program mode), and in the case of a large amount of data, it is done by DMA (DMA
mode).

Access to common memory is also available in program mode and D.
This is enabled with MA mode.

In the program mode, the CPU in each base issues a main instruction reference instruction (READ/WRITE) to refer to the common memory. On the other hand.

In DMA mode, each unit issues a startup command to the common memory or CHU, and when the common memory is started, the DMA1+lJ control function of the common memory executes DMA transfer between the common memory and main memory. , also CHU
, the CHU performs a DMA transfer between the common memory and the I10 device. By the way, in the case of a duplex system, for example, the common memory is used as a relay means for transferring important data such as control information between systems, and therefore requires some kind of protection. However, currently, either the same storage protection method as main memory is used, or there is no protection at all.

[Problem that the invention seeks to solve]

The main memory and the common memory are allocated to different address areas within the address space of each group of the duplex system, and are accessed using addresses at the same level.

Therefore, common memory uses the same memory protection method as main memory.
For example, if you apply a key protection scheme.

The disadvantage was that the increase in the amount of hardware was quite large, and the burden on the software became heavy, leading to an increase in costs.

On the other hand, the common memory access tower is often provided entirely to users, which is often seen in certain individual systems such as duplex systems. Therefore, rather than providing O8 with a memory protection function for common memory,
Providing it in a bare form without memory protection provides more flexibility in the development of an individual system, and from that perspective, it is desirable not to protect the common memory.

For this reason, although there is a need to protect the common memory, there has been a problem in the past that it has not been possible to provide a low-cost and appropriate memory protection function.

[Means for solving problems]

Generally, the data transferred between systems is often particularly important data, such as state information for synchronization in a duplex system, and because the amount of data is relatively large, it is transferred between main memory and common memory. Usually, DMA transfer is used.

The present invention realizes memory protection in such a case with a simple hardware circuit by limiting the memory protection.

For this reason, common memory is provided with areas with memory protection and areas without memory protection, and memory protection is applied to areas with memory protection that only allows access by DMA transfer from the main memory. The functions are provided by hardware circuitry rather than by O8.

The basic structure of the present invention will be explained with reference to FIG.

In FIG.

11 is a main memory.

12 is a common memory.

12a is a protected area set within the common memory 12.

Reference numeral 13 denotes a common memory control adapter, which has functions of program mode control, DMA control between main memory and common memory, and common memory storage protection.

14 is an address and write or read data transfer circuit.

Reference numeral 15 denotes a common memory storage protection circuit, which detects whether the access address is within the protected area 12a and whether the access is by a method other than DMA between the main memory and the common memory. If it is established,
The transfer operation of the transfer circuit 14 is prohibited.

A CPU (not shown) can similarly request access to the main memory or common memory using a main memory reference instruction in the program mode.

[Effect]

According to the configuration of the invention shown in FIG.

Storage protection of the common memory 12 covers the entire common memory 12. 1! set on the common memory 12! Area 1
2a, all access to that area other than access by DMA between main memory and common memory is prohibited, and free access to that area is permitted.

The common memory storage protection circuit 15 of the common memory control adapter 13 determines whether the access address falls within the range of the protected area 12a by comparing it with the protected area address, and if the access address falls within the range of the protected area 12a. When accessing the common memory control adapter 13, access to the common memory control adapter 13 is prohibited unless the access is based on a DMA command between main memory and common memory.

In other words, ■ If the access address from the CPU in the program mode points inside the protected area 12a due to a program runaway or a bug, a transfer prohibition instruction signal is sent to the transfer circuit 14, and the access address and data are transferred to the transfer circuit 14. The data is blocked and is not passed to the common memory 12.

In other words, access is prohibited.

■Similarly, even if the access address enters the protected WIM area 12a, if the access is in DMA mode, unless it is a DMA transfer by the common memory control adapter itself, for example, a DMA transfer by the CHU. case.

The access address and data are blocked by the transfer circuit 14.

〔Example〕

FIG. 2 shows the configuration of one embodiment of the present invention.

In FIG. 2, 10 is a main memory, 12 is a common memory,
12a is a protection area, 13 is a common memory control adapter, 1
4 is a transfer circuit, 15 is a common memory protection circuit, 16 is a command control circuit, 17 is a DMA control circuit, 18 is a program mode control circuit, 19 is a protection area detection circuit, 20
is an inverter.

21 and 22 are AND circuits, and 23 is an OR circuit.

24 is a CPU, and 25 is a bus.

The command control circuit 16 responds to a DMA command instruction from the CPU 24.

The main memory common memo IJDMA transfer control is instructed to the DMA control circuit 17. Also while running the command.

Outputs command execution signal (on).

The DMA control circuit 17 has a main memory 10 and a common memory 12.
based on the start address and data length of each data transfer area according to command instructions.

The bus 25 is exclusively occupied in a commonly used manner, and DMA transfer control is executed while continuously updating addresses. Also DM
While the A transfer control is being executed, a DMA transfer in progress signal (ON) is output.

The program mode control circuit 18 controls the access operation of the common memory 12 by the CPU 24 during the program mode. Also, during this operation, a transfer instruction signal (ON) is output.

Next, the operation of the common memory storage protection circuit 15 will be explained.

The protected area detection circuit 19 detects that the access address to the common memory 12 supplied from the bus 25 is protected 21! It is detected whether or not it is within the range of the T and M regions 12a, and when it is within the range, a region detection signal is supplied to AND circuits 21 and 22.

The other input of the AND circuit 21 is supplied with a transfer instruction signal output from the program mode control circuit 18 during execution of a common memory access operation in the program mode, and when both inputs are on, a transfer prohibition instruction is issued. A signal is generated and applied to the transfer circuit 14 via the OR circuit 23.

At this time, transfer circuit 14 prevents address and data transfer between bus 25 and common memory 12.

The AND circuit 22 operates when the above area detection signal is on, the command control circuit 16 is not executing a command, and the output command execution signal is off.

That is, when the output of the inverter 20 is on and DM
When the DMA transfer in progress signal output from the A control circuit 17 is on, a transfer prohibition instruction signal is generated and applied to the transfer circuit 14 via the OR circuit 23.

Prevent address and data transfer.

In this way, the AND circuit 21 does not respond to a request to access the protected area 12a of the common memory 12 in the program mode.

The access command is terminated abnormally. Also, AND circuit 2
2 is an access request in DMA mode.

In the case where the protection area 12a is executed and the common memory control adapter 13 is not the main execution entity, for example, when the CHU is executed between the common memory 12 and the I10 device.

There will be no response to that access, and the command will terminate abnormally.

〔Effect of the invention〕

According to the present invention, it is possible to provide the necessary minimum memory protection to the common memory of a duplex system by adding a simple hardware circuit without relying on O8,
Also, sufficient flexibility in software development is maintained.

Users of such duplex systems equipped with common memory generally have a fairly advanced level of technology, and it is thought that the possibility of structural errors occurring in software development is relatively small. It can function effectively even at low levels of memory protection.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the basic configuration of the present invention, Figure 2 is a diagram showing the configuration of an embodiment of the present invention, Figure 3 is a diagram showing the configuration of a conventional duplex system having a common memory, and Figure 4 is a diagram showing the memory configuration in the duplex system. It is. In Figure 1. to, tts Main memory 12: Common memory 12a: Keep! 1 area 13: Common memory control adapter 14 + transfer circuit 15: Common memory storage protection circuit Patent applicant Panafacom Co., Ltd. (1 other person) Representative patent attorney Hase Yo Fumi Hiroshi (1 other person) Honshan Mei Q Principle sideways 1st area

Claims (1)

[Claims] In a redundant system having a common memory (12) that is accessed by the same access means as the main memory (10, 11), the common memory (12) includes the main memory (10, 11) and the main memory (10, 11). A protected area that only allows access via DMA transfer between
12a), and memory protection control is performed by a hardware circuit.