JPH0337750A - Function device peripheral of processor - Google Patents

Abstract

PURPOSE:To eliminate the need of providing a decoder on the outside by providing a means for deciding a permission or an inhibition of an access, based on a level signal. CONSTITUTION:A processor 10 inputs an address signal ADD for designating a control register 32 to an address decoder 34, and inputs a level signal for showing the level of a program to be executed to an access level comparator 33. The access level comparator 33 compares the access permission level written in an access level storage register 31 and a level signal LEV, and outputs its result to an address decoder 34. In the case of the level signal LEV exceeds the access permission level, an effective decoding result is inputted to a buffer 36, and it is permitted to supply and receive a data signal DATA to and from the processor 10. In such a way, the access level can be decided, and it is unnecessary to provide a decoder on the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a processor peripheral function device incorporated in a processor system that performs level-based memory protection.

[Conventional technology]

With the development of processor systems, various measures have been taken to protect the system from erroneous operations or erroneous programs, one of which is memory protection using levels. This makes the system management program a higher level program than the application program, and prohibits the application program from accessing the memory area used by the system management program. That is, the processor generates a level signal corresponding to the level of the program being executed, while the memory device has a write level or read level set (defined) for each memory area, and the level signal matches the level. This method allows reading and writing of data in the corresponding area only when the area is open.

Furthermore, even in the case of a system in which a processor peripheral function device is incorporated, level-based management can be performed to prevent erroneous operations of application programs or malfunctions due to erroneous programs.

FIG. 4 is a block diagram of a processor system incorporating a processor peripheral function device 30 that operates according to bus control, such as an interrupt controller and a serial transfer controller. Processor IO is connected to address bus 50. Data bus 51. It is connected to the memory device 20 via a level signal line 52. Further, an address signal ^DD and a level signal LEV are inputted from the processor 10 to a decoder 53 via an address bus 50 and a level signal line 52, and the decoding result of the decoder 53 and a data signal output from the processor 10 via a data bus 51 are inputted. DAT
A is input to the peripheral function device 30.

In the processor system configured as described above, the processor 10 has an address bus 50 and a level signal line 52.
When the address signal ADD and the level signal LEV are outputted to the memory device 20, these signals are input manually to the memory device 20. Memory unit W
20 is divided into a plurality of memory areas, and each memory area has a defined level. When the level of the program being executed is higher than the level of the memory area to be accessed, the data signal DAT is transferred between the processor IO and the memory device 20 via the data bus 51.

Further, when the processor 10 accesses the peripheral function device 30, the processor 10 uses an address signal ADD specifying the peripheral function device 30 and a level signal L corresponding thereto.
The EV is output to the decoder 53. In response to this, the decoder 53 outputs a signal to the peripheral function device 30 to permit access from the processor 10 to the peripheral function device 30 . Then, data signals are exchanged between the processor 10 and the peripheral function device 30.

The above is an example in which the peripheral function device 30 is used as a hash slave that is subordinate to hash control, but there are also peripheral function devices that perform bus control and access memory devices, such as the IIMA controller.

FIG. 5 is a block diagram of a processor system in which a peripheral function device 40 is incorporated as a bus mask for controlling a bus. The processor 10 has an address bus 50, a data bus 51 . It is connected to the memory device 20 via a level signal line 52. Further, a bus request signal REQ from the peripheral function device 40 is inputted to the processor 10, and the processor 10
There is a configuration in which the bus right permission signal CRT is output to the peripheral function device 40 and the level signal generation circuit 54, and a configuration in which the bus right permission signal CRT is not output. The peripheral function device 40 has an address bus 50 . The level signal generation circuit 5 is connected to the memory device 20 via the data bus 51.
4 is connected to the memory device 20 via a level signal line 52.

In the processor system configured as described above, when it becomes necessary for the peripheral function device 40 to access the memory device 20, the peripheral function device 40 sends a bus request signal REQ, which is the right to control the bus to the processor.
outputs. When processor IO does not need to use the bus, processor 10 outputs bus permission signal CRT to peripheral function device 40 and level signal generation circuit 54. Peripheral function device 40 authorized to control the bus
is an address signal ^ in order to access the memory device 20.
DO is output to the memory device 20 via the address bus 50, and the level signal generating circuit 54 outputs a level signal LIEV at a preset level to the memory device 20 via the level signal line 52. When the level of the level signal line 52 is equal to or higher than the level of the memory area designated by the address signal ^DD, access is permitted and data is transferred between the peripheral function device 40 and the memory device 20 via the data bus 51. A data signal DATA is exchanged.

[Problem to be solved by the invention]

The peripheral function device 30 shown in FIG. 4 does not have a level determination function. Furthermore, the peripheral function device 40 shown in FIG. 5 does not have a level signal generation function. Therefore, when these are incorporated into a processor system that performs level-based memory protection, it is necessary to provide a decoder 53 that determines the access level and a level signal generation circuit 54 that generates the level signal LIEV, which causes the problem that the circuit becomes complicated. be. Furthermore, since the levels in these circuits are set in advance, there is a problem in that the levels cannot be easily changed.

The present invention has been made to solve such problems, and the first invention aims to provide a processor peripheral function device that can determine an access level, and the second invention aims to provide a processor peripheral function device that can output a level signal. The purpose is to provide equipment.

[Means to solve the problem]

The processor peripheral function device of the first invention includes means for determining a level signal generated by the processor.

A processor peripheral function device according to a second aspect of the invention includes means for generating a level signal for accessing a memory whose level is defined.

[Effect]

In the processor system incorporating the processor peripheral function device of the first invention, the processor sets a level at which the processor peripheral function device can be accessed by the processor. When a processor accesses a processor peripheral function device, it permits access if it determines that the level signal output from the processor is equal to or higher than the access level.

In the processor system incorporating the processor peripheral function device of the second invention, a level signal is generated when the processor peripheral function device attempts to access the memory. If the level signal matches the level of the memory area to be accessed, access is permitted.

[Example] Hereinafter, the present invention will be described based on drawings showing one example thereof.

FIG. 1 is a block diagram of a processor system incorporating a processor peripheral function device 30 of the first invention. Processor 10 and memory device 20 are connected to address bus 50 .
Data bus 51. It is connected via Level iM No. 14%52 and operates in the same way as before.

The processor 10 also has an address bus 50. Data bus 51. It is connected to the peripheral function device 30 via a level signal line 52. The peripheral function device 30 has an access level storage register 31 in which the access level is written; an access register comparison that reads the register written in the access register storage register 31 and compares this with the register signal LEV outputted by the processor 10; Vessel 3
3. An address decoder 34 that manually compares the comparison result of the access register comparator 33 and the address signal ^DD output by the processor 10, and when the level signal LEV is equal to or higher than the level written in the access level storage register 31. It includes a control register 32 that exchanges a data signal DATA with the processor 10. The access permission level for the peripheral function device 30 is written into the access level storage register 31 at any time. This writing is
This is performed when the address signal ADD specifying the access level storage register 31 and the level signal LEV of the privilege level having the highest priority are inputted from the processor 10 to the buffer 35 via the address bus 50 and the level signal line 52. , write data DATA representing the access permission level is input manually via the data bus 51.

When the level of the address to be accessed is higher than the input level signal LEV, a valid decoding result is manually input from the address decoder 34 to the buffer 36, and data transfer from the processor 10 to the control register 32 via the data bus 51 is permitted. be done.

The operation of accessing the peripheral function device 30 or the control register 32 configured as described above is performed as follows.

The processor 10 inputs an address signal ADD specifying the control register 32 to the address decoder 34, and inputs a level signal LEV representing the level of the program to be executed to the access level comparator 33. The access level comparator 33 compares the access permission level written in the access level storage register 31 with the level signal LEν, and outputs the result to the address decoder 34.

When the level signal LEV is equal to or higher than the access permission level, a valid decoding result is input to the buffer 36, and data signal DATA is permitted to be exchanged with the processor 10.

Next, the processor peripheral function device 40a of the second invention will be explained based on FIG.

The processor 10 and the memory device 20 are connected to an address bus 5.
0. Data bus 51. It is connected via a level signal line 52 and operates in the same manner as the conventional one. Also, memory device 2
0 is the address bus 50. A data bus 51 is connected to the peripheral function device 40a via a level signal line 52.

The processor peripheral function device 40a operates as a bus mask that performs bus control.

The IδH22 function device 40a is provided with an operation level register 41 in which a level is set when the IδH22 function device operates as a bus mask, and when a level is set here, the IδH22 function device 40a is configured to operate as a bus mask, thereby causing the processor 10 to use the bus. A bus right request signal REΩ is output to request the bus right, and a bus right grant signal CR is outputted to permit use of the bus from the processor 10.
There is no need for T to be done manually. Peripheral function device 40a
Is the bus right permission signal GI? When T is input, the level of the level signal output when it operates as a bus mask is written into the operation level register 41. This writing is performed by inputting data DATA via data bus 5I when address signal ADD specifying operation level register 41 is input to buffer 46.

Next, the operation will be explained.

The level at which the peripheral function device 40a operates as a bus mask is determined by the processor 10 in the operating level register 4.
Written to 1. When the peripheral function device 40a needs to access the memory device 20 in such a state, the peripheral function device 40a outputs the bus request signal REQ. Upon receiving this, the processor 10 outputs a bus right permission signal CRT when there is no need to use the bus. The peripheral function device 40a to which the bus right has been granted is the memory device 2
0 from the operation level register 41 to access the level signal line 52, and an address signal ADD from an address generation circuit (not shown) to the level signal line 52. It is output to the memory device 20 via the address bus 50. In the memory device 20, when the manually input level signal LEV is equal to or higher than the level defined in the accessed memory area, the peripheral function device 40
A data signal DATA is exchanged via the data bus 51 and the data bus 51.

Another embodiment of the second invention is shown in FIG.

The processor peripheral function device 40b of this embodiment has an operation level register 41. to which a level is set when operating as a bus mask. An access level storage register 43 in which a register serving as a criterion for register rewriting to the operation level register 41 is set; an address decoder 42 for the access level storage register 43 and an address decoder 44 for the operation level register 41 are provided. . Address decoder 42 outputs a valid decoding result to buffer 45 only when manually inputted level signal CHEv is at a privileged level when inputted from processor 10 is an address signal ADD specifying access level storage register 43. When a valid decoding result is input to the buffer 45, the level set in the access level storage register 43 is input from the processor 1o to the access level storage register 43 via the data bus 51. The address decoder 44 inputs an address signal ADD specifying the operation level register 41 and a level signal LEV from the processor 10, and inputs the level set in the access level storage register 43, and from this level inputs the level signal LEVO. A valid decoding result is output to the buffer 46 when the decoding result is higher. When a valid decoding result is input to the buffer 46, the level of the level signal line 52 is written to the operation level register 41. The peripheral function device 40b configured as described above has an address bus 50. Data bus 51. It is connected to the memory device 20 via a register signal line 52.

Next, the operation will be explained.

The level at which the peripheral function device 40b operates as a lotus mask and the reference level used as a determination for rewriting the level are written in advance in the operation level register 41 and the access level storage register 43 by the processor 10. In such a state, when the peripheral function device 40b needs to access the memory device 20, the peripheral function device 40b outputs a bus request signal REQ. Upon receiving this, processor 10 outputs a hash right permission signal CRT when there is no need to use the bus. The peripheral function device 40b to which the bus right has been granted receives a level signal LEV indicating the level set there from the operation level register 41 in order to access the memory device 20, and an address signal ADD from an address generation circuit (not shown). line 5
2. It is output to the memory device 20 via the address bus 50. Level signal LE manually input in memory device 20
If V is equal to or higher than the level defined in the accessed memory area, the peripheral function bag g4ob and the data bus 51
A data signal DATA is exchanged via the terminal.

When rewriting the level of the level signal LEV output by the operation level register 41 in response to a change in the operation mode,
An address signal ADD specifying the operating level register 41 and a level signal LEV indicating the level to be rewritten are manually inputted from the processor 10 to the address decoder 44. Then, the address decoder 44 manually inputs the level set in the access level storage register 43, and outputs a valid decoding result to the buffer 46 if the level to be rewritten is higher than the level. Then, the level to be rewritten is manually written into the operation level register 41 via the level signal line 52.

Furthermore, when rewriting the reference level set in the access level storage register 43 in accordance with a change in the operation mode, the access level storage register 4 is rewritten from the processor 10.
An address signal ADD specifying number 3 and a level signal LEV indicating a privilege level are manually input to the address decoder 42.

Then, the address decoder 42 outputs a valid decoding result to the buffer 45. When a valid decoding result is input to the buffer 45, the data of the level to be rewritten is manually written into the access level storage register 43 via the data bus 5I.

〔Effect of the invention〕

As explained above, the processor peripheral function device of the first invention includes means for determining a level signal inside the device, so there is no need to provide an external decoder, and the circuit does not become complicated.

Since the processor peripheral function device of the second invention includes means for generating a level signal inside the device, there is no need to provide an external level signal line 52, and the circuit does not become complicated.

Furthermore, when the processor peripheral function device of the present invention is incorporated into a processor system that performs level-based memory protection,
Since the access operation is performed without using an external device, there is an advantage that the level can be set and changed at any time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a processor system that performs memory protection 4 according to the level when it is equipped with the processor peripheral function device according to the first invention, and FIG. 2 is the level when it is equipped with the processor peripheral function device according to the second invention. FIG. 3 is a block diagram illustrating a digital processor system that performs memory protection according to levels according to another embodiment of the second invention, and FIG. FIG. 4 is a block diagram showing a system including a conventional processor peripheral function device, and FIG. 5 is a block diagram showing a system including a conventional processor peripheral function device capable of acting as a bus master. 30, 40.40a, 40b...Processor peripheral function device 10...Processor 41...Operation level register 3L 43...Access level storage register Note that in the figures, the same reference numerals indicate the same or equivalent parts. .

Claims (2)

[Claims] (1) When the level signal that specifies the level that defines the priority of access matches that level, in the processor peripheral function device that allows access by the processor that outputs it, based on the level signal. A processor peripheral function device comprising means for determining permission or prohibition of access. (2) In a processor peripheral function device that can access a memory that has an area defined with a level indicating the priority of access, if access to the memory is permitted, a level that specifies the level to access the memory. A processor peripheral function device comprising means for generating a signal.