JP2000304801A - Electronic part reliability evaluation device and electronic part reliability evaluation method - Google Patents

Electronic part reliability evaluation device and electronic part reliability evaluation method

Info

Publication number
JP2000304801A
JP2000304801A JP11114564A JP11456499A JP2000304801A JP 2000304801 A JP2000304801 A JP 2000304801A JP 11114564 A JP11114564 A JP 11114564A JP 11456499 A JP11456499 A JP 11456499A JP 2000304801 A JP2000304801 A JP 2000304801A
Authority
JP
Japan
Prior art keywords
terminals
resistance
electronic component
voltage
insulation resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11114564A
Other languages
Japanese (ja)
Inventor
Tomohisa Motomura
知久 本村
Yoshitaka Fukuoka
義孝 福岡
Kimiaki Hoizumi
公昭 保泉
Kenji Sasaoka
賢司 笹岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11114564A priority Critical patent/JP2000304801A/en
Publication of JP2000304801A publication Critical patent/JP2000304801A/en
Pending legal-status Critical Current

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To detect a defect without feeding excessively high current and confirm the defect in an early stage by providing a load resistor between a terminal of an electronic part with insulation resistance to be measured and a power source and measuring a voltage between both terminals of the load resistor. SOLUTION: A reliability evaluation testing device evaluating a terminal insulation resistance for a printed circuit board 2 and the like is provided with a load resistor 5 connected to a power source 1 and the circuit board 2 in series and a voltmeter 6 connected in parallel between both terminals of the resistor 5. A predetermined voltage is applied between terminals 2C, 2D from the power source 1, and a voltage always monitored by the voltmeter 6 is recorded by a pen recorder 7, for example. A defect such as a short circuit is detected when a voltage between both terminals 2C, 2D is increased. As the insulation resistance of an evaluated object such as the circuit board 2, an insulation resistance of about 100 KΩ is necessary, and an insulation resistance of about 1000 KΩ is desirable. When a resistance value of the resistor 5 is 1/1000 or less to a minimum value of the insulation resistance, measurement can be facilitated.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は電子部品用信頼性評
価装置及びプリント配線板の信頼性評価方法に関するも
のであり、特に多層配線を用いたプリント配線板の信頼
性評価方法及びそのための信頼性評価装置に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reliability evaluation apparatus for an electronic component and a reliability evaluation method for a printed wiring board, and more particularly to a reliability evaluation method for a printed wiring board using multilayer wiring and the reliability therefor. It relates to an evaluation device.

【0002】[0002]

【従来の技術】近年、半導体装置の高集積化、高機能化
が進み、半導体装置の寸法に比して多数の接続端子が必
要とされるようになっている。一方、半導体装置を実装
使用する電子機器においては急速に機器の小型化が進
み、使用する半導体装置、電子部品の小型化が要求され
ている。
2. Description of the Related Art In recent years, semiconductor devices have become highly integrated and sophisticated, and a large number of connection terminals are required in comparison with the dimensions of the semiconductor device. On the other hand, in electronic devices mounted with a semiconductor device, miniaturization of the device is rapidly progressing, and miniaturization of a semiconductor device and electronic components to be used is required.

【0003】これらの事情を背景にして、半導体装置等
の実装に用いるプリント配線板においても配線密度の高
密度化が、また、多層配線を用いたプリント配線板では
層間絶縁層の薄層化が進展している。また、携帯電話な
どの電子機器の急速な普及に伴い機器の低価格化が急速
に進んでおり、プリント配線板に対しても小型化要求と
ともに低価格化要求も大きい。更に携帯電話などの市場
では、製品規格の変更は極めて頻繁である。このような
技術、需要動向に伴い、プリント配線板を高密度化、薄
層化した際の長期信頼性の確保を短時間に確認すること
が重要になっている。即ち大幅なコストアップ無しに、
簡易に、かつ、迅速にプリント配線板の良否を判別する
評価方法が求められている。
[0003] Under these circumstances, printed wiring boards used for mounting semiconductor devices and the like are required to have higher wiring densities, and printed wiring boards using multilayer wiring are required to have thinner interlayer insulating layers. Evolving. Also, with the rapid spread of electronic devices such as mobile phones, price reduction of devices is rapidly progressing, and there is a great demand for smaller and lower price printed wiring boards. Further, in markets such as mobile phones, changes in product standards are extremely frequent. With such technology and demand trends, it has become important to confirm in a short time how long-term reliability is secured when a printed wiring board is densified and thinned. That is, without significant cost increase,
There is a need for an evaluation method for easily and quickly determining the quality of a printed wiring board.

【0004】これらの要求にこたえるために従来から一
定形状の信頼性評価パターンを標準として用いて、絶縁
された配線間に電圧を引加して絶縁抵抗の減少を測定す
ることによりプリント配線板の信頼性を確認する評価試
験が実施されてきた。
In order to meet these requirements, a printed circuit board is manufactured by applying a voltage between insulated wires and measuring a decrease in insulation resistance by using a reliability evaluation pattern of a fixed shape as a standard. Evaluation tests have been conducted to confirm reliability.

【0005】以下に図5を用いて従来のプリント配線板
の評価方法について説明する。図5(A)は、電源1に
評価用のプリント配線板2を接続した時の概略図であ
り、図5(B)は絶縁抵抗計4にプリント配線板2を接
続した時の概略図である。図5(A)、図5(B)にそ
の表面概略図を示したように、評価用に作成されたプリ
ント配線板2は、その最外表面に互いに一定距離離間し
て櫛の歯状に配線部が形成され、その一端で全配線部が
集束しているテストパターン2Aと、そのテストパター
ン2Aの隣接する櫛の歯状配線部間の各々の中央部に、
同様の櫛の歯状の配線部が位置するようにテストパター
ン2Aとほぼ同一形状に形成されたテストパターン2B
とが形成されている。テストパターン2A,2Bはそれ
ぞれ全配線部が集束した端子部2C,2Dを有し、この
部分で外部と電気的に接続可能とされている。
A conventional method for evaluating a printed wiring board will be described below with reference to FIG. FIG. 5A is a schematic diagram when the printed wiring board 2 for evaluation is connected to the power supply 1, and FIG. 5B is a schematic diagram when the printed wiring board 2 is connected to the insulation resistance meter 4. is there. As shown in the schematic surface views of FIGS. 5A and 5B, the printed wiring board 2 prepared for evaluation is spaced apart from the outermost surface by a certain distance to form a comb-like shape. A test pattern 2A in which a wiring portion is formed and all the wiring portions are converged at one end thereof, and a central portion between the adjacent comb tooth-shaped wiring portions of the test pattern 2A,
A test pattern 2B formed in substantially the same shape as the test pattern 2A so that a similar comb tooth-shaped wiring portion is located.
Are formed. The test patterns 2A and 2B have terminal portions 2C and 2D, respectively, in which all wiring portions are converged, and these portions can be electrically connected to the outside.

【0006】テストパターン2A,2Bの各端子部2
C,2Dはそれぞれ電源1の+電極,−電極に接続され
ている。この状態で、電源1により端子部2C,2D間
にプリント配線板の使用電圧を一定時間印加する(例え
ば85℃、85%の高温高湿雰囲気で、5.5Vを10
00時間引加する)。尚、テストパターン2A,2B間
でショートが発生した場合に過大電流が流れるのを防ぐ
ために、電源1は電流リミッタが設定され、0.01A
以上の電流が流れないようになっている。
Each terminal 2 of test patterns 2A and 2B
C and 2D are connected to the + and-electrodes of the power supply 1, respectively. In this state, the power supply 1 applies a working voltage of the printed wiring board between the terminal portions 2C and 2D for a certain period of time (for example, by applying 5.5 V to a high-temperature and high-humidity atmosphere of 85 ° C. and 85% for 10 V).
00 hours). Incidentally, in order to prevent an excessive current from flowing when a short circuit occurs between the test patterns 2A and 2B, a current limiter is set for the power supply 1 and the current limiter is set to 0.01 A.
The above current is prevented from flowing.

【0007】その後、1000時間経過後に、図5
(B)に図示したように電源1に替えて絶縁抵抗計4を
端子部2C,2D間に接続し、5V乃至50Vの電圧を
60秒程度引加してこの間の絶縁抵抗を測定し、電圧印
加前の抵抗値と比較することにより、その変動の大小か
らプリント配線板の良否を判断することができる。ま
た、1000時間引加するばあいでも、100時間、5
00時間程度の経過時の途中段階でも同様に特性測定を
行い早期に不良を確認することも出来る。
After 1000 hours, FIG.
As shown in (B), instead of the power supply 1, an insulation resistance meter 4 is connected between the terminals 2C and 2D, a voltage of 5 V to 50 V is applied for about 60 seconds, and the insulation resistance during this period is measured. By comparing with the resistance value before application, the quality of the printed wiring board can be determined from the magnitude of the change. In addition, even if 1000 hours is added, 100 hours, 5 hours
Even in the middle stage after the lapse of about 00 hours, the characteristics can be measured in the same manner and the defect can be confirmed at an early stage.

【0008】このような方法を用いることにより、隣接
するテストパターン間の耐圧が不充分の場合には電圧印
加中に隣接するテストパターン2A,2B間のもっとも
耐圧が低いところでショートが生じ、図5(B)に示し
た測定時に端子部2C,2D間の抵抗値が大幅に低下す
ることにより、プリント配線板の不良を確認することが
できる。また、大幅な変動が無い場合でも、通常絶縁抵
抗は電圧引加により低下するので、絶縁抵抗値の下限を
設けて、それ以下のものは不良とする措置を取ることも
出来る。
By using such a method, if the withstand voltage between adjacent test patterns is insufficient, a short circuit occurs between the adjacent test patterns 2A and 2B at the lowest withstand voltage during voltage application, and FIG. When the resistance value between the terminal portions 2C and 2D is significantly reduced at the time of the measurement shown in (B), a defect of the printed wiring board can be confirmed. In addition, even if there is no significant fluctuation, the insulation resistance usually decreases due to the application of a voltage. Therefore, it is possible to set a lower limit of the insulation resistance value and take measures to determine that the insulation resistance value is lower than the lower limit.

【0009】[0009]

【発明が解決しようとする課題】しかしながら上記の評
価方法には次のような問題があった。即ち、従来のプリ
ント配線板の評価方法では、製品規格に対して十分に余
裕を持った評価を行うには、評価時間は1000時間程
度必要である。途中段階で不良が発生した場合には10
0時間、500時間程度の決められた時間で測定して不
良を検出できるが、その評価時間の間は不良発生を確認
する手段が無かった。更に評価回数を増加することは、
測定に要する作業時間を考慮すると現実的ではなかっ
た。このため、プリント配線板の設計変更着手が遅れ、
改良品の試作が遅れていた。このような試作評価の遅延
は製品寿命の短い携帯端末市場などでは製品展開上の致
命傷に成りかねなかった。
However, the above evaluation method has the following problems. That is, in the conventional method for evaluating a printed wiring board, an evaluation time of about 1000 hours is required to perform an evaluation with a sufficient margin with respect to a product standard. 10 if a defect occurs in the middle stage
A defect can be detected by measuring at a predetermined time of about 0 hour or 500 hours, but there is no means for confirming the occurrence of the defect during the evaluation time. Increasing the number of evaluations further
It was not realistic considering the working time required for the measurement. For this reason, the design change of the printed wiring board is delayed,
Prototyping of the improved product was delayed. Such a delay in prototype evaluation could be a fatal injury in product development in the market for mobile terminals with a short product life.

【0010】また、ショート不良の発生箇所は、図4に
概略表面図(拡大図)を示すように、不良発生部の隣接
配線間で広い幅にわたって黒く焦げている黒変部11B
がある場合が多く、不良発生部位の特定、不良原因の推
定が困難な場合が多かった。また、複数の不良発生箇所
にわたって黒く焦げてしまい、不良発生場所の数がわか
らなくなっている場合があった。更にひどい場合には、
プリント配線板が燃えてしまうことがあった。
Further, as shown in a schematic surface view (enlarged view) of FIG. 4, a short-circuit defect is generated at a black discolored portion 11B which is scorched black over a wide width between wirings adjacent to the defective portion.
In many cases, it was difficult to identify the location where the failure occurred and to estimate the cause of the failure. Further, there is a case where a plurality of defective locations are scorched black and the number of defective locations is unknown. In the worse case,
The printed wiring board sometimes burned.

【0011】また、このような不良が発生したプリント
配線板では、図5(B)に示した方法で抵抗を測定する
際に、5V乃至50Vの測定定格の電圧を引加すると、
その電圧で最大0.3A程度の大電流が流れ、それによ
り測定抵抗値がばらついたり、黒い焦げが広がって不良
発生部位の特定、不良原因の推定が更に困難になるなど
の不都合があった。
In a printed wiring board in which such a defect has occurred, when a voltage having a measurement rating of 5 V to 50 V is applied when measuring the resistance by the method shown in FIG.
At this voltage, a large current of about 0.3 A at the maximum flows, causing variations in the measured resistance value, and the spread of black scorch, which makes it more difficult to identify the location of the failure and to estimate the cause of the failure.

【0012】[0012]

【課題を解決するための手段】本発明に記載の電子部品
用信頼性評価装置及び電子部品の信頼性評価方法は上記
の問題を解決するためになされたものであり、下記の特
徴を有する。本発明に記載の電子部品用信頼性評価装置
は、電子部品の端子間絶縁抵抗を評価する電子部品用信
頼性評価装置であって、絶縁抵抗を測定するべき前記電
子部品の端子に接続してその端子間に電圧を引加し得る
電源と、前記電源と前記電子部品間に接続された負荷抵
抗と、前記負荷抵抗の両端子間の電圧を測定する電圧測
定手段とを具備し、前記電源に接続すべき電子部品の端
子間絶縁抵抗値が100kΩ以上であり、前記負荷抵抗
の抵抗値が前記電源に接続すべき電子部品の端子間絶縁
抵抗値の1/1000以下であることを特徴とする。
SUMMARY OF THE INVENTION An electronic component reliability evaluation apparatus and an electronic component reliability evaluation method according to the present invention have been made to solve the above problems, and have the following features. An electronic component reliability evaluation device according to the present invention is an electronic component reliability evaluation device that evaluates insulation resistance between terminals of an electronic component, and is connected to a terminal of the electronic component whose insulation resistance is to be measured. A power supply capable of applying a voltage between its terminals, a load resistance connected between the power supply and the electronic component, and voltage measuring means for measuring a voltage between both terminals of the load resistance; The insulation resistance between terminals of the electronic component to be connected to the power supply is 100 kΩ or more, and the resistance value of the load resistance is 1/1000 or less of the insulation resistance between terminals of the electronic component to be connected to the power supply. I do.

【0013】また、前記電子部品の端子間絶縁抵抗値が
1000kΩ以上であり、前記負荷抵抗の抵抗値が前記
電子部品の端子間絶縁抵抗値の1/10000以下であ
ることを特徴とする。
[0013] Also, the present invention is characterized in that the inter-terminal insulation resistance value of the electronic component is 1000 kΩ or more, and the resistance value of the load resistance is 1/10000 or less of the inter-terminal insulation resistance value of the electronic component.

【0014】また、本発明に記載の電子部品の信頼性評
価方法は端子間絶縁抵抗の変動を用いた電子部品の信頼
性評価方法であって、前記電子部品の端子間抵抗値より
も小さい抵抗値の負荷抵抗を直列接続して前記端子間に
電圧を引加する工程と、前記負荷抵抗両端の抵抗値変動
を測定する工程と、前記抵抗値変動が所望値に到達した
ときに前記電圧引加を停止する工程とを具備したこを特
徴とする。
Further, the method for evaluating the reliability of an electronic component according to the present invention is a method for evaluating the reliability of an electronic component using variation in insulation resistance between terminals, wherein the resistance of the electronic component is smaller than the resistance between terminals of the electronic component. Connecting a load resistance having a value in series to apply a voltage between the terminals, measuring a resistance value variation between both ends of the load resistor, and when the resistance value variation reaches a desired value, And stopping the addition.

【0015】更に、本発明に記載の電子部品の信頼性評
価方法は端子間絶縁抵抗の変動を用いた電子部品の信頼
性評価方法であって、前記電子部品の端子間抵抗値より
も小さい抵抗値の負荷抵抗を電子部品の端子間に直列接
続して前記端子間に電圧を継続して引加する工程と、前
記電圧を継続して引加する工程と同時に前記負荷抵抗両
端の抵抗値を継続して測定する工程とを具備し、前記負
荷抵抗値が前記電子部品の端子間抵抗値の1/1000
以下であることを特徴とする。
Further, the method for evaluating the reliability of an electronic component according to the present invention is a method for evaluating the reliability of an electronic component using a variation in insulation resistance between terminals, wherein the resistance is smaller than the resistance between terminals of the electronic component. A step of connecting a load resistance of a value in series between the terminals of the electronic component to continuously apply a voltage between the terminals, and a step of continuously applying the voltage, simultaneously with the step of applying the voltage, the resistance value between both ends of the load resistor. Continuously measuring, wherein the load resistance is 1/1000 of the inter-terminal resistance of the electronic component.
It is characterized by the following.

【0016】[0016]

【発明の実施の形態】以下、図面を参照しながら、本発
明の実施の形態(以下、実施形態と略す)に付いて詳細
に説明する。 (第1の実施形態)図1(A)は、本発明の第1の実施
形態に係るプリント配線板評価装置(電子部品評価装
置)にプリント配線板を接続した時の概略図である。
Embodiments of the present invention (hereinafter, abbreviated as embodiments) will be described in detail with reference to the drawings. (First Embodiment) FIG. 1A is a schematic diagram when a printed wiring board is connected to a printed wiring board evaluation device (electronic component evaluation device) according to a first embodiment of the present invention.

【0017】図1(A)では、電源1に評価用のプリン
ト配線板2と、10kΩの抵抗(負荷抵抗)5とが直列
に接続されている。また、抵抗5の両端子間には並列に
電圧計6が接続されて、常時電圧がモニター可能となっ
ており、電圧計6でモニターされた電圧は電圧計6に接
続されたペンレコーダーで常時記録されている。図1
(A)に概略表面図を示したプリント配線板2は、評価
用に作成された多層プリント板であり、その最外表面に
互いに一定距離離間して櫛の歯状に配線部が形成され、
その一端で全配線部が集束しているテストパターン2A
と、そのテストパターン2Aの隣接する櫛の歯状配線部
間の中央部に、同様に櫛の歯状に形成された配線部が位
置するようにテストパターン2Aと同一形状のテストパ
ターン2Bとが形成されている。テストパターン2A,
2Bはそれぞれ全配線部が集束した端子部2C,2Dを
有し、この部分で外部と電気的に接続可能とされてい
る。テストパターン2Aとテストパターン2Bは、それ
ぞれ厚さ18ミクロンの銅配線層で形成されている。テ
ストパターン2A,2Bの櫛の歯部の配線幅は100ミ
クロンであり、隣接するテストパターン2A,2B間の
配線間の間隔も100ミクロンである。
In FIG. 1A, a printed wiring board 2 for evaluation and a resistance (load resistance) 5 of 10 kΩ are connected in series to a power supply 1. A voltmeter 6 is connected in parallel between the two terminals of the resistor 5 so that the voltage can be monitored at all times. The voltage monitored by the voltmeter 6 is constantly monitored by a pen recorder connected to the voltmeter 6. Has been recorded. FIG.
The printed wiring board 2 whose schematic surface view is shown in (A) is a multilayer printed board prepared for evaluation, and has a comb-shaped wiring portion formed on the outermost surface thereof at a certain distance from each other,
Test pattern 2A where all wiring parts are converged at one end
And a test pattern 2B having the same shape as the test pattern 2A so that a wiring portion similarly formed in the shape of a comb is located at the center between adjacent comb tooth-shaped wiring portions of the test pattern 2A. Is formed. Test pattern 2A,
2B has terminal portions 2C and 2D in which all the wiring portions are converged, and these portions can be electrically connected to the outside. The test pattern 2A and the test pattern 2B are each formed of a copper wiring layer having a thickness of 18 microns. The wiring width of the comb teeth of the test patterns 2A and 2B is 100 microns, and the distance between the wirings between the adjacent test patterns 2A and 2B is also 100 microns.

【0018】このプリント配線板2のA−A’に沿った
断面の概略断面図を図1(B)に示す。図1(B)に示
したように、このプリント配線板2は三層の層間絶縁膜
21,22,23と、4層の配線層から成る4層の多層
基板であり、層間絶縁膜21,22,23は順に厚さ6
0ミクロン,250ミクロン,60ミクロンの有機絶縁
材料である。本実施の形態ではこの有機絶縁材料として
BTレジンが用いられている。これは、PPE、FR−
4等であっても良い。また、これらの材料のうち、異種
のものを積層して用いても良い。また、配線層は銅であ
る。このプリント配線板2では4層の各配線層に上記と
同形状のテストパターン2Aとテストパターン2Bが等
間隔に形成されており、また、各配線層のテストパター
ン2A,2Bは各層でそれぞれほぼ同一の位置に形成さ
れている。各配線層のテストパターン2A,2Bはそれ
ぞれの端子部2C,2Dで、図示しない全層を貫通した
スルーホールによって接続されている。
FIG. 1B is a schematic sectional view of a section of the printed wiring board 2 along AA '. As shown in FIG. 1B, the printed wiring board 2 is a four-layered multi-layer substrate including three interlayer insulating films 21, 22, 23 and four wiring layers. 22 and 23 are thickness 6 in order
It is an organic insulating material of 0 micron, 250 micron, and 60 micron. In the present embodiment, BT resin is used as the organic insulating material. This is PPE, FR-
It may be 4 or the like. Further, among these materials, different materials may be laminated and used. The wiring layer is made of copper. In the printed wiring board 2, test patterns 2A and 2B having the same shape as described above are formed at equal intervals on each of the four wiring layers, and the test patterns 2A and 2B of each wiring layer are substantially equal to each other. They are formed at the same position. The test patterns 2A and 2B of each wiring layer are connected to each other at terminal portions 2C and 2D by through holes penetrating all layers (not shown).

【0019】テストパターン2A,2Bの端子部2C,
2Dはそれぞれ電源1の+電極,−電極に接続されてい
る。この状態で、電源1により端子部2C,2D間にプ
リント配線板の使用電圧を一定時間印加する(例えば8
5℃、85%の高温高湿雰囲気で、5.5Vを1000
時間引加する)。尚、ショートが発生した場合に過大電
流が流れるのを防ぐために電源1は0.01A以上の電
流が流れないように電源1にはリミッタが設定されてい
る。
The terminal portions 2C of the test patterns 2A, 2B,
2D is connected to the + electrode and-electrode of the power supply 1, respectively. In this state, the power supply 1 applies a working voltage of the printed wiring board between the terminal portions 2C and 2D for a certain period of time (for example, 8
In a high temperature and high humidity atmosphere of 5 ° C. and 85%, 5.5 V is applied to 1000
Add time). In order to prevent an excessive current from flowing when a short circuit occurs, a limiter is set in the power supply 1 so that a current of 0.01 A or more does not flow.

【0020】次のこの評価装置を用いて、プリント配線
板の信頼性評価を行う方法について説明する。まず、図
1 (A)の状態で電源1によりプリント配線板2の端子
部2C,2D間に5.5Vの電圧を引加した。この際、
抵抗5の両端子間の電圧はほぼ0Vであった。なお、評
価に先だって確認したプリント配線板2の端子部2C,
2D間の抵抗は1011Ω乃至1013Ω程度であり、抵抗
5の10kΩ(104Ω)よりも十分に大きかった。
Next, a method for evaluating the reliability of a printed wiring board using this evaluation apparatus will be described. First, figure
1 A voltage of 5.5 V was applied between the terminal portions 2C and 2D of the printed wiring board 2 by the power supply 1 in the state of FIG. On this occasion,
The voltage between both terminals of the resistor 5 was almost 0V. In addition, the terminal portions 2C of the printed wiring board 2 which were confirmed prior to the evaluation,
The resistance between 2D was about 10 11 Ω to 10 13 Ω, which was sufficiently larger than the resistance 5 of 10 kΩ (10 4 Ω).

【0021】次にこの装置にプリント配線板2を図1
(A)のように接続したまま5.5Vの電圧引加を続け
たところ、10時間程度の引加時間で抵抗5の両端子間
の電圧(ペンレコーダー7でモニターされる電圧)が上
昇を始めるものがあった。電圧上昇の開始から1秒以
下、乃至1時間程度の比較的短時間の間にこの電圧はほ
ぼ5.5Vに到達したものが多かった。ここで、プリン
ト配線板2を取外して端子部2C,2D間の抵抗を測定
したところ,100Ω以下に低下しているものがあり、
105Ω程度に低下しているものが多かった。尚,端子
部2C,2D間を上述の配線幅の銅配線で接続した場合
でも100Ω程度の抵抗を持つので、端子間絶縁抵抗の
低下の著しいものは、ほぼショートした状態と推測でき
る。
Next, a printed wiring board 2 is connected to this apparatus in FIG.
As shown in (A), when the voltage application of 5.5 V was continued while connected, the voltage between both terminals of the resistor 5 (the voltage monitored by the pen recorder 7) increased in the application time of about 10 hours. There was something to start. This voltage almost reached 5.5 V in a relatively short time of 1 second or less or about 1 hour after the start of the voltage rise. Here, when the printed wiring board 2 was removed and the resistance between the terminal portions 2C and 2D was measured, it was found that the resistance dropped to 100Ω or less.
Many were reduced to about 10 5 Ω. Even when the terminal portions 2C and 2D are connected by the copper wiring having the above-described wiring width, the terminal portions 2C and 2D have a resistance of about 100Ω.

【0022】ここで、従来技術に記載した方法では端子
部2C,2D間の抵抗が低下するとプリント配線板2の
ショートした部分にはリミッタで設定された例えば0.
01Aの電流が流れてしまう。しかしながら本実施形態
に記載の装置を用いれば、プリント配線板に直列に10
kΩの抵抗が接続されているため、プリント配線板2の
ショートした部分に500μA程度以上の電流が流れる
ことは無い。
Here, according to the method described in the prior art, when the resistance between the terminal portions 2C and 2D decreases, the short-circuited portion of the printed wiring board 2 is set to, for example, 0.
A current of 01A flows. However, if the device described in the present embodiment is used, 10
Since a resistor of kΩ is connected, a current of about 500 μA or more does not flow in the short-circuited portion of the printed wiring board 2.

【0023】本実施形態に係る評価方法を用いることに
より、ペンレコーダー7でモニターされる電圧を常時確
認していれば、プリント配線板の不良発生を早期に確認
することが出来、プリント配線板の不良解析、設計変更
に早期に着手することが可能となった。
By using the evaluation method according to the present embodiment, if the voltage monitored by the pen recorder 7 is constantly checked, the occurrence of a defect in the printed wiring board can be checked at an early stage, and the printed wiring board can be checked. Failure analysis and design changes can be started early.

【0024】尚、本実施形態で、ペンレコーダーに替え
て、或いは、ペンレコーダーと並列に電圧リミッターを
接続し、一定電圧になったところをモニターして電源を
切断する、ないし、アラーム等の終了シグナルを出力す
ることが可能である。このような構成にすることで、更
に早期に、また、無人稼動中でも不良発生を確認し、電
圧引加を停止することが出来る。
In the present embodiment, a voltage limiter is connected in place of the pen recorder or in parallel with the pen recorder, and when a constant voltage is reached, the power is cut off and the power is turned off. It is possible to output a signal. With such a configuration, it is possible to confirm the occurrence of a defect earlier and even during unattended operation, and stop the voltage application.

【0025】また、本実施形態ではプリント配線板の評
価方法について説明したが、被評価物はプリント配線板
に限ることはなく、絶縁抵抗を要する電子部品であれば
良い。この際、被評価物の絶縁抵抗の最低値に対し、抵
抗5としては1/100以下の抵抗値を持つ抵抗が必要
であり、望ましくは1/1000以下の抵抗値であれば
測定が容易である。本実施形態では上記のように約1/
10000であった。また、ペンレコーダー7等で電圧
変化をモニターするには抵抗5は最低1kΩ以上が必要
である。
In this embodiment, the method for evaluating a printed wiring board has been described. However, the object to be evaluated is not limited to a printed wiring board, but may be any electronic component that requires insulation resistance. At this time, a resistance having a resistance value of 1/100 or less is required as the resistance 5 with respect to the lowest value of the insulation resistance of the device to be evaluated. is there. In the present embodiment, about 1 /
It was 10,000. Further, in order to monitor the voltage change with the pen recorder 7 or the like, the resistance 5 must be at least 1 kΩ or more.

【0026】上記より、被評価物の絶縁抵抗は最低10
0kΩ程度は必要であり、1000kΩ以上であること
望ましい。また、絶縁抵抗値の変化を感度良く検出する
には、不良となった時の被測定物の絶縁抵抗が初期抵抗
値の1/1000程度以下に減少することが望ましい。
From the above, the insulation resistance of the device to be evaluated is at least 10
A value of about 0 kΩ is required, and is preferably 1000 kΩ or more. Further, in order to detect a change in the insulation resistance value with high sensitivity, it is desirable that the insulation resistance of the device under test when it becomes defective is reduced to about 1/1000 or less of the initial resistance value.

【0027】尚,抵抗5の値は、引加電圧条件が異なる
場合にはそれに合わせて、最大電流が大きく成り過ぎな
いように調整する必要がある。例えば、引加電圧を60
Ωとする場合には、最大電流を500μAに押さえるよ
うに、抵抗5は100kΩを用いれば良い。
When the applied voltage condition is different, it is necessary to adjust the value of the resistor 5 so that the maximum current does not become too large. For example, if the applied voltage is 60
In the case of Ω, the resistor 5 may use 100 kΩ so that the maximum current is suppressed to 500 μA.

【0028】(第2の実施形態)次に本発明の第2の実
施形態について説明する。本実施形態で用いた評価装置
は第一の実施形態で用いた装置と同一なので説明を省略
する。
(Second Embodiment) Next, a second embodiment of the present invention will be described. The evaluation device used in the present embodiment is the same as the device used in the first embodiment, and a description thereof will be omitted.

【0029】本実施形態では、プリント配線板のショー
ト不良の解析を行うべく、ペンレコーダー7で5.5V
程度の電圧変動の発生を確認後直ちに電圧引加を停止し
て、プリント配線板2の端子部2C,2D間の抵抗を測
定した。
In the present embodiment, in order to analyze a short circuit failure of the printed wiring board, the pen recorder 7 uses 5.5V.
Immediately after confirming the occurrence of a small voltage fluctuation, the voltage application was stopped, and the resistance between the terminals 2C and 2D of the printed wiring board 2 was measured.

【0030】端子部2C,2D間の抵抗は、107Ω程
度であり、上述の第一の実施形態で記載したショートほ
ど進行していないが、初期抵抗からは大きく(10-4
乃至10-6倍程度)変化していることが確認された。
The resistance between the terminal portions 2C and 2D is about 10 7 Ω, which does not progress as much as the short circuit described in the first embodiment, but is larger than the initial resistance (10 -4 times to 10 times). (About -6 times).

【0031】図2に示すようにこのプリント配線板2に
光源14より光15を照射し、透過光16を光学顕微鏡
の対物レンズ13に入射することにより観察したとこ
ろ、図3に示すように配線2A,2B間を短絡するよう
な黒変部11が観察された。尚、図3の倍率は図4の倍
率と同一である。黒変部11は図示したように配線2
A,2B間を、折り曲がりながら途中に樹木状に細い黒
変部11Aを分岐しつつ配線2A,2B間を接続するよ
うに形成されていた。また、これらの黒変部11はプリ
ント配線板2の表面にある場合、やや中にある場合、内
部の配線層間に形成されている場合などさまざまであっ
た。尚、内部の配線層間に黒変部がある場合でも、BT
レジンは光透過性なので、光学顕微鏡の焦点深度を調整
して同様の黒変を観察することが出来た。
As shown in FIG. 2, the printed wiring board 2 was irradiated with light 15 from a light source 14 and the transmitted light 16 was observed by being incident on an objective lens 13 of an optical microscope. As shown in FIG. Black discolored portions 11 that short-circuit between 2A and 2B were observed. The magnification in FIG. 3 is the same as the magnification in FIG. The blackened portion 11 is the wiring 2
The wirings 2A and 2B are formed to be connected between the wirings 2A and 2B while branching between the A and 2B and branching into a tree-like black discolored portion 11A while bending. In addition, there are various cases where these black discolored portions 11 are on the surface of the printed wiring board 2, are slightly inside, or are formed between internal wiring layers. It should be noted that even when there is a blackened portion between the internal wiring layers, the BT
Since the resin was light-transmitting, the same blackening could be observed by adjusting the depth of focus of the optical microscope.

【0032】また、これらの黒変部11の周囲には多く
の場合空洞12が形成されていた。これらの空洞12の
成因は明確ではないが、黒変部12の温度上昇によって
周囲のBTレジンが揮発して形成されたものと推測され
た。
In many cases, cavities 12 were formed around these blackened portions 11. Although the cause of these cavities 12 is not clear, it was presumed that the surrounding BT resin was volatilized and formed due to the temperature rise of the black discolored portions 12.

【0033】次のこの黒変部12近傍部分をサンプリン
グして赤外分光分析したところ、セルロースの成分が検
出されたものがあった。このセルロースの成分は多層プ
リント配線板11のBTレジンの積層時に工程冶具に用
いられている繊維から混入したものと推定された。ま
た、同様に黒変部近傍の表面のXMA分析で,鉄などの
金属が検出されたものもあった。これらは,部品,材料
の製造工程からの混入と推定された。
When the next portion near the blackened portion 12 was sampled and subjected to infrared spectroscopy, it was found that some cellulose components were detected. It was presumed that this cellulose component was mixed from the fibers used in the process jig when the BT resin of the multilayer printed wiring board 11 was laminated. Similarly, in some cases, metals such as iron were detected by XMA analysis of the surface near the blackened portion. These were presumed to be from the manufacturing process of parts and materials.

【0034】以上のように本実施の形態を用いることに
より、早期にショート不良の発生を確認することが出
来、不良発生部位の特定、不良原因の推定が容易になっ
た。また、それに伴って工程管理に速やかにフィードバ
ックをかけることが可能となり、工程上の問題を早期に
解決する事が可能となった。
As described above, by using the present embodiment, the occurrence of a short-circuit failure can be confirmed at an early stage, and it becomes easy to specify the location of the failure and to estimate the cause of the failure. In addition, it has become possible to promptly give feedback to the process management, thereby making it possible to solve problems in the process at an early stage.

【0035】また、上述のペンレコーダー7の記録から
不良発生に、いくつかのパターンがあることがわかっ
た。即ち、 1)電圧変動の開始から急激に5.5V近辺まで一気に
変動し、そのまま安定してしまうもの、 2)瞬間的に5.5Vまで変動し、すぐに0V近辺まで
戻るもの。 3)上記2とほぼ同様に瞬間的に変動して元に戻るが、
また、数分、乃至、数十時間後に同様に瞬間的な変動を
示すもの。 などが確認された。このうち,上記の2,3に記載した
不良は変化時間が極めて短く、1msecに追従可能な
高速ペンレコーダを用いても十分に追従出来ない場合が
多かった。また、数回上記の3に示したような変動を示
した後に、上記1のような不良と成る場合もあった。こ
れらの不良に対し、それぞれに不良原因を確認して対策
を取ることが出来た。上記に述べた各不良では、2,3
のように極めて短時間の変動のみが見られた場合でも、
プリント配線板の何れかの場所に上記第2の実施形態で
述べたような黒変が,例えわずかではあっても観察され
た。このような微小な変化は従来の評価方法では検知不
可能なものであり、ペンレコーダー等による連続した電
圧のモニターが極めて有効であることがわかった。
Further, it was found from the recording of the pen recorder 7 that there were several patterns in the occurrence of defects. That is, 1) those which fluctuate suddenly from the start of voltage fluctuation to around 5.5 V and stabilize as they are, and 2) those which fluctuate to 5.5 V instantly and return to around 0 V immediately. 3) Although it fluctuates instantaneously and returns to its original state in almost the same manner as in 2 above,
In addition, those which show an instantaneous fluctuation similarly after several minutes to several tens of hours. And so on. Of these, the defects described in the above 2 and 3 have extremely short change times, and often cannot be sufficiently followed even by using a high-speed pen recorder capable of following 1 msec. In addition, there are cases in which a defect such as the above 1 occurs after several times of the fluctuation shown in the above 3 are shown. For each of these failures, the cause of the failure was confirmed and countermeasures could be taken. For each of the defects mentioned above,
Even if only a very short-term fluctuation is seen like
Black discoloration as described in the second embodiment was observed at any location on the printed wiring board, even if it was slight. Such a minute change cannot be detected by the conventional evaluation method, and it has been found that continuous voltage monitoring using a pen recorder or the like is extremely effective.

【0036】以上述べたように、本発明の第1ないし第
2の実施形態を用いることにより、プリント配線板のシ
ョート不良を早期に確認することが出来るようになっ
た。これに伴って、プリント配線板の設計変更を短期間
で行うことが出来るようになった。
As described above, by using the first and second embodiments of the present invention, a short circuit failure of a printed wiring board can be confirmed at an early stage. Along with this, the design change of the printed wiring board can be performed in a short time.

【0037】なお、上記の各実施形態では有機絶縁層と
してBTレジンを用いたが、これらに替えて、FR−
4,PPE等の樹脂を用いても良い。これらの樹脂も光
透過性であり、内層配線部に発生したショートの目視確
認が可能である。また、光非透過性の樹脂であっても、
表面観察でショートを確認することは可能であり、本発
明の効果を享受できる。さらに、上記の各実施形態では
配線層として銅配線層を用いたが、導電層であれば銅に
限らないことは言うまでもない。
In each of the above embodiments, BT resin was used as the organic insulating layer.
4, a resin such as PPE may be used. These resins are also light-transmissive, so that short-circuits occurring in the inner-layer wiring portion can be visually confirmed. In addition, even if the resin is a light-impermeable resin,
It is possible to confirm a short circuit by observing the surface, and the effects of the present invention can be enjoyed. Furthermore, although a copper wiring layer is used as a wiring layer in each of the above embodiments, it is needless to say that the conductive layer is not limited to copper.

【0038】さらに、配線板は、プリント配線板に限ら
れるものではなく、上記の構成が適用可能な基板であれ
ば良く、セラミック多層板等でもよい。また、本願の基
本構成は配線板の評価に限定される物ではなく、耐圧低
下の起こり得る半導体素子、電子部品などにも適用可能
である。
Further, the wiring board is not limited to a printed wiring board, but may be any substrate to which the above-described configuration can be applied, and may be a ceramic multilayer board or the like. In addition, the basic configuration of the present application is not limited to the evaluation of a wiring board, but can be applied to a semiconductor element, an electronic component, and the like in which a withstand voltage may decrease.

【0039】[0039]

【発明の効果】上述のように本発明の装置を用いること
により、プリント配線板のショート不良発生時に過大電
流を流さずに不良を検出することが出来るようになっ
た。また、上述のように本発明の方法を用いることによ
り、プリント配線板のショート不良を早期に確認するこ
とが出来るようになった。これに伴って、プリント配線
板の設計変更を短期間で行うことが出来るようになっ
た。
As described above, the use of the apparatus of the present invention makes it possible to detect a short-circuit failure of a printed wiring board without causing an excessive current to flow. Further, by using the method of the present invention as described above, a short circuit failure of a printed wiring board can be confirmed at an early stage. Along with this, the design change of the printed wiring board can be performed in a short time.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態に係るプリント配線板
とその評価装置の概略図である。
FIG. 1 is a schematic diagram of a printed wiring board and a device for evaluating the same according to a first embodiment of the present invention.

【図2】プリント配線板の不良箇所の顕微鏡観察方法を
示した概略見取り図である。
FIG. 2 is a schematic view showing a method for observing a defective portion of a printed wiring board with a microscope.

【図3】本発明のプリント配線板の評価方法で発生した
プリント配線板のショート不良発生箇所の拡大表面図で
ある。
FIG. 3 is an enlarged surface view of a short-circuit failure portion of the printed wiring board generated by the method for evaluating a printed wiring board according to the present invention.

【図4】従来のプリント配線板の評価方法で発生したプ
リント配線板のショート不良発生箇所の拡大表面図であ
る。
FIG. 4 is an enlarged surface view of a short-circuit failure location of a printed wiring board generated by a conventional printed wiring board evaluation method.

【図5】従来のプリント配線板の評価方法を示した概略
図である。
FIG. 5 is a schematic view showing a conventional method for evaluating a printed wiring board.

【符号の説明】[Explanation of symbols]

1…電源 2…プリント配線板 2A、2B…テストパターン 2C,2D…端子部 4…絶縁抵抗測定計 5…抵抗(負荷抵抗) 6…電圧計 7…ペンレコーダー 10…ショート部分 11…黒変部 12…空洞 13…対物レンズ 14…光源 15…光(入射光) 16…透過光 21,22,23…層間絶縁膜 DESCRIPTION OF SYMBOLS 1 ... Power supply 2 ... Printed wiring board 2A, 2B ... Test pattern 2C, 2D ... Terminal part 4 ... Insulation resistance measurement meter 5 ... Resistance (load resistance) 6 ... Voltmeter 7 ... Pen recorder 10 ... Short part 11 ... Black discoloration part DESCRIPTION OF SYMBOLS 12 ... Cavity 13 ... Objective lens 14 ... Light source 15 ... Light (incident light) 16 ... Transmitted light 21, 22, 23 ... Interlayer insulating film

フロントページの続き (72)発明者 保泉 公昭 東京都府中市東芝町1番地 株式会社東芝 府中工場内 (72)発明者 笹岡 賢司 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝小向工場内 Fターム(参考) 2G014 AA03 AA15 AB59 AC09 AC15 2G028 AA02 BB11 BC01 CG03 DH03 FK02 LR01 LR07 MS05 5E346 GG34 HH31 Continued on the front page (72) Inventor Kimiaki Hoizumi 1 Toshiba-cho, Fuchu-shi, Tokyo Inside the Toshiba Fuchu Plant Co., Ltd. In-plant F-term (reference) 2G014 AA03 AA15 AB59 AC09 AC15 2G028 AA02 BB11 BC01 CG03 DH03 FK02 LR01 LR07 MS05 5E346 GG34 HH31

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】電子部品の端子間絶縁抵抗を評価する電子
部品用信頼性評価装置であって、絶縁抵抗を測定するべ
き前記電子部品の端子に接続してその端子間に電圧を引
加し得る電源と、前記電源と前記電子部品間に接続され
た負荷抵抗と、前記負荷抵抗の両端子間の電圧を測定す
る電圧測定手段とを具備し、前記電源に接続すべき電子
部品の端子間絶縁抵抗値が100kΩ以上であり、前記
負荷抵抗の抵抗値が前記電源に接続すべき電子部品の端
子間絶縁抵抗値の1/1000以下であることを特徴と
する電子部品用信頼性評価装置。
An electronic component reliability evaluation device for evaluating insulation resistance between terminals of an electronic component, wherein the reliability evaluation device is connected to a terminal of the electronic component whose insulation resistance is to be measured and a voltage is applied between the terminals. A power supply to be obtained, a load resistance connected between the power supply and the electronic component, and voltage measuring means for measuring a voltage between both terminals of the load resistance. An electronic component reliability evaluation device, wherein an insulation resistance value is 100 kΩ or more, and a resistance value of the load resistance is 1/1000 or less of an insulation resistance value between terminals of an electronic component to be connected to the power supply.
【請求項2】前記電子部品の端子間絶縁抵抗値が100
0kΩ以上であり、前記負荷抵抗の抵抗値が前記電子部
品の端子間絶縁抵抗値の1/10000以下であること
を特徴とする請求項1に記載の電子部品用信頼性評価装
置。
2. An electronic component having an insulation resistance between terminals of 100.
2. The reliability evaluation device for an electronic component according to claim 1, wherein the resistance value of the load resistance is 0 kΩ or more, and the resistance value of the load resistance is 1/10000 or less of an insulation resistance value between terminals of the electronic component. 3.
【請求項3】端子間絶縁抵抗の変動を用いた電子部品の
信頼性評価方法であって、前記電子部品の端子間抵抗値
よりも小さい抵抗値の負荷抵抗を直列接続して前記端子
間に電圧を引加する工程と、前記負荷抵抗両端の抵抗値
変動を測定する工程と、前記抵抗値変動が所望値に到達
したときに前記電圧引加を停止する工程とを具備したこ
を特徴とする電子部品の信頼性評価方法。
3. A method for evaluating the reliability of an electronic component using variation in insulation resistance between terminals, the method comprising: connecting a load resistance having a resistance value smaller than the resistance value between terminals of the electronic component in series to connect between the terminals. A step of applying a voltage, a step of measuring a resistance value variation between both ends of the load resistor, and a step of stopping the voltage application when the resistance value variation reaches a desired value. To evaluate the reliability of electronic components.
【請求項4】端子間絶縁抵抗の変動を用いた電子部品の
信頼性評価方法であって、前記電子部品の端子間抵抗値
よりも小さい抵抗値の負荷抵抗を電子部品の端子間に直
列接続して前記端子間に電圧を継続して引加する工程
と、前記電圧を継続して引加する工程と同時に前記負荷
抵抗両端の抵抗値を継続して測定する工程とを具備し、
前記負荷抵抗値が前記電子部品の端子間抵抗値の1/1
000以下であることを特徴とする電子部品の信頼性評
価方法。
4. A method for evaluating the reliability of an electronic component using variation in insulation resistance between terminals, wherein a load resistance having a resistance value smaller than a resistance value between terminals of the electronic component is connected in series between terminals of the electronic component. A step of continuously applying a voltage between the terminals, and a step of continuously measuring the resistance value across the load resistor simultaneously with the step of continuously applying the voltage,
The load resistance is 1/1 of the resistance between terminals of the electronic component.
000 or less, a method for evaluating the reliability of electronic components.
JP11114564A 1999-04-22 1999-04-22 Electronic part reliability evaluation device and electronic part reliability evaluation method Pending JP2000304801A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11114564A JP2000304801A (en) 1999-04-22 1999-04-22 Electronic part reliability evaluation device and electronic part reliability evaluation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11114564A JP2000304801A (en) 1999-04-22 1999-04-22 Electronic part reliability evaluation device and electronic part reliability evaluation method

Publications (1)

Publication Number Publication Date
JP2000304801A true JP2000304801A (en) 2000-11-02

Family

ID=14640983

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2000304801A (en)

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Cited By (9)

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Publication number Priority date Publication date Assignee Title
WO2007104229A1 (en) * 2006-03-13 2007-09-20 Huawei Technologies Co., Ltd. Method and system for evaluating the corrosion risk of a circuit board
CN102375092A (en) * 2010-08-05 2012-03-14 富士通株式会社 Multilayer wiring board and method for evaluating multilayer wiring board
CN104508503A (en) * 2012-08-23 2015-04-08 通力股份公司 Printed circuit arrangement
US9733300B2 (en) 2012-08-23 2017-08-15 Kone Corporation Corrosion detection system
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