JP2000208669A - Structure of hybrid integrated circuit device - Google Patents
Structure of hybrid integrated circuit deviceInfo
- Publication number
- JP2000208669A JP2000208669A JP901099A JP901099A JP2000208669A JP 2000208669 A JP2000208669 A JP 2000208669A JP 901099 A JP901099 A JP 901099A JP 901099 A JP901099 A JP 901099A JP 2000208669 A JP2000208669 A JP 2000208669A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- circuit board
- dielectric layer
- capacitor
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、各種の回路素子を
形成した半導体チップを、絶縁回路基板に対して直接的
に搭載して成るハイブリッド集積回路装置において、そ
の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a hybrid integrated circuit device in which a semiconductor chip on which various circuit elements are formed is directly mounted on an insulated circuit board.
【０００２】[0002]
【従来の技術】最近のハイブリッド集積回路装置におい
ては、その小型・軽量化を図ることのために、各種の回
路パターンを形成した絶縁回路基板に、各種の回路素子
を形成した半導体チップを直接的に搭載すると言ういわ
ゆるチップオン型に構成することが行われている。2. Description of the Related Art In a recent hybrid integrated circuit device, in order to reduce the size and weight of the device, a semiconductor chip having various circuit elements formed directly on an insulated circuit board having various circuit patterns formed thereon is used. A so-called chip-on type, which is mounted on a device, has been used.
【０００３】そして、このチップオン型のハイブリッド
集積回路装置において、その絶縁回路基板に搭載した半
導体チップに対しては、当該半導体チップを保護する等
のために、絶縁回路基板における電源回路パターン又は
グランド回路パターンとの間にコンデンサを設けること
が必要であり、従来は、このコンデンサを、前記半導体
チップとは別個にして、前記絶縁回路基板に搭載するよ
うに構成している。In this chip-on hybrid integrated circuit device, a power supply circuit pattern or a ground on the insulated circuit board is provided for the semiconductor chip mounted on the insulated circuit board in order to protect the semiconductor chip. It is necessary to provide a capacitor between the semiconductor chip and the circuit pattern. Conventionally, the capacitor is mounted on the insulated circuit board separately from the semiconductor chip.
【０００４】[0004]
【発明が解決しようとする課題】しかし、このように、
半導体チップの保護等に対するコンデンサを、前記半導
体チップとは別個にして絶縁回路基板に搭載すること
は、絶縁回路基板には、このコンデンサを搭載するため
のスペース、及び、このコンデンサに対する回路パター
ンを必要とするから、この分だけハイブリット集積回路
装置の小型・軽量化を図ることができないばかりか、こ
れに加えて前記コンデンサを搭載する手数が必要である
ために、価格のアップを招来すると言う問題があった。However, as described above,
Mounting a capacitor for protecting a semiconductor chip on an insulated circuit board separately from the semiconductor chip requires a space for mounting the capacitor and a circuit pattern for the capacitor on the insulated circuit board. Therefore, not only can the size and weight of the hybrid integrated circuit device not be reduced by that much, but also in addition to this, the trouble of mounting the capacitor is required, which leads to an increase in price. there were.
【０００５】本発明は、これらの問題を解消した構造を
提供することを技術的課題とするものである。An object of the present invention is to provide a structure that solves these problems.
【０００６】[0006]
【課題を解決するための手段】この技術的課題を達成す
るため本発明は、「各種の回路素子を形成した半導体チ
ップを、表面に回路パターンを形成した絶縁回路基板に
搭載して成るハイブリット集積回路装置において、前記
絶縁回路基板における表面のうち前記半導体チップの部
分に、前記回路パターンの一部に電気的に導通する適宜
面積の導体膜を形成し、この導体膜の表面に誘電体層を
形成し、この誘電体層の表面に前記半導体チップを導電
ペーストにて接着する。」と言う構成にした。In order to achieve this technical object, the present invention provides a hybrid integrated circuit comprising a semiconductor chip having various circuit elements formed on an insulated circuit board having a circuit pattern formed on its surface. In the circuit device, a conductor film having an appropriate area electrically connected to a part of the circuit pattern is formed on a portion of the semiconductor chip on a surface of the insulating circuit board, and a dielectric layer is formed on a surface of the conductor film. And bonding the semiconductor chip to the surface of the dielectric layer with a conductive paste. "
【０００７】[0007]
【発明の作用・効果】このように構成することにより、
絶縁回路基板の表面に形成した導体膜と、半導体チップ
に対する接着用の導電ペーストと、その間における誘電
体層とによってコンデンサを形成することができ、換言
すると、半導体チップに対する保護等のコンデンサを、
当該半導体チップの裏側に形成することができるのであ
る。Operation and effect of the present invention
A capacitor can be formed by the conductive film formed on the surface of the insulated circuit board, the conductive paste for bonding to the semiconductor chip, and the dielectric layer between them, in other words, a capacitor for protecting the semiconductor chip, etc.
It can be formed on the back side of the semiconductor chip.
【０００８】従って、本発明によると、絶縁回路基板に
半導体チップに対する保護等用のコンデンサを搭載する
ためのスペース及び回路パターンを設けること、並び
に、コンデンサを搭載することの工程を省略することが
できるから、絶縁回路基板の小型・軽量化、ひいては、
ハイブリッド集積回路装置の小型・軽量化を確実に達成
できると共に、低価格化を達成できる効果を有する。Therefore, according to the present invention, it is possible to provide a space and a circuit pattern for mounting a capacitor for protecting a semiconductor chip on an insulated circuit board, and to omit the steps of mounting the capacitor. From this, the size and weight of the insulated circuit board are reduced,
This has the effect that the size and weight of the hybrid integrated circuit device can be reliably reduced and the cost can be reduced.
【０００９】[0009]
【発明の実施の形態】以下、本発明の実施の形態を、図
１及び図２の図面について説明する。この図において、
符号１は、フレキシブル回路基板等の絶縁回路基板を示
し、この絶縁回路基板１の表面の一部には、半導体チッ
プ２を搭載するためのスペース３が設けられていると共
に、前記半導体チップ２に電気的に接続する各種の回路
パターン４、及び電源回路パターン５又はグランド回路
パターンが形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In this figure,
Reference numeral 1 denotes an insulated circuit board such as a flexible circuit board. A space 3 for mounting a semiconductor chip 2 is provided on a part of the surface of the insulated circuit board 1, and the semiconductor chip 2 Various circuit patterns 4 to be electrically connected and a power supply circuit pattern 5 or a ground circuit pattern are formed.
【００１０】前記絶縁回路基板１の表面にのうち前記半
導体チップ２を搭載するためのスペース３に、前記電源
回路パターン５に電気的に一体的に繋がる適宜面積の導
体膜６を形成する。なお、この導体膜６は、前記各種の
回路パターン４，５を、絶縁回路基板１の表面に対する
スクリーン印刷にて形成するとき、又は、絶縁回路基板
１の表面全体を形成した金属膜に対するホォトリソ法に
て形成するときにおいて同時に形成する。In the space 3 for mounting the semiconductor chip 2 on the surface of the insulated circuit board 1, a conductor film 6 having an appropriate area electrically connected to the power supply circuit pattern 5 is formed. The conductive film 6 may be formed when the various circuit patterns 4 and 5 are formed by screen printing on the surface of the insulated circuit board 1 or by a photolithography method on a metal film on the entire surface of the insulated circuit board 1. It is formed at the same time as the formation.
【００１１】そして、前記導体膜６の上面に、酸化チタ
ン、チタン酸バリウム又は窒化珪素等の誘電体層７を形
成したのち、この誘電体層７の上面に、前記半導体チッ
プ２を、銀ペースト等の導電ペースト８にて接着するの
である。なお、前記誘電体層７は、その薄板を前記導体
膜６に対して貼着することによって形成するか、前記導
体膜６に対して塗布することによって形成する。Then, after forming a dielectric layer 7 such as titanium oxide, barium titanate or silicon nitride on the upper surface of the conductor film 6, the semiconductor chip 2 is placed on the upper surface of the dielectric layer 7 with a silver paste. The conductive paste 8 is used for bonding. The dielectric layer 7 is formed by attaching the thin plate to the conductor film 6 or by applying the thin plate to the conductor film 6.
【００１２】このように構成することにより、絶縁回路
基板１の表面に形成した導体膜６と、半導体チップ２に
対する接着用の導電ペースト８と、その間における誘電
体層７とによってコンデンサを形成することができ、換
言すると、半導体チップ２に対する保護等のコンデンサ
を、当該半導体チップ２の裏側に形成することができる
のである。With this configuration, a capacitor is formed by the conductive film 6 formed on the surface of the insulated circuit board 1, the conductive paste 8 for bonding to the semiconductor chip 2, and the dielectric layer 7 therebetween. In other words, a capacitor for protecting the semiconductor chip 2 can be formed on the back side of the semiconductor chip 2.
【００１３】なお、前記コンデンサにおける静電容量
は、前記導体膜６、誘電体層７及び導電ペースト８の面
積によって任意に設定できることは言うまでもない。ま
た、前記半導体チップ２と、前記各回路パターン４との
間は、その間をワイヤボンディングした金属線９にて電
気的に接続され、この半導体チップ２の全体は、絶縁回
路基板１の上面に塗布した樹脂１０にてパッケージされ
ている。It goes without saying that the capacitance of the capacitor can be arbitrarily set according to the areas of the conductor film 6, the dielectric layer 7, and the conductive paste 8. The semiconductor chip 2 and each of the circuit patterns 4 are electrically connected to each other by a metal wire 9 wire-bonded therebetween, and the entire semiconductor chip 2 is coated on the upper surface of the insulated circuit board 1. Is packaged with the resin 10 as described above.
【図１】本発明の実施の形態を示す縦断正面図である。FIG. 1 is a longitudinal sectional front view showing an embodiment of the present invention.
【図２】本発明の実施の形態の分解した状態を示す斜視
図である。FIG. 2 is a perspective view showing an exploded state of the embodiment of the present invention.
１ 絶縁回路基板 ２ 半導体チップ ４ 回路パターン ５ 電源回路パターン ６ 導体膜 ７ 誘電体層 ８ 導電ペースト DESCRIPTION OF SYMBOLS 1 Insulated circuit board 2 Semiconductor chip 4 Circuit pattern 5 Power supply circuit pattern 6 Conductive film 7 Dielectric layer 8 Conductive paste
Claims (1)
を、表面に回路パターンを形成した絶縁回路基板に搭載
して成るハイブリット集積回路装置において、 前記絶縁回路基板における表面のうち前記半導体チップ
の部分に、前記回路パターンの一部に電気的に導通する
適宜面積の導体膜を形成し、この導体膜の表面に誘電体
層を形成し、この誘電体層の表面に前記半導体チップを
導電ペーストにて接着したことを特徴とするハイブリッ
ド集積回路装置の構造。1. A hybrid integrated circuit device in which a semiconductor chip on which various circuit elements are formed is mounted on an insulated circuit board having a circuit pattern formed on a surface thereof. A conductive film having an appropriate area that is electrically conductive to a part of the circuit pattern, a dielectric layer is formed on the surface of the conductive film, and the semiconductor chip is formed on the surface of the dielectric layer with a conductive paste. The structure of a hybrid integrated circuit device characterized by being adhered by bonding.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP901099A JP2000208669A (en) | 1999-01-18 | 1999-01-18 | Structure of hybrid integrated circuit device |
| TW89100582A TW441077B (en) | 1999-01-18 | 2000-01-15 | Hybrid integrated circuit device |
| KR1020000002245A KR20000071262A (en) | 1999-01-18 | 2000-01-18 | Electrical device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP901099A JP2000208669A (en) | 1999-01-18 | 1999-01-18 | Structure of hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000208669A true JP2000208669A (en) | 2000-07-28 |
Family
ID=11708693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP901099A Pending JP2000208669A (en) | 1999-01-18 | 1999-01-18 | Structure of hybrid integrated circuit device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2000208669A (en) |
| KR (1) | KR20000071262A (en) |
| TW (1) | TW441077B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007005561A (en) * | 2005-06-23 | 2007-01-11 | Fujitsu Ltd | Electronic device having double sided mounting circuit substrate with built-in capacitor |
| WO2007029445A1 (en) * | 2005-09-06 | 2007-03-15 | Matsushita Electric Industrial Co., Ltd. | Capacitor-equipped semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6442158A (en) * | 1987-08-10 | 1989-02-14 | Nec Corp | Hybrid integrated circuit device |
| JPH0435058A (en) * | 1990-05-31 | 1992-02-05 | Hitachi Ltd | Composite ic device and hybrid ic device |
| JPH08340059A (en) * | 1995-06-12 | 1996-12-24 | Oki Electric Ind Co Ltd | Semiconductor device packaging system |
| JPH09252076A (en) * | 1996-03-15 | 1997-09-22 | Sansei Denshi Japan Kk | Ic and lead frame therefor |
-
1999
- 1999-01-18 JP JP901099A patent/JP2000208669A/en active Pending
-
2000
- 2000-01-15 TW TW89100582A patent/TW441077B/en not_active IP Right Cessation
- 2000-01-18 KR KR1020000002245A patent/KR20000071262A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007005561A (en) * | 2005-06-23 | 2007-01-11 | Fujitsu Ltd | Electronic device having double sided mounting circuit substrate with built-in capacitor |
| JP4486553B2 (en) * | 2005-06-23 | 2010-06-23 | 富士通株式会社 | Electronic device having double-sided mounting circuit board with built-in capacitor |
| WO2007029445A1 (en) * | 2005-09-06 | 2007-03-15 | Matsushita Electric Industrial Co., Ltd. | Capacitor-equipped semiconductor device |
| US7884443B2 (en) | 2005-09-06 | 2011-02-08 | Panasonic Corporation | Semiconductor device having a mounting substrate with a capacitor interposed therebetween |
Also Published As
| Publication number | Publication date |
|---|---|
| TW441077B (en) | 2001-06-16 |
| KR20000071262A (en) | 2000-11-25 |
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Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20050601 |
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| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20060711 |