KR20000071262A - Electrical device - Google Patents
Electrical device Download PDFInfo
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- KR20000071262A KR20000071262A KR1020000002245A KR20000002245A KR20000071262A KR 20000071262 A KR20000071262 A KR 20000071262A KR 1020000002245 A KR1020000002245 A KR 1020000002245A KR 20000002245 A KR20000002245 A KR 20000002245A KR 20000071262 A KR20000071262 A KR 20000071262A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
전기장치는, 절연기판과, 기판에 의해 지지되며 제1의 전기적 기능을 수행하기 위해 배치된 제1의 부품과, 기판에 의해 지지되며 제2의 전기적 기능을 수행하기 위해 배치된 제2의 부품을 구비하고 있으며, 상기 제1과 제2의 부품은 상호 밀접하게 접촉되어 유지되어 있다.The electrical device includes an insulating substrate, a first component supported by the substrate and arranged to perform a first electrical function, and a second component supported by the substrate and arranged to perform a second electrical function The first and second parts are in intimate contact with each other.
Description
본 발명은 전기장치에 관하며, 더욱 상세하게는 단일기판상에 다른형의 부품이 장착된 하이브리드 집적회로(hybred IC)장치에 관한 것이다.TECHNICAL FIELD The present invention relates to electrical devices, and more particularly, to a hybrid IC device in which different types of components are mounted on a single substrate.
최근의 하이브리드 IC(integrated circuit)장치에 있어서는, 그 소형·경량화를 도모하기 위해, 각종의 회로패턴을 형성한 절연회로기판에, 각종의 회로소자를 형성한 반도체 칩을 직접적으로 탑재한다는 이른바 소위 칩온형(chip-on type)으로 구성하는 것이 행해지고 있다.In a recent hybrid IC (integrated circuit) device, a so-called chip that directly mounts a semiconductor chip on which various circuit elements are formed on an insulated circuit board on which various circuit patterns are formed in order to reduce its size and weight. The chip-on type is constructed.
알려진 바와 같이 전기적 손상 등에 대하여 그러한 칩온형을 보호하기 위해 캐패시터를 사용하게 되었다.As is known, capacitors have been used to protect such chip-on types against electrical damage.
캐패시터는 절연기판상에 형성된 반도체칩과 배선패턴(전력공급패턴 또는 접지회로패턴)간에 배치되어 있다.The capacitor is disposed between the semiconductor chip formed on the insulating substrate and the wiring pattern (power supply pattern or ground circuit pattern).
종래의 그러한 캐패시터는, 반도체칩과 별도로 제조되어 그 다음의 단계에서 기판상에 장착되었다.Such capacitors of the prior art were manufactured separately from the semiconductor chip and mounted on the substrate in the next step.
그러나, 이 방법에서는 절연기판의 장착 표면에 캐패시터를 장착시키기 위한 추가적인 공간이 필요하게 된다.However, this method requires additional space for mounting the capacitor on the mounting surface of the insulated substrate.
그리고, 기판상에 형성해야 할 캐패시터를 위한 추가적인 배선패턴이 필요하게 되어, 그 만큼 하이브리드 IC의 소형·경량화를 도모할 수가 없게 된다.Further, an additional wiring pattern for the capacitor to be formed on the substrate is required, and as a result, miniaturization and weight reduction of the hybrid IC cannot be achieved.
또한, 기판상에 캐패시터를 장착시키기 위한 추가적인 단계가 필요하게 되어 비용증가를 초래하게 된다는 문제가 있었다.In addition, there is a problem that an additional step for mounting a capacitor on the substrate is required, resulting in an increase in cost.
본 발명은 상기한 문제를 극복할 수 있는 하이브리드 IC장치를 제공하는데 그 목적이 있다.An object of the present invention is to provide a hybrid IC device that can overcome the above problems.
도 1은 본 발명의 전기장치의 세로단면도.1 is a longitudinal sectional view of the electrical apparatus of the present invention.
도 2는 도 1의 전기장치의 분해도.2 is an exploded view of the electrical device of FIG. 1;
(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
1. 기판 2. 반도체칩1. Substrate 2. Semiconductor Chip
3. 지지영역 4. 배선패턴3. Support Area 4. Wiring Pattern
5. 전력공급패턴 6. 도전층5. Power Supply Pattern 6. Conductive Layer
7. 유전체층 8. 도전층7. Dielectric layer 8. Conductive layer
9. 와이어 10. 수지패키지9. Wire 10. Resin Package
본 발명에 따른 전기장치는, 절연기판과, 기판에 의해 지지되며 제1의 전기적 기능을 수행하기 위해 배치된 제1의 부품과, 기판에 의해 지지되며 제2의 전기적 기능을 수행하기 위해 배치된 제2의 부품을 구비하고 있으며, 상기 제1과 제2의 부품은 상호 밀접하게 접촉되어 유지된 것을 특징으로 하고 있다.An electrical apparatus according to the present invention includes an insulating substrate, a first component supported by a substrate and arranged to perform a first electrical function, and supported by the substrate and arranged to perform a second electrical function. A second component is provided, wherein the first and second components are in intimate contact with each other.
그러한 배치에 의해 제1과 제2의 부품은 함께 밀접하게 유지된다.By such an arrangement, the first and second parts are held closely together.
따라서, 결과적인 장치는 바람직하게 크기와 중량이 작게 제조된다.Thus, the resulting device is preferably made small in size and weight.
바람직한 실시예에 있어서, 제1의 전기적 기능과 제2의 전기적 기능은 상이한 구성으로 되어 있다.In a preferred embodiment, the first electrical function and the second electrical function have different configurations.
바람직하게는, 제1의 부품은 평탄한 제1의 접촉면을 갖고, 제2의 부품은 평탄한 제2의 접촉면을 갖고 있다.Preferably, the first component has a first flat contact surface and the second component has a second flat contact surface.
그러한 배치로 제1과 제2의 부품은 이들 접촉면을 통하여 상호 견고히 부착될 수 있다.In such an arrangement the first and second parts can be firmly attached to each other via these contact surfaces.
바람직하게는, 제1의 부품은 제2의 부품 기판의 사이에 배치되어 있다.Preferably, the first component is disposed between the second component substrates.
이러한 방법에 의해, 제1의 부품은 장치에서 지나치게 돌출되는 것이 방지된다.By this method, the first part is prevented from protruding excessively from the apparatus.
바람직한 실시예에 따르면, 제1의 접촉면은 제2의 접촉면보다 면적이 크다.According to a preferred embodiment, the first contact surface is larger in area than the second contact surface.
이러한 방법에 의해, 제2의 접촉면은 제1의 접촉면에 의해 확실히 지지될 수 있다.In this way, the second contact surface can be reliably supported by the first contact surface.
그리고, 제1의 접촉면은 제2의 접촉면의 아래에 위치하고 있다.The first contact surface is located under the second contact surface.
바람직하게는, 제1의 부품은 캐패시터로 구성되고, 제2의 부품은 반도체칩으로 구성된다.Preferably, the first component is composed of a capacitor and the second component is composed of a semiconductor chip.
그러한 구성에 의해, 캐패시터를 구비하기 위한 추가의 별도의 단계가 필요하지 않게 된다.Such a configuration eliminates the need for additional separate steps for providing a capacitor.
캐패시터는 본 발명의 전기적장치를 제조하는 일련의 단계에서 제조된다.The capacitor is manufactured in a series of steps to manufacture the electrical device of the present invention.
바람직하게는, 반도체칩은 복수의 회로소자로 구성된다.Preferably, the semiconductor chip is composed of a plurality of circuit elements.
반도체칩은 IC칩이다.The semiconductor chip is an IC chip.
바람직하게는, 캐패시터는 기판에 형성된 제1의 도체와, 반도체칩에 부착된 제2의 도체와, 제1과 제2의 도체간에 배치된 유전체층으로 구성된다.Preferably, the capacitor is composed of a first conductor formed on the substrate, a second conductor attached to the semiconductor chip, and a dielectric layer disposed between the first and second conductors.
유익하게는 제2의 도체는 도전성이고 접착성재료로 구성된다.Advantageously the second conductor is conductive and consists of an adhesive material.
그러한 재료의 예는, 은함유 페이스트이다.An example of such a material is a silver containing paste.
바람직하게는 제1의 도체는 유전체층에 접촉되어 유지된 제1의 내부 표면을 갖고, 한편 제2의 도체는 유전체층에 접촉되어 유지된 제2의 내부 표면을 갖는다.Preferably the first conductor has a first inner surface held in contact with the dielectric layer, while the second conductor has a second inner surface held in contact with the dielectric layer.
그리고, 제1의 내부 표면은 제2의 내부 표면보다 면적이 크다.And, the first inner surface is larger in area than the second inner surface.
본 발명의 기타의 특징과 이점은 첨부된 도면을 참조한 다음의 상세한 설명으로부터 명백해질 것이다.Other features and advantages of the present invention will become apparent from the following detailed description with reference to the accompanying drawings.
(실시예)(Example)
이하, 본 발명의 실시예를 첨부 도면을 참조하여 설명한다.Best Mode for Carrying Out the Invention Embodiments of the present invention will be described below with reference to the accompanying drawings.
도 1과 도 2는 본 발명에 따른 하이브리드 IC장치를 나타낸다.1 and 2 show a hybrid IC device according to the present invention.
여기에 표시된 IC장치는, 절연성의 유연한 기판(1)과, 기판(1)의 지지영역(3)에 배치된 반도체칩(2)을 포함한다.The IC device shown here includes an insulating flexible substrate 1 and a semiconductor chip 2 arranged in the support region 3 of the substrate 1.
기판(1)의 상면에는 반도체칩(2)에 전기적으로 접속된 배선패턴(4) 및 전력공급패턴(5)이 형성되어 있다.The wiring pattern 4 and the power supply pattern 5 electrically connected to the semiconductor chip 2 are formed on the upper surface of the substrate 1.
또한 적절하게는, 접지회로패턴이 추가적으로 또는 선택적으로 형성되어 있다.Also suitably, the ground circuit pattern is additionally or selectively formed.
도 2에 나타내는 바와 같이, 기판(1)의 상면에는 전력공급패턴(5)에 접속된 도전층(6)이 형성되어 있다.As shown in FIG. 2, the conductive layer 6 connected to the power supply pattern 5 is formed on the upper surface of the substrate 1.
도전층(6)은 지지영역(3)에 배치되어 있고, 소정의 면적을 갖는 직4각형이나 정방형의 형태를 갖고 있다.The conductive layer 6 is disposed in the support region 3 and has a rectangular or square shape having a predetermined area.
도전층(6)과 배선패턴(4) 및 전력공급패턴(5)은 공지의 스크린 인쇄법으로 동시에 형성된다.The conductive layer 6, the wiring pattern 4 and the power supply pattern 5 are simultaneously formed by a known screen printing method.
또한, 기판(1)의 상면에 형성된 금속층에 사진인쇄법을 적용하므로서 그들을 형성하는 것도 가능하다.It is also possible to form them by applying a photo printing method to the metal layer formed on the upper surface of the substrate 1.
그후, 유전체층(7)은 도전층(6)상에 형성된다.Thereafter, a dielectric layer 7 is formed on the conductive layer 6.
여기서 얇은 유전체판을 도전층(6)의 상면에 부착시키거나, 또는 유전체 재료를 도전층(6)의 표면에 도포하는 것에 의해 형성할 수 있다.The thin dielectric plate can be formed by attaching a thin dielectric plate to the upper surface of the conductive layer 6 or by applying a dielectric material to the surface of the conductive layer 6.
그러한 유전체판이나 재료는, 예를들면 산화티탄, 바륨티탄산염, 실리콘질화물을 함유할 수 있다.Such dielectric plates and materials may contain titanium oxide, barium titanate, silicon nitride, for example.
도 1에 나타내는 바와 같이, 예를들면, 은을 함유하는 도전 및 접착페이스트는 반도체칩(2)을 유전체층(7)에 고정시키기 위해 유전체층(7)의 상면에 도포된다.As shown in FIG. 1, for example, silver-containing conductive and adhesive pastes are applied to the upper surface of the dielectric layer 7 to fix the semiconductor chip 2 to the dielectric layer 7.
도포된 도전페이스트는 상부도전층(8)으로서 작용한다.The applied conductive paste serves as the upper conductive layer 8.
복수의 회로소자로 구성된 반도체칩(2)은, 예를들면 금으로 제조된 복수의 와이어(9)를 통하여 배선패턴(4)에 전기적으로 접속된다.The semiconductor chip 2 composed of a plurality of circuit elements is electrically connected to the wiring pattern 4 via a plurality of wires 9 made of, for example, gold.
반도체칩(2), 와이어(9) 및 기타 소자는 기판의 상측에 도포한 수지재료로 제조된 수지패키지(10)에 의해 패키지된다.The semiconductor chip 2, the wire 9 and other elements are packaged by a resin package 10 made of a resin material coated on the upper side of the substrate.
본 발명에 따르면, 캐패시터는 기판(1)상에 형성된 하부도전층(6)과 상부도전층(8)과 두 도전소자간에 끼인 중간유전체층(7)의 조합에 의해 구성되어 있다.According to the invention, the capacitor is constituted by a combination of the lower conductive layer 6 and the upper conductive layer 8 formed on the substrate 1 and the intermediate dielectric layer 7 sandwiched between the two conductive elements.
그러한 배치에 의해, 전기적 손상으로부터 반도체칩(2)을 보호하기 위한 캐패시터는 반도체칩(2)의 후방 또는 아래에 위치하고 있다.With such an arrangement, a capacitor for protecting the semiconductor chip 2 from electrical damage is located behind or below the semiconductor chip 2.
이러한 특징은 장치를 소형화하고, 제조비용을 감소시키는데 유익하다.This feature is beneficial for miniaturizing the device and reducing manufacturing costs.
또, 본 발명의 장치를 제조하는데 있어서, 별도의 캐패시터를 기판상에 고정시키고 또한, 이것을 반도체칩에 접속하기 위한 추가적인 단계가 필요하지 않도록 캐패시터는 결합된다.In addition, in manufacturing the device of the present invention, the capacitors are combined so that a separate capacitor is fixed on the substrate and further steps are not required to connect it to the semiconductor chip.
도 1을 참조하면, 상부도전층(8)과 반도체칩(2)은 그들이 상호 부착된 평탄한 접촉면을 갖는다.Referring to FIG. 1, the upper conductive layer 8 and the semiconductor chip 2 have flat contact surfaces to which they are attached.
도전층(8)의 접촉면은 반도체칩(2)의 접촉면보다 면적이 크다.The contact surface of the conductive layer 8 has a larger area than the contact surface of the semiconductor chip 2.
따라서, 반도체칩(2)은 도전층(8)에 의해 안정되게 또한 견고히 지지된다.Therefore, the semiconductor chip 2 is stably and firmly supported by the conductive layer 8.
본 실시예에 따르면, 상면으로부터 보았을 때 하부도전층(6)이 상부도전층(8) 보다 크게 제조되어 있다.According to this embodiment, the lower conductive layer 6 is made larger than the upper conductive layer 8 when viewed from the top surface.
또한, 특히 양 하부 및 상부도전층(6, 8)은 유전체층(7)에 접촉 유지된 내부 표면을 갖는다.In addition, both the lower and upper conductive layers 6, 8 have an inner surface in contact with the dielectric layer 7.
하부도전층(6)의 내부 표면은 상부도전층(8)의 표면 보다 면적이 크게 제조되어 있다.The inner surface of the lower conductive layer 6 is made larger in area than the surface of the upper conductive layer 8.
쉽사리 이해되는 바와 같이, 상술한 캐패시터의 용량은 하부도전층(6)과 유전체층(7) 및 상부도전체층(8)의 표면적을 변경하므로서 조정 가능하다.As will be readily understood, the capacitance of the above-described capacitor can be adjusted by changing the surface areas of the lower conductive layer 6 and the dielectric layer 7 and the upper conductive layer 8.
이상과 같이 본 발명을 기술했지만 다른 많은 방법으로 변경할 수 있는 것은 명백하다.Although the present invention has been described above, it is obvious that the present invention can be modified in many other ways.
그러한 변경은 본 발명의 요지와 정신에서 일탈한다고 할 수 없고, 그러한 모든 변형은 이 기술에 숙련된 자는 다음의 청구항의 범위에 포함시키려고 의도할것이다.Such modifications are not to be regarded as a departure from the spirit and spirit of the invention, and all such modifications are intended to be included within the scope of the following claims by those skilled in the art.
본 발명의 전기장치에 따르면, 별도로 캐패시터를 기판상에 고정시키고 이것을 반도체칩에 접속하기 위한 추가적인 단계가 필요하지 않기 때문에, 장치를 소형화시키거나 저비용으로 제조할 수 있다는 이점이 있다.According to the electrical apparatus of the present invention, there is an advantage that the apparatus can be miniaturized or manufactured at low cost since an additional step for separately fixing the capacitor on the substrate and connecting it to the semiconductor chip is not necessary.
Claims (10)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11-9010 | 1999-01-18 | ||
| JP901099A JP2000208669A (en) | 1999-01-18 | 1999-01-18 | Structure of hybrid integrated circuit device |
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| Publication Number | Publication Date |
|---|---|
| KR20000071262A true KR20000071262A (en) | 2000-11-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000002245A KR20000071262A (en) | 1999-01-18 | 2000-01-18 | Electrical device |
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| Country | Link |
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| JP (1) | JP2000208669A (en) |
| KR (1) | KR20000071262A (en) |
| TW (1) | TW441077B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4486553B2 (en) * | 2005-06-23 | 2010-06-23 | 富士通株式会社 | Electronic device having double-sided mounting circuit board with built-in capacitor |
| CN101233614A (en) | 2005-09-06 | 2008-07-30 | 松下电器产业株式会社 | Capacitor-equipped semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6442158A (en) * | 1987-08-10 | 1989-02-14 | Nec Corp | Hybrid integrated circuit device |
| JPH0435058A (en) * | 1990-05-31 | 1992-02-05 | Hitachi Ltd | Composite ic device and hybrid ic device |
| JPH08340059A (en) * | 1995-06-12 | 1996-12-24 | Oki Electric Ind Co Ltd | Semiconductor device packaging system |
| JPH09252076A (en) * | 1996-03-15 | 1997-09-22 | Sansei Denshi Japan Kk | Ic and lead frame therefor |
-
1999
- 1999-01-18 JP JP901099A patent/JP2000208669A/en active Pending
-
2000
- 2000-01-15 TW TW89100582A patent/TW441077B/en not_active IP Right Cessation
- 2000-01-18 KR KR1020000002245A patent/KR20000071262A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6442158A (en) * | 1987-08-10 | 1989-02-14 | Nec Corp | Hybrid integrated circuit device |
| JPH0435058A (en) * | 1990-05-31 | 1992-02-05 | Hitachi Ltd | Composite ic device and hybrid ic device |
| JPH08340059A (en) * | 1995-06-12 | 1996-12-24 | Oki Electric Ind Co Ltd | Semiconductor device packaging system |
| JPH09252076A (en) * | 1996-03-15 | 1997-09-22 | Sansei Denshi Japan Kk | Ic and lead frame therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| TW441077B (en) | 2001-06-16 |
| JP2000208669A (en) | 2000-07-28 |
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