A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（i ) [發明背景] 1、 發明領域： 本發明係關於一種併合積體電路裝置，係具有不同之 安装在單一基體上的元件型式。 2、 相關技藝說明： 近來’併合積體電路（1C)裝置可以製成所謂的晶片上 型式’’chip-on type” ’即為半導體晶片（由許多電路元件所 形成）直接地建構在一個絕緣的基體上，如此安排的優點 在於整個裝置可以在尺寸及重量上做的更小。 如所知曉的，利用電容來對抗如電氣破壞以保護該晶 片上型式裝置，該電容器可以安排在半導體晶片及在絕緣 基體上形成的佈線圖（如同一個電源供應圖或接地電路圖） 之間。傳統上’該電容器是與半導體晶片分開來準備，且 在其後階段建構在基體上。 在這方法下’無論如何將需要一個額外在絕緣基體建 構表面上之電容建構空間，額外電容佈線圖亦需要在基體 上形成。結果，要在尺寸及重量上縮小併合積趙電路裝置 有不適當的限制。再者’需要額外在基體上建構電容的步 驊，將會導致成本增加之不利因素。 [發明概要] 本發明的目的是要提供一種併合積趙電路裝置使其有 能力克服上述的問題。 根據本發明，在此所提供的電子裝置包括有·· 絕緣基體； ^紙張尺度適用中國國家梯準（〇呢）八4规格（210><297公釐) -------- ----------襄-------玎------0 (請先閲讀背面之注意事項再填寫本頁) 1 311100 4 41 0 7 7 A7 M濟部智慧財產局員工消资合作社印製 五、發明説明（ 又基艘支樓及安排做為第一電子功能的第一元件； 受基體支撐及安排做為第二電子功能的第二元件； 其中第一和第二個元件保持在互相接近地接觸。 以該安排方式，第一和第二個元件接近地保持在一 因此，該完成裝置在尺寸及重量上具有縮小的優勢。 依據較佳的實施例，第一電子功能可以和第二個電子 功能不一樣》 較佳的是，該第一元件可有平坦的第一接觸表面，且 第二元件可有平坦的第二接觸表面。以該安排，則第一及 第二元件可以透過這些接觸表面互相堅固的依附著。 第一元件可以佈置於第二元件及基體之間，依此方 法防止第一元件該產品裝置不適當的放大上佔有優勢。 依據較佳的實施例’第一接觸表面在面積上可以大於 第二接觸表面。在此方法下，第二接觸表面可信賴地由第 一接觸表面支撐。第一接觸表面可以坐落在第二接觸表面 之下。 較佳的是’第一元件可包括電容器，而第二元件可包 括半導體晶片。以該安排方式，提供一個電容器是不需要 額外或分開的步驟，在一連串的步驟中可以準備一個用來 製作本發明電子裝置之電容器β 較佳的是，該半導體晶片可以設有許多的電路元件， 該半導體晶片可以是一個積艘電路晶片β 較佳的是，該電容器可以包括在基體上形成之第一導 電體、依附著半導《晶片之第二導電體、及安排在第一及 本紙張尺度遢用中國國家椹率（CNS ) A4ft格（210X297公釐> -- 起 ill· —---4 装！ (請先閲讀背面之注意事項再填寫本頁) 訂 -1¼ 2 311100A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (i) [Background of the invention] 1. Field of the invention: The present invention relates to a type of integrated circuit device with different components mounted on a single substrate. Pattern. 2. Relevant technical description: Recently, the "integrated integrated circuit (1C) device can be made into a so-called" chip-on type ", that is, a semiconductor wafer (formed by many circuit components) is directly constructed on an insulation The advantage of this arrangement on the substrate is that the entire device can be made smaller in size and weight. As is known, the capacitor can be used to resist, for example, electrical damage to protect the device on the chip. The capacitor can be arranged on the semiconductor chip and A wiring pattern (such as a power supply diagram or a ground circuit diagram) formed on an insulating substrate. Traditionally, the capacitor is prepared separately from the semiconductor wafer, and is constructed on the substrate at a later stage. In this method, regardless of How to build an additional capacitor construction space on the insulating substrate construction surface, and the additional capacitor wiring diagrams also need to be formed on the substrate. As a result, there is an undue limitation on reducing and integrating Zhao circuit devices in size and weight. Furthermore, ' The need to build additional capacitors on the substrate will lead to unfavorable factors of increased cost. Summary of the invention] The object of the present invention is to provide an integrated Zhao circuit device capable of overcoming the above-mentioned problems. According to the present invention, the electronic device provided herein includes an insulating substrate; ^ The paper size is applicable to the Chinese national ladder Quasi (〇 呢) 8 4 specifications (210 > < 297 mm) -------- ---------- Xiang ------- 玎 ------ 0 (Please read the notes on the back before filling out this page) 1 311100 4 41 0 7 7 A7 M Printed by the Consumers ’Cooperative of the Ministry of Economic Affairs and Intellectual Property, V. Invention Description The first element of electronic function; the second element supported and arranged by the substrate as the second electronic function; wherein the first and second elements are kept in close contact with each other. In this arrangement, the first and second elements It is kept close to one. Therefore, the finished device has the advantage of reduction in size and weight. According to a preferred embodiment, the first electronic function may be different from the second electronic function. Preferably, the first element There may be a flat first contact surface and the second element may have a flat second contact surface With this arrangement, the first and second components can be firmly adhered to each other through these contact surfaces. The first component can be arranged between the second component and the substrate, and in this way, the product of the first component and the device are not properly installed. It has advantages in terms of magnification. According to a preferred embodiment, 'the first contact surface may be larger in area than the second contact surface. In this method, the second contact surface may be reliably supported by the first contact surface. The first contact surface may be Located below the second contact surface. It is preferred that the 'first element may include a capacitor and the second element may include a semiconductor wafer. In this arrangement, providing a capacitor does not require additional or separate steps in a series of In the step, a capacitor β for preparing the electronic device of the present invention may be prepared. Preferably, the semiconductor wafer may be provided with a plurality of circuit elements, and the semiconductor wafer may be a build-up circuit wafer β. Preferably, the capacitor may be Including the first conductor formed on the substrate, the second conductor of the wafer according to the attached semiconductor, and the This paper untidy and a scale with the Chinese National Mulberry rate (CNS) A4ft grid (210X297 mm > - from ill · ---- 4 installed! (Please read the notes on the back before filling this page) Order -1¼ 2 311100
經濟部智慧財產局員工消资合作社印製 第二導電體之間之介電層。 第一導電體佔有可以由具導電性及黏合性物質製作上 之優勢例之該物質可以是包函銀的枯糊（paste)。 較佳的疋，該第一導電鱧可有與介電層保持接觸之第 一内表面，同時第二導電體可有與介電層保持接觸之第二 内表面。第一内表面可在面積上較第二内表層大。 本發明可以從參考下列附隨的圖式詳細敘述中，使其 特色及優點更明顯地表現出來。 [圖式之簡要說明] 第1囷是依據本發明所顯示的電子裝置垂直截面圖； 以及 第2圖是第1圖所示電子裝置的分解圖。 [元件符號之說明] 1 基體 2 半導體晶片 3 支撐區域 4 佈線圖 5 電源供應佈線圖 6 導電層 7 介電層 8 上導電層 9 佈線 10 樹脂包裝 [較佳實施例之詳細說明] 本發明之較佳實施例將參照所附圖式說明於下。 第1圓及第2圈係依據本發明顯示一個併合積體電路 (hrbrid integrated circuit)裝置》該顯示的積趙電路裝置包 括一個絕緣、具彈性的基體1，以及安排在基體1的支撐 區域3之半導髖晶片2»基艘1之上表面形成有佈線圖4, ----------^------tT------^ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家梂準（CNS ) A4規格（2丨0X297公釐） 3 311100 4 41 0 7 7 五、發明説明（4 係電氣連接至半導體晶片2，亦具有電源供應佈線圖5。 不論是否適當’接地電路圖可以額外或者交替地形成。 基艘1的上表面亦形成有以導電層6連接至電源供應 佈線圓5，如第2圖所示。導電層6安排在支撐區域3， 且具有事先決定面積的矩形或方形架構。 導電層6其佈線圖4及該電源供應佈線囷5可以同時 藉由一個已知絲網印製方法（screen printing method)同時 形成’亦可選擇藉由運用微影方式於基體1之上表面所形 成的金屬層來形成》 然後介電層7在導電層6上形成。為此目的，一個細 薄的介電板可以依附在導電層6之上表層，或者介電材料 可以運用在導電層6的上表面。該介電板或介電材料可以 包含例如氧化鈦，鈦睃鋇或氮化矽。如第1圖所示，包括 例如銀之導電性及黏合性粘糊，運用在介電層7的上表層 來固定半導體晶片2至該介電層7。所運用的導電性粘糊 將用作上導電層8。 設有許多電路元件的半導艘晶片2’經由許多例如金 所製作的佈線9電氣連接至佈線圖半導體晶片2、佈 線9及其他元件是由樹脂材料所製作的樹脂包裝1〇運用 在基體1的上側邊封起來。 依據本發明，電容是由在基艎i上形成的低導電層6 組合所提供，上導電層8及中間介電層7包夹在兩個導電 元件之間。 _以此安巧方式’用來保護半導想晶片2不夸Φ工柯^ 本紙張尺麟财關_準（CNS )从胁（2丨Gx297公着）----- ° 4 裝 訂 311100 A7 ________B7___ 五、發明説明（） 5 的電容器是安排在半導體晶片2後面或下面的位置。該特 徵為具有縮小裝置尺寸及減低生產成本的優點。再者，在 製作本發明之裝置時，電容器將合併因此不需額外的步驟 來使得分開的電容器固定至基體且將此電容器連接至丰道 艘晶片。 再參照第1圖，上導電層8及半導體晶片2具有透過 它們互相依附的平板接觸表面。該導電層8之接觸表面其 面積較半導體晶片2的接觸表面大。因此，半導體晶片2 藉由導電層8穩定且堅固地支撐著》 依據圖解之實施例，如以上所看到的，下導電層6做 成較上導電層8大。更特別地，該下導電層6及上導電層 8兩者皆有與介電層7保持接觸的内表面。該下導電層6 的内表面其面積做成較上導電層8者大。 可輕易的了解，上述的電容器電容值可以藉由變換低 導電層6、介電層7、上導電層8的表面積來進行調整》 依此敘述之本發明，很明顯地可以於變化其他許多的 方法仍是相同的，如此變化並未視為背離本發明的精神及 領域，且所有對該技藝上技術明顯修改仍應包括在下述的 專利範圍之内。 本紙張尺度逋用中國國家標牟（CNS ) A4規格（ 210X297公釐） 311100 f請先閱讀背面之注意事項再填寫本頁) 裝· 訂 經濟部智慧財產局員工消費合作社印製 5The dielectric layer between the second electrical conductor is printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. An example of the advantage of the first electric conductor being that it can be made of a conductive and adhesive substance is a paste of silver. Preferably, the first conductive plutonium may have a first inner surface in contact with the dielectric layer, while the second conductive body may have a second inner surface in contact with the dielectric layer. The first inner surface may be larger in area than the second inner surface layer. The present invention can be made more apparent from the detailed description with reference to the accompanying drawings below. [Brief Description of the Drawings] FIG. 1 is a vertical sectional view of an electronic device according to the present invention; and FIG. 2 is an exploded view of the electronic device shown in FIG. [Explanation of component symbols] 1 Base body 2 Semiconductor wafer 3 Support area 4 Wiring diagram 5 Power supply wiring diagram 6 Conductive layer 7 Dielectric layer 8 Upper conductive layer 9 Wiring 10 Resin packaging [Detailed description of preferred embodiments] The present invention Preferred embodiments will be described below with reference to the drawings. The first circle and the second circle show a hybrid integrated circuit device according to the present invention. The displayed integrated circuit device includes an insulating, elastic base 1 and a support area 3 arranged on the base 1. The semiconducting hip chip 2 »Wiring diagram 4 is formed on the upper surface of the base ship 1, ---------- ^ ------ tT ------ ^ (Please read the Note: Please fill in this page again) This paper size is applicable to China National Standard (CNS) A4 specification (2 丨 0X297mm) 3 311100 4 41 0 7 7 V. Description of the invention (4 series is electrically connected to semiconductor wafer 2 and also has Power supply wiring diagram 5. Regardless of whether or not the 'grounding circuit diagram' can be additionally or alternately formed. The upper surface of the base vessel 1 is also formed with a conductive layer 6 connected to the power supply wiring circle 5 as shown in Figure 2. The conductive layer 6 Arranged in the support area 3 and having a rectangular or square structure with a predetermined area. The conductive layer 6 and its wiring diagram 4 and the power supply wiring 囷 5 can be formed simultaneously by a known screen printing method. 'You can also choose to use lithography on the base 1 A metal layer is formed on the upper surface. Then a dielectric layer 7 is formed on the conductive layer 6. For this purpose, a thin dielectric plate can be attached to the surface layer above the conductive layer 6, or a dielectric material can be used on The upper surface of the conductive layer 6. The dielectric plate or dielectric material may include, for example, titanium oxide, barium titanium or barium nitride, or silicon nitride. As shown in FIG. 1, it includes a conductive and adhesive paste such as silver, and is used in The upper surface layer of the dielectric layer 7 holds the semiconductor wafer 2 to the dielectric layer 7. The conductive paste used will be used as the upper conductive layer 8. The semiconductive wafer 2 'provided with many circuit elements is passed through many, for example, gold The produced wiring 9 is electrically connected to the wiring pattern semiconductor wafer 2, the wiring 9 and other components are made of a resin package 10 made of a resin material and sealed on the upper side of the base 1. According to the present invention, the capacitor is Provided by the combination of the low conductive layer 6 formed on i, the upper conductive layer 8 and the intermediate dielectric layer 7 are sandwiched between two conductive elements. _This is a smart way to protect the semiconductor chip 2 from exaggeration Φ 工 柯 ^ The paper ruler Lin Caiguan_Jun (CNS) Threat (2 丨 Gx297) ----- ° 4 Binding 311100 A7 ________B7___ V. Description of the invention (5) The capacitor is arranged behind or below the semiconductor wafer 2. This feature is to reduce the size of the device and reduce production Cost advantage. Furthermore, when manufacturing the device of the present invention, the capacitors will be merged so no additional steps are needed to fix the separate capacitors to the substrate and connect this capacitor to the Fengdao ship chip. Referring again to Figure 1, above The conductive layer 8 and the semiconductor wafer 2 have flat-plate contact surfaces that are attached to each other through them. The contact surface of the conductive layer 8 has a larger area than the contact surface of the semiconductor wafer 2. Therefore, the semiconductor wafer 2 is stably and firmly supported by the conductive layer 8. According to the illustrated embodiment, as seen above, the lower conductive layer 6 is made larger than the upper conductive layer 8. More specifically, both the lower conductive layer 6 and the upper conductive layer 8 have inner surfaces that are in contact with the dielectric layer 7. The area of the inner surface of the lower conductive layer 6 is larger than that of the upper conductive layer 8. It can be easily understood that the above-mentioned capacitor capacitance value can be adjusted by changing the surface area of the low-conductive layer 6, the dielectric layer 7, and the upper conductive layer 8. According to the invention described here, it can be obviously changed that many other The method is still the same, and such a change is not considered to depart from the spirit and field of the present invention, and all obvious modifications to the technique should still be included in the scope of the patents described below. This paper uses the Chinese National Standards (CNS) A4 size (210X297 mm) 311100 f (Please read the notes on the back before filling out this page).