JPS6442158A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS6442158A
JPS6442158A JP19827687A JP19827687A JPS6442158A JP S6442158 A JPS6442158 A JP S6442158A JP 19827687 A JP19827687 A JP 19827687A JP 19827687 A JP19827687 A JP 19827687A JP S6442158 A JPS6442158 A JP S6442158A
Authority
JP
Japan
Prior art keywords
thick film
capacitor
chip
film printed
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19827687A
Other languages
Japanese (ja)
Inventor
Shigemi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19827687A priority Critical patent/JPS6442158A/en
Publication of JPS6442158A publication Critical patent/JPS6442158A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To make it possible to increase the degree of integration to reduce influence of a power noise, by mounting a capacitor for absorbing the power noise on a thick film printed wiring board and mounting a semiconductor integrated circuit chip on the capacitor. CONSTITUTION:A thick film printed wiring board is constituted by forming printed conductive patterns 12 and 13 on an insulating substrate 11 of ceramic, glass epoxy resin or the like. A plate capacitor 15 is mounted on the thick film printed board by a conductive adhesive 14 and an IC chip 17 is adhered and fixed to the plate capacitor 15 by a conductive adhesive 16. The IC chip 17 is connected to the printed conductive pattern 12 of the thick film printed wiring board by a bonding wire 18. Since the plate capacitor 15 for absorbing a power noise is provided between the IC chip 17 and the thick film printed conductive board, the space for disposing the capacitor 15 is not necessary. As a result, it is possible to increase the degree of integration.
JP19827687A 1987-08-10 1987-08-10 Hybrid integrated circuit device Pending JPS6442158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19827687A JPS6442158A (en) 1987-08-10 1987-08-10 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19827687A JPS6442158A (en) 1987-08-10 1987-08-10 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6442158A true JPS6442158A (en) 1989-02-14

Family

ID=16388432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19827687A Pending JPS6442158A (en) 1987-08-10 1987-08-10 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6442158A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0399661A2 (en) * 1989-05-22 1990-11-28 Advanced Micro Devices, Inc. Integrated circuit lead assembly structure
FR2724054A1 (en) * 1994-06-09 1996-03-01 Samsung Electronics Co Ltd SEMICONDUCTOR PACKAGE MOUNTING STRUCTURE
KR20000071262A (en) * 1999-01-18 2000-11-25 사토 게니치로 Electrical device
KR100764682B1 (en) * 2006-02-14 2007-10-08 인티그런트 테크놀로지즈(주) Ic chip and package

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0399661A2 (en) * 1989-05-22 1990-11-28 Advanced Micro Devices, Inc. Integrated circuit lead assembly structure
EP0399661B1 (en) * 1989-05-22 1998-09-16 Advanced Micro Devices, Inc. Integrated circuit lead assembly structure
FR2724054A1 (en) * 1994-06-09 1996-03-01 Samsung Electronics Co Ltd SEMICONDUCTOR PACKAGE MOUNTING STRUCTURE
KR20000071262A (en) * 1999-01-18 2000-11-25 사토 게니치로 Electrical device
KR100764682B1 (en) * 2006-02-14 2007-10-08 인티그런트 테크놀로지즈(주) Ic chip and package

Similar Documents

Publication Publication Date Title
CA2171458A1 (en) Multi-chip module
EP0350588A3 (en) Electronic package with improved heat sink
EP0996154A4 (en) Semiconductor device and method for manufacturing the same, circuit substrate, and electronic device
EP0841694A4 (en) Semiconductor package with multilayered circuit and semiconductor device
GB2312786A (en) High performance integrated circuit package
ATE167319T1 (en) BASE FILM FOR CHIP CARD
ES464959A1 (en) Integrated circuit package
WO2001069680A3 (en) Electronic module having a three dimensional array of carrier-mounted integrated circuit packages
CA2108868A1 (en) Printed circuit board with electric elements mounted thereon
EP0381383A3 (en) Semiconductor device having insulating substrate adhered to conductive substrate
EP1150355A4 (en) Integrated circuit chip, integrated circuit, printed-circuit board and electronic device
TW365035B (en) Semiconductor device package having a board, manufacturing method thereof and stack package using the same
CA2056781A1 (en) Multichip module
TW366574B (en) A semiconductor device package and method semiconductor package having multilayer of chip stacking connected to a ceramic package of printed circuit boards
CA2095609A1 (en) Leadless pad array chip carrier
SE9202077D0 (en) COMPONENT MODULE
GB2341003A (en) Integrated passive components and package with posts
JPS56161696A (en) Board
JPS6442158A (en) Hybrid integrated circuit device
JPS57181144A (en) Semiconductor device
GB2202994B (en) Circuit assembly, e.g. for an electronic timepiece
JPS645894A (en) Thin-type mounting type semiconductor device
SE8703913D0 (en) DEVICE FOR ELECTRICAL RELAXATION OF INTEGRATED CIRCUITS
JPS647688A (en) Mounting method for film carrier
JPH0358465A (en) Resin sealed type semiconductor device