KR100356928B1 - A circuit board having protection against electrostatic discharge - Google Patents

Abstract

The present invention describes a circuit board having protection against electrostatic discharge. The board includes a plurality of interconnect traces and a conductive ground plate formed on the substrate, with a gap formed between the interconnect traces and the ground plate. The resistive electrostatic discharge protection material is arranged to bridge the gap between the ground plate and the interconnect trace, so that the electrostatic discharge protection material electrically insulates the interconnect trace from the ground plate at a voltage less than the predetermined limit voltage, At higher voltages, an electrical connection is established between the conductive plate and the interconnect trace. A method of manufacturing a circuit board includes forming an interconnect trace and a ground plate, with a gap formed between the ground plate and the interconnect trace. Resistive electrostatic discharge protection material is present in the gap between the ground plate and the trace for protection against electrostatic discharge. The package includes the circuit board described above and the process of manufacturing such a package is also described herein.

Description

Circuit board with electrostatic discharge protection {A CIRCUIT BOARD HAVING PROTECTION AGAINST ELECTROSTATIC DISCHARGE}

The present invention generally relates to circuit boards for use in packaged integrated circuits. In particular, this relates to a circuit board having electrostatic discharge (ESD) protection and in the case of electrostatic discharge (ESD) can reduce the possibility of integrated circuit disconnection.

Naturally occurring and inevitable ESD is known to induce high voltage and high current surges that can exceed thousands of volts. In the absence of any integrated circuit protection devices, current surges or overvoltages may pass through the integrated circuit, resulting in hardware losses such as integrated circuit breaks or electronic failures, such as memory loss or loss of transmission data. Integrated circuits fabricated using metal oxide semiconductor (MOS) or similar techniques may be considered as an example of integrated circuits that become unavailable by ESD. As is well known to those skilled in the art, metal oxide semiconductor (MOS) devices generally use a gate structure, which includes an insulating thin film typically formed from silicon dioxide. Under overvoltage, which may be due to ESD, the thin film gate insulating layer may have dielectric breakdown damage, for example, at about 10 volt potential for a 0.35 micron process, such that the gate is broken and the entire device is inoperable. do. Because integrated circuit processing technology is being moved to smaller sizes to operate at lower current densities, the energy required to generate such damage is even more reduced.

In general, in an effort to protect integrated circuits against overvoltages, particularly overvoltages by ESD, manufacturers have integrated various circuit protection devices into chip designs. For example, a conventional integrated circuit package design integrated with a circuit protection device is disclosed in US Pat. No. 4,928,199 by Diaz et al. In this design, the integrated circuit includes a die connected to a ground voltage and protected by a metallic cavity cover, which acts as a ground plate. This circuit protection device, for example a glass layer, is disposed on the inner surface of the cavity cover in contact with the bonding wires to connect the bonding pads on the die to the leads on the lead frame.

In the normal operating mode, the circuit protection device has a high resistance. However, in response to a short-circuit voltage surge, the circuit protection device in the relatively short short-circuit period is switched from the high resistance state to the low resistance state. Immediately after the short-circuit surge ends, the circuit protection returns to its original high resistance state.

In the conventional integrated circuit package design described above, the voltage surge generated from the external circuit and input into the integrated circuit package passes through a bonding wire connected to the circuit protection device. In response to the voltage surge, the circuit protection device transitions from a high resistance state to a low resistance state and directs the voltage surge to the ground plate cavity cover. In this way, the circuit protection device protects the die from disconnection that may be generated from voltage surges generated in external circuits. Although this design protects the die from voltage surges, this presents several disadvantages. Accordingly, there is a need for improved integrated circuit package designs that provide adequate ESD protection using effective methods for manufacturing package designs and the like.

1 is a plan view of a packaged integrated circuit according to one embodiment of the present invention, which is integrated with an ESD protective material.

FIG. 2 is a side cross-sectional view of the cross section of the package shown in FIG. 1. FIG.

3 is a flowchart of a process of packaging an integrated circuit integrated with an ESD protection material according to an embodiment of the present invention.

FIG. 4 is a flow chart illustrating one implementation of step 110, as described in FIG. 3, showing another method of providing an ESD protective material within the gaps shown in FIGS.

5 is a plan view of a packaged integrated circuit according to another embodiment of the present invention integrated with an ESD protective material.

Explanation of symbols on the main parts of the drawing

20: packaged integrated circuit 26: interconnect metal trace

32 interconnect wire 34 lead

36: PCB base substrate 38: PCB

According to the present invention, a circuit board having protection against electrostatic discharge is described in order to attain a purpose different from the above object. In a first embodiment of the invention, a circuit board includes a conductive ground plate formed on the substrate and a plurality of interconnect traces, with a gap formed between the interconnect traces and the ground plate. The resistive electrostatic discharge protection material is arranged to bridge the gap between the ground plate and the mutual trace. The electrostatic discharge protection material electrically insulates the ground plate and the interconnect trace at a voltage below a predetermined limit voltage, and establishes an electrical connection between the interconnect trace and the conductive plate at a voltage above the limit voltage.

In another embodiment of the present invention, a packaged semiconductor device including the circuit board described above is also described. A packaged semiconductor device includes a die attached to a circuit board, a plurality of bonding wires for electrically connecting the bond pads on the die to an associated trace, a lead frame, at least a portion of the die, the circuit board, the bonding wire, and the lead frame. It includes a capsule material for encapsulating.

In another embodiment of the present invention, a method for manufacturing a circuit board having electrostatic discharge protection will also be described. The method includes forming an interconnect trace and a ground plate on the substrate board, such that a gap is formed between the ground plate and the interconnect trace. A resistive electrostatic discharge protective material is disposed in the gap between the ground plate and the trace. Electrostatic discharge protection electrically insulates the ground plate and the trace at voltages below a predetermined threshold voltage, and establishes an electrical connection between the trace and the conductive plate at voltages above the threshold voltage. In one embodiment, disposing the electrostatic discharge protective material in the gap between the ground plate and the trace includes disposing a polymer solution of the electrostatic discharge protective material in the gap and curing the polymer solution in the gap.

In order to form the package described above, the method also includes mounting a die having a plurality of bond pads on the substrate board, and electrically connecting the die to an appropriate trace on the substrate board using a first set of bonding wires. It may further comprise the step of. Each bonding wire has a first end coupled with an associated bonding pad and a second end coupled with an associated interconnect trace. Several selected ones of the interconnect traces are electrically connected to the associated leads of the lead frame. A portion of the die, bonding wire and leads are encapsulated to provide a protective package with portions of the leads exposed, thereby facilitating electrical connection of the die with external circuitry.

These and other advantages of the present invention will become apparent upon studying the following detailed description and various features of the drawings.

The present invention relates to printed circuit boards (PCBs), which are integrated with an electrostatic discharge (ESD) protection device to protect the integrated circuit from voltage surges that may be generated by electrostatic discharge (ESD). In addition, a process for manufacturing an integrated circuit package including new printed circuit boards (PCBs) is also described. In the following description, numerous specific details are provided for the overall understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced otherwise than with these specific details. In addition, well-known processes will not be described for the sake of clarity.

1, an embodiment of a packaged integrated circuit design including a PCB integrated with an ESD protection device in accordance with the present invention is shown. The packaged integrated circuit 20 includes a PCB backing substrate 36 coupled with a lead frame. The PCB 38, which will be described in detail later, is connected to the lead 34 by a set of interconnect wires 32, ie, the interconnect wire 32 is connected at one end to a set of interconnect metal traces ( And connected to the associated lead 34 or corresponding lead at the other end. Next, the leads 34 are connected to typical external circuits (not shown). As is known to those skilled in the art, the package 20 is arranged to encapsulate a portion 34 of the device, interconnect wire 32 and leads on the PCB 38.

In one embodiment of the present invention, the PCB 38 has a network of conductive interconnect metallic traces 26 disposed outside of the discharge plate 30. The interconnect metallic traces 26 are separated from the discharge plate 30 by the gap 44. As shown in FIG. 1, the discharge plate 30 is connected with one of the interconnect metallic traces 26, which is via one of the interconnect wires 32 and one of the leads 34. It is connected to the ground voltage 50. The ESD protection material 28 substantially fills or covers the gap 44, which may extend the length of the discharge plate 30. The ESD protection material 28 in the gap 44 is in physical contact with both the interconnect metal trace 26 and the discharge plate 30. In general, the die 22 including the current sensing circuit may be disposed in the opening of the discharge plate 30 or in any suitable position on the substrate 36. The die 22 typically includes a plurality of bond pads 46, which are connected to the corresponding interconnect metal traces 26 via a set of bonding wires 24.

2, a cross-sectional view of package 20 is shown to better describe the various components in one embodiment of the present invention. Lead frame 42 includes a number of leads 34. PCB 38 is mounted to a suitable support, such as lead frame paddle 40. Interconnect wire 32, interconnect metal traces 26 and bonding wires 24, bond pads 46, ESD protection material 28, gaps 44 and dies 22 are as shown in FIG. It is shown in substantially the same structure. In some embodiments, the gap 44 is shown as a channel region or cut between the interconnect metal traces 26 and the discharge plate 30. The ESD protection material 28 substantially fills the gap 44 to form a good electrical connection with both the interconnect metal trace 26 and the discharge plate 30.

When a voltage surge exceeding or equaling a predetermined threshold voltage of the ESD protective material 28 is input from the specific lead 34 into the integrated circuit package 20, it is induced in the associated trace 26 on the PCB 38. . In response to this voltage surge, the ESD protection material 28, which is electrically connected to the trace 26, generally transitions from a high resistance state to a low resistance state. The ESD protection material 28 in the low resistance state induces a voltage surge to the discharge plate 30, causing the voltage surge to shunt to ground. In this way, the ESD protection material 28 protects the sensing circuit components of the die 22 from the possibility of disconnection by ESD. As soon as the short-circuit voltage surge ends, the ESD protection material 28 returns to the normal state of high resistance.

5, although the package 20 shows a single chip module assembly, as shown in FIGS. 1 and 2, the present invention is not limited to a single die configuration. More specifically, the single die configuration described above is used as an example to illustrate the simplicity of the packaged integrated circuit design according to the present invention and the advantages over the prior art. In fact, the invention described above applies equally to multichip module assemblies.

Similarly, the PCB 38 as described in the present invention is not limited to only packaged integrated circuits. It may also be effectively integrated with other electrical devices, such as popular PCBs with various electrical components. PCB 38 is generally disposed on substrate board 36, which is a technique known to those skilled in the art. Leads 34, wires 32 and bonding wires 24, bond pads 46, interconnect metal traces 26, discharge plates 30 (above, all shown in FIG. 1) and lead frames ( 42 and lead frame paddle 40 (both shown in FIG. 2) may be constructed from materials known to those skilled in the art. Die 22 generally relates to any electrical device that may include a chip, an integrated circuit, or a circuit that is sensitive to voltage surges.

As shown in FIG. 1, the discharge plate 30 may serve as a grounded conductive plate. However, in other embodiments of the present invention, various other devices may be used as the grounded conductive plate. Examples of such devices include metal traces of any geometry, such as die attach regions, conductive plates, or substantially ring shaped metal traces. It will be apparent to one skilled in the art that the present invention is also not limited to a single grounded conductive plate, and that the present invention may include multiple plates. Also, like the discharge plate 30, connecting the ground voltage to the conductive plate is shown in FIG. 1, that is, via one of the interconnect metallic traces 26, the wires 32 and the leads 34. It is not limited to such a configuration. Of course, the connection of such a ground voltage can be performed by any method known to those skilled in the art.

The gap 44 is generally defined by the space between the interconnect metallic trace and the conductive plate. It may have a variety of different shapes and sizes. Some gap shaped examples include grooved, concave or channelized regions on simply empty or metallized spaces on a substrate. To illustrate, FIG. 2 shows one embodiment of the present invention, where the gap may be a channel region or cut between the interconnect metallic trace 26 and the discharge plate 30. Although the width of the gap is any suitable size, it is desirable to have a gap that does not exceed the gap depth. The size of the gap depth may generally be in an area between about 0.5 mils and about 5 mils. The size of the gap width may generally be in the range of about 0.25 to about 5 mils, preferably in the range of 0.5 to about 1.5 mils, and more preferably about 1 mils.

ESD protection material 28 includes any suitable resistive current sensing material capable of sufficiently inducing electricity at a predetermined threshold voltage. However, ESD protective material 28 preferably comprises a polymer, which may be used in the form of a solid strip or solution in the present invention. An example is a polymer strip called Surg X ^™ from Surg X of Fremot, California.

Sufficient amount of ESD protection material 18 in any form, such as a polymer solution or strip, is placed between the gaps so that a solid connection is established between the interconnect metal traces and the conductive plate and shunts it at a predetermined threshold voltage. ) Effectively induces a voltage surge to ground. However, in an embodiment of the present invention, where the empty space on the substrate acts as a gap, it is desirable to have a polymer strip that adheres to the gap, e.g. backing). In addition, in the embodiment of the present invention, the grooved, channeled or concave region acts as a gap, which preferably uses a polymer solution by the method described above.

The threshold voltage required to convert a normal resistive ESD protection material 28 into a substantially conductive material may vary greatly depending on the use of a particular system. For example, threshold voltages in the range of about 10 to about 500 volts will be used in most conventional packaging devices. Threshold voltages in the range of about 10 to about 100 volts are preferred, and more preferably in the range of about 10 to about 50 volts.

3, a method 100 for packaging an integrated circuit using a packaging structure integrated with an ESD protective material according to the present invention will be described. In step 102, any preceding manufacturing steps necessary for manufacturing the substrate for metallization, i.e., pre-heating the substrate, are performed. In step 104, metallization is formed on the substrate to form a network of interconnect traces and discharge plates. In one embodiment of the invention, the network of traces may be arranged in such a way that the die attach region is formed near or near the center of the substrate. The formation of the traces and discharge plates is carried out by conventional forming methods known to those skilled in the art, and in one embodiment include printing the metallization directly on the substrate. In one embodiment, the die attach region is simply an empty region near the center of the substrate.

In step 106, the gap between the trace and the discharge plate is formed by any known method. In one embodiment, the gap is formed by cutting the metallization after the metallization is printed on the substrate. Cutting of the metallization may be performed by any method known to those skilled in the art, and in one embodiment of the present invention, this includes etching the metallization by conventional lithographic techniques. In another embodiment, the traces and discharge plates are printed in appropriate locations in step 104 to be separated by a gap. In such an arrangement, a separation gap forming step is not required. In another embodiment, steps 104 and 106 of the present invention may be performed by etching the conductive layer of the substrate board, for example metallization, to form a network of interconnect traces, discharge plates, and gaps. The substrate board in this embodiment may include a laminated structure.

In step 108, the ESD protection material is placed in the gap. This is done by various methods used by those skilled in the art. For example, in one embodiment, an ESD protection tape is applied to the gap between the interconnect metallic trace and the discharge plate. Alternatively, the ESD protection material on the gap may be placed by screen printing or change printing or by dispensing the ESD protection material in solution form through a nozzle on the gap. Different forms of ESD protective materials having different gap shapes are described in detail above. In an embodiment of the invention, the polymer solution is preferred as an ESD protective material, and the gap size may ultimately define the amount of ESD protective material that is present or disposed. As already explained, the amount of ESD protective material provided in the gap is sufficient to facilitate reliable solid contact between the interconnect metallic trace and the conductive plate and to sufficiently induce a voltage surge above or below a predetermined limit voltage. In this way, in the above, the width of the plurality of workable gaps has been described in detail. It has become clear that the discharge voltage for a particular ESD material can be controlled fairly accurately by controlling the gap width, which is easy to implement using conventional instruments.

In step 110, the package is assembled according to conventional steps known to those skilled in the art. These steps include, for example, mounting one or more dies with multiple bond pads on associated die attach regions, and at one end the associated bonding pads of the die and the associated interconnect metal traces at the other end with the bonding wire set. Mounting a PCB on a lead frame paddle, connecting an interconnect wire set to an associated interconnect metal trace at one end and an associated lead on the lead frame at the other end, and a portion of the package, e.g. Encapsulating elements on the PCB, portions of interconnect wires, leads. In one embodiment, most of these steps may be performed with a Multi Chip Module Die Attach System, such as Kulicke & Soffa Model 6990 from Kulicke & Soffa of Willow Grove, PA. Process 100 ends at step 112, which generally includes past assembly steps known to those skilled in the art.

4, this is a variation of step 110 in one embodiment of the present invention. Step 110 shown in FIG. 3 relates to providing an ESD protective material in the gap. In FIG. 4, step 110 of the present invention begins at step 120. In step 122, an ESD protective material in the form of a polymer solution is disposed in the gap between the interconnect metal trace and the conductive plate. In step 124, the polymer solution is cured, which generally includes heat treatment of the polymer material. The curing temperature depends on whether the polymer solution is a low temperature or high temperature polymer. Curing the polymer solution is generally carried out at a temperature between about 100 and about 500 ° C., preferably between about 100 and about 200 ° C., and more preferably at a temperature between about 100 and about 150 ° C. Is performed. In step 126, step 110 ends, and one embodiment of the process of the present invention may continue as described in FIG.

The present invention provides an improved integrated circuit package design that provides adequate ESD protection using effective methods for manufacturing package designs and the like.

Although the invention has been described in some preferred embodiments, there may be variations, substitutions, and equivalents within the scope of the spirit of the invention. There are also many other ways of implementing the methods and apparatus of the present invention, for example the protection of the present invention against ESD will be effective in other applications where there are other sources of voltage surges. Therefore, the following claims are intended to cover such modifications, substitutions, and equivalents within the spirit and scope of the invention.

Claims (5)

A circuit board having protection against electrostatic discharge (ESD), A substrate supporting the die, A plurality of interconnect traces formed on the substrate, A conductive ground plate formed on the substrate and substantially coplanar with the interconnect trace, the conductive ground plate arranged to form a gap between the interconnect trace and the ground plate; A resistive electrostatic discharge (ESD) protective material disposed to bridge the gap between the ground plate and the interconnect trace on the same plane without covering the interconnect trace or the conductive ground plate, The electrostatic discharge protection material electrically insulates the ground plate and the interconnect trace at a voltage below a predetermined threshold voltage, and at a voltage above the threshold voltage, the electrical connection is established between the conductive plate and the interconnect trace. A circuit board comprising an electrostatic discharge protection material. 2. The circuit board of claim 1, further comprising a die attach region suitable for connection to a ground voltage, wherein the ESD protection material is between the trace and the die attach region. 2. The circuit board of claim 1, further comprising a die attach region on the substrate, wherein the conductive plate obtains a substantially ring-shaped metal trace around the die attach region. The circuit board of claim 1, wherein the ESD protection material is a strip-shaped polymer tape. 2. The circuit board of claim 1, wherein the predetermined threshold voltage is in a range of about 10 to about 500 volts.