JP2583242Y2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2583242Y2 JP2583242Y2 JP1992013227U JP1322792U JP2583242Y2 JP 2583242 Y2 JP2583242 Y2 JP 2583242Y2 JP 1992013227 U JP1992013227 U JP 1992013227U JP 1322792 U JP1322792 U JP 1322792U JP 2583242 Y2 JP2583242 Y2 JP 2583242Y2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- hole
- semiconductor element
- semiconductor device
- mounting area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本考案は、半導体素子の搭載領域
内や封止材の塗布領域内にスルーホールが設けられた半
導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a through hole is provided in a mounting region of a semiconductor element or a coating region of a sealing material.
【０００２】[0002]
【従来の技術】電子機器の小型化や薄型化を図る観点か
ら、基板上にベアチップ等の半導体素子を直接搭載した
表面実装型の半導体装置がある。これを図２に基づいて
説明する。この半導体装置１は、基板１１上の半導体素
子１２を搭載する位置に搭載領域Ｓが設けられ、この搭
載領域Ｓ上にダイボンド材１２ａを介してベアチップ状
の半導体素子１２が搭載されている。搭載された半導体
素子１２は、ボンディングワイヤー１５により配線パタ
ーン１７のパッド１７ａと接続されており、この半導体
素子１２とボンディングワイヤー１５とを保護するため
に、熱硬化性樹脂等から成る封止材１３がこの半導体素
子１２とボンディングワイヤー１５とを封止する状態に
塗布されている。また、基板１１の封止材１３の塗布領
域Ｒより外側には配線パターン１７と導通状態のスルー
ホール１４が設けられており、このスルーホール１４を
介して基板１１の両面に半導体素子１２やチップ部品
（図示せず）等を接続することで、実装密度の向上を図
っている。2. Description of the Related Art From the viewpoint of reducing the size and thickness of electronic devices, there is a surface mount type semiconductor device in which a semiconductor element such as a bare chip is directly mounted on a substrate. This will be described with reference to FIG. In the semiconductor device 1, a mounting area S is provided at a position where the semiconductor element 12 is mounted on the substrate 11, and the bare chip semiconductor element 12 is mounted on the mounting area S via a die bonding material 12a. The mounted semiconductor element 12 is connected to the pad 17 a of the wiring pattern 17 by a bonding wire 15. To protect the semiconductor element 12 and the bonding wire 15, a sealing material 13 made of a thermosetting resin or the like is used. Is applied to seal the semiconductor element 12 and the bonding wire 15. A through hole 14 is provided outside the coating region R of the sealing material 13 of the substrate 11 so as to be electrically connected to the wiring pattern 17. The semiconductor element 12 and the chip are provided on both surfaces of the substrate 11 through the through hole 14. By connecting components (not shown) and the like, the mounting density is improved.
【０００３】[0003]
【考案が解決しようとする課題】しかしながら、この半
導体装置には次のような問題がある。すなわち、基板上
の封止材の塗布領域内にスルーホールを設けた場合、塗
布した封止材がこのスルーホールを通り、基板の裏面側
に漏れてしまう。また、半導体素子の搭載領域内にスル
ーホールを設けた場合には、ダイボンド材がスルーホー
ルから基板の裏面側に漏れてしまう。このため、基板上
の封止材の塗布領域および半導体素子の搭載領域にはス
ルーホールを設置することができない、いわゆる禁止領
域となっている。したがって、この禁止領域以外にスル
ーホールを設けなければならず、配線パターンの設計
上、大きな制約を受けることになる。とくに、半導体素
子の実装面積が大きい場合には、部品の実装密度の低下
を招き、基板の縮小化が困難となる。よって、本考案は
スルーホールが設けられた基板において、実装密度の向
上が図れる半導体装置を提供することを目的とする。However, this semiconductor device has the following problems. That is, when a through-hole is provided in the application region of the sealing material on the substrate, the applied sealing material leaks to the back surface of the substrate through the through-hole. Further, when a through hole is provided in the mounting region of the semiconductor element, the die bonding material leaks from the through hole to the back surface side of the substrate. For this reason, a through-hole cannot be provided in a region where the sealing material is applied on the substrate and a region where the semiconductor element is mounted, which is a so-called prohibited region. Therefore, a through hole must be provided in a region other than the forbidden region, which greatly restricts the design of the wiring pattern. In particular, when the mounting area of the semiconductor element is large, the mounting density of components is reduced, and it is difficult to reduce the size of the substrate. Therefore, an object of the present invention is to provide a semiconductor device capable of improving the mounting density on a substrate provided with through holes.
【０００４】[0004]
【課題を解決するための手段】本考案は上記の課題を解
決するために成された半導体装置である。すなわち、本
考案の半導体装置は、配線パターンが設けられていると
ともに、スルーホールが設けられている基板と、基板に
設けられた搭載領域に対応して搭載される半導体素子
と、基板のスルーホール内に埋め込まれるとともに搭載
領域に一様に塗布される樹脂と、半導体素子と基板の配
線パターンとを接続するボンディングワイヤーと、半導
体素子とボンディングワイヤーとを封止するため、基板
の一方面に塗布される封止材とを備えており、基板のス
ルーホールが搭載領域およびその周辺において配線パタ
ーンと導通し基板を貫通するよう設けられるとともに、
半導体素子が樹脂の表面にダイボンド材を介して搭載さ
れるものである。 SUMMARY OF THE INVENTION The present invention is a semiconductor device made to solve the above-mentioned problems. That is, the book
The invented semiconductor device is provided with a wiring pattern.
In both cases, the board with the through hole and the board
Semiconductor element mounted corresponding to the mounting area provided
And embedded in the through hole of the board and mounted
Resin that is uniformly applied to the area, and the arrangement of the semiconductor element and the substrate.
Bonding wire to connect the wire pattern
To seal the body element and the bonding wire
And a sealing material applied to one side of the substrate.
The through hole has a wiring pattern in and around the mounting area.
And is provided to penetrate through the substrate
A semiconductor element is mounted on the resin surface via a die bond material.
It is what is done.
【０００５】[0005]
【作用】本考案では、基板の一方面に封止材を塗布する
ことで、基板に搭載した半導体素子や配線パターンと接
続したボンディングワイヤーを封止する場合において、
基板における封止材の塗布領域にスルーホールが設けら
れていても、そのスルーホール内に樹脂が埋め込まれて
いることから、基板の一方面に封止材を塗布してもその
封止材がスルーホールを通って基板の他方面側に漏れる
てしまうことを防ぐことができる。また、半導体素子の
搭載領域にスルーホールが設けられていても、そのスル
ーホール内に樹脂が埋め込まれていることから、搭載領
域にダイボンド材を塗布してもそのダイボンド材がスル
ーホールを通って基板の他方面側に漏れてしまうことを
防ぐことができる。しかも、搭載領域に一様に樹脂が塗
布されていることから、搭載領域にスルーホールが設け
られていてもその搭載領域の表面を平滑にすることがで
き、ダイボンド材を介して搭載する半導体素子の密着性
を向上させることができる。 In the present invention, a sealing material is applied to one surface of a substrate.
This allows contact with the semiconductor elements and wiring patterns mounted on the substrate.
When sealing the continuous bonding wire,
A through hole is provided in the encapsulant application area on the substrate.
Resin is embedded in the through hole
Therefore, even if the sealing material is applied to one side of the substrate,
Sealant leaks through the through hole to the other side of the board
Can be prevented. In addition, semiconductor devices
Even if a through hole is provided in the mounting area,
-Since the resin is embedded in the hole,
Even if the die bond material is applied to the area,
Over the other side of the substrate through the hole
Can be prevented. In addition, resin is uniformly applied to the mounting area.
Since it is clothed, a through hole is provided in the mounting area
The surface of the mounting area can be smoothed.
Of semiconductor elements mounted via die bonding material
Can be improved.
【０００６】[0006]
【実施例】以下に本考案の半導体装置の実施例を図に基
づいて説明する。図１は本考案の半導体装置を説明する
断面図である。この半導体装置１は、主に配線パターン
１７が形成された基板１１と、この基板１１上の搭載領
域Ｓに搭載され、かつボンディングワイヤー１５にて配
線パターン１７と接続された半導体素子１２と、基板１
１上で半導体素子１２とボンディングワイヤー１５とを
封止する状態に塗布された封止材１３とから成るもので
ある。なお、本実施例において、基板１１上の半導体素
子１２が搭載された一部分を用いて説明するが、他の半
導体素子１２が搭載された部分についても同様である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention. FIG. 1 is a sectional view illustrating the semiconductor device of the present invention. The semiconductor device 1 includes a substrate 11 on which a wiring pattern 17 is mainly formed, a semiconductor element 12 mounted on a mounting area S on the substrate 11 and connected to the wiring pattern 17 by a bonding wire 15, 1
1 comprises a sealing material 13 applied so as to seal the semiconductor element 12 and the bonding wire 15. In the present embodiment, a description will be made using a part of the substrate 11 on which the semiconductor element 12 is mounted, but the same applies to a part on which another semiconductor element 12 is mounted.
【０００７】半導体素子１２は、基板１１上の搭載領域
Ｓに塗布された絶縁性の高いダイボンド材１２ａを介し
て接続されている。したがって、半導体素子１２の裏面
を用いた基板１１との電気的な接地は成されない。基板
１１上で封止材１３を塗布する塗布領域Ｒ内には、配線
パターン１７と導通状態にあるスルーホール１４が設け
られている。このスルーホール１４は半導体素子１２の
搭載領域Ｓ内にも設けられており、各スルーホール１４
のホール１４ａ内にはレジスト材等の樹脂１６が埋め込
まれている。[0007] The semiconductor element 12 is connected via a highly insulative die bond material 12a applied to the mounting area S on the substrate 11. Therefore, electrical grounding with the substrate 11 using the back surface of the semiconductor element 12 is not performed. In a coating region R where the sealing material 13 is coated on the substrate 11, a through hole 14 that is in a conductive state with the wiring pattern 17 is provided. The through holes 14 are also provided in the mounting area S of the semiconductor element 12, and each through hole 14
A resin 16 such as a resist material is embedded in the hole 14a.
【０００８】これにより、基板１１上で塗布領域Ｒ内に
封止材１３を塗布した場合、この封止材１３がスルーホ
ール１４のホール１４ａを通って基板１１の裏面側に漏
れることがない。さらに、基板１１上の搭載領域Ｓに塗
布したダイボンド材１２ａがスルーホール１４のホール
１４ａを通って基板１１の裏面側に漏れることがない。
また、樹脂１６を搭載領域Ｓの全体を覆う状態に塗布す
れば、この搭載領域Ｓの表面が平滑となり、ダイボンド
材１２ａによる半導体素子１２と基板１１との密着性が
向上する。Accordingly, when the sealing material 13 is applied in the application region R on the substrate 11, the sealing material 13 does not leak to the back surface of the substrate 11 through the holes 14 a of the through holes 14. Further, the die bonding material 12a applied to the mounting area S on the substrate 11 does not leak to the back surface side of the substrate 11 through the holes 14a of the through holes 14.
If the resin 16 is applied so as to cover the entire mounting area S, the surface of the mounting area S becomes smooth, and the adhesion between the semiconductor element 12 and the substrate 11 by the die bonding material 12a is improved.
【０００９】次に、この半導体装置１の製造方法につい
て簡単に説明する。先ず、エポキシ基板等の基板１１に
所定の配線パターン１７を印刷法等を用いて形成し、必
要な箇所にスルーホール１４を設ける。なお、このスル
ーホール１４の設置位置に関して特に制限はない。Next, a method of manufacturing the semiconductor device 1 will be briefly described. First, a predetermined wiring pattern 17 is formed on a substrate 11 such as an epoxy substrate by using a printing method or the like, and through holes 14 are provided at necessary places. There is no particular limitation on the installation position of the through hole 14.
【００１０】次いで、基板１１上の封止材１３の塗布領
域Ｒにレジスト材等の樹脂１６を塗布する。そして、ボ
ンディングワイヤー１５を接続するためのパッド１７ａ
上に塗布された樹脂１６を除去する。Next, a resin 16 such as a resist material is applied to an application region R of the sealing material 13 on the substrate 11. Then, a pad 17a for connecting the bonding wire 15
The resin 16 applied above is removed.
【００１１】次に、樹脂１６が塗布された状態の搭載領
域Ｓに絶縁ペースト等のダイボンド材１２ａを塗布す
る。このとき、搭載領域Ｓ内にスルーホール１４が設け
られていても、そのホール１４ａ内が樹脂１６にて埋め
込まれているため、基板１１の裏面側に樹脂１６が漏れ
ることはない。そして、このダイボンド材１２ａにより
ベアチップ状の半導体素子１２を搭載領域Ｓ上に接着す
る。Next, a die bonding material 12a such as an insulating paste is applied to the mounting area S where the resin 16 has been applied. At this time, even if the through hole 14 is provided in the mounting region S, the resin 16 does not leak to the back surface side of the substrate 11 because the hole 14a is filled with the resin 16. Then, the bare chip-shaped semiconductor element 12 is bonded onto the mounting region S by the die bonding material 12a.
【００１２】次に、半導体素子１２と配線パターン１７
のパッド１７ａとを熱圧着法等によりボンディングワイ
ヤー１５を用いて接続する。最後に、基板１１上の塗布
領域Ｒにエポキシ樹脂等の熱硬化性樹脂から成る封止材
１３を滴下法等により塗布し、ベアチップ状の半導体素
子１２とボンディングワイヤー１５を保護する。この塗
布の際、塗布領域Ｒ内に設けられたスルーホール１４の
ホール１４ａ内にも前述の樹脂１６が埋め込まれている
ため、封止材１３が基板１１の裏面側に漏れることはな
い。なお、基板１１の裏面に回路構成に応じたチップ部
品（図示せず）を接続することにより、両面実装型の半
導体装置１となる。Next, the semiconductor element 12 and the wiring pattern 17
Is connected to the pad 17a using a bonding wire 15 by a thermocompression bonding method or the like. Finally, a sealing material 13 made of a thermosetting resin such as an epoxy resin is applied to the application region R on the substrate 11 by a dropping method or the like to protect the bare chip-shaped semiconductor element 12 and the bonding wires 15. At the time of this application, since the above-described resin 16 is also embedded in the hole 14 a of the through hole 14 provided in the application region R, the sealing material 13 does not leak to the back surface side of the substrate 11. By connecting a chip component (not shown) corresponding to the circuit configuration to the back surface of the substrate 11, the semiconductor device 1 is a double-sided mounting type semiconductor device.
【００１３】このような方法により製造した半導体装置
１は、従来スルーホール１４の設置禁止領域であった塗
布領域Ｒ内にスルーホール１４を設けることが可能とな
る。したがって、配線パターン１７やスルーホール１４
のレイアウト設計を自由に行うことができ、半導体装置
１の基板面積を従来の基板面積と比べて約６０％程度に
することが可能となる。In the semiconductor device 1 manufactured by such a method, the through-hole 14 can be provided in the coating region R, which is a region where the installation of the through-hole 14 is conventionally prohibited. Therefore, the wiring pattern 17 and the through hole 14
Can be freely designed, and the substrate area of the semiconductor device 1 can be reduced to about 60% of the conventional substrate area.
【００１４】[0014]
【考案の効果】以上説明したように、本考案の半導体装
置によれば次のような効果がある。すなわち、封止材の
塗布領域内にスルーホールを設けることが可能となるた
め、半導体素子やチップ部品等を実装する基板の実装密
度の大幅な向上と、基板の縮小化を図ることが可能とな
る。これにより、半導体素子の搭載領域内にもスルーホ
ールを設けることができる。したがって、実装面積の大
きい半導体素子を用いた場合において、本考案はとくに
有効である。As described above, the semiconductor device of the present invention has the following effects. That is, through holes can be provided in the application region of the sealing material, so that the mounting density of a substrate on which semiconductor elements, chip components, and the like are mounted can be significantly improved, and the substrate can be reduced in size. Become. Thereby, a through hole can be provided also in the mounting region of the semiconductor element. Therefore, the present invention is particularly effective when a semiconductor element having a large mounting area is used.
【図１】本考案の半導体装置を説明する断面図である。FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.
【図２】従来の半導体装置を説明する断面図である。FIG. 2 is a cross-sectional view illustrating a conventional semiconductor device.
１ 半導体装置 １１ 基板 １２ 半導体素子 １２ａ ダイボンド材 １３ 封止材 １４ スルーホール １４ａ ホール １５ ボンディングワイ
ヤー １６ 樹脂 １７ 配線パターン １７ａ パッドDESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Substrate 12 Semiconductor element 12a Die bond material 13 Sealing material 14 Through hole 14a Hole 15 Bonding wire 16 Resin 17 Wiring pattern 17a Pad
Claims (1)
に、スルーホールが設けられている基板と、 前記基板に設けられた搭載領域に対応して搭載される半
導体素子と、 前記基板のスルーホール内に埋め込まれるとともに、前
記搭載領域に一様に塗布される樹脂と、 前記半導体素子と前記基板の配線パターンとを接続する
ボンディングワイヤーと、 前記半導体素子と前記ボンディングワイヤーとを封止す
るため、前記基板の一方面に塗布される封止材とを備え
ており、 前記基板のスルーホールは前記搭載領域およびその周辺
において前記配線パターンと導通し前記基板を貫通する
よう設けられるとともに、前記半導体素子は前記樹脂の
表面にダイボンド材を介して搭載される ことを特徴とす
る半導体装置。1. The method according to claim 1, wherein the wiring pattern is provided.
A substrate provided with a through hole, and a half mounted corresponding to a mounting area provided on the substrate.
A conductor element and embedded in the through hole of the substrate,
Connecting the resin uniformly applied to the mounting area with the wiring pattern of the semiconductor element and the substrate;
A bonding wire, and the semiconductor element and the bonding wire are sealed.
A sealing material applied to one surface of the substrate.
And the through hole of the substrate is in the mounting area and in the vicinity thereof.
Conducts with the wiring pattern and penetrates the substrate at
And the semiconductor element is made of the resin.
A semiconductor device mounted on a surface via a die bonding material .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1992013227U JP2583242Y2 (en) | 1992-02-07 | 1992-02-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1992013227U JP2583242Y2 (en) | 1992-02-07 | 1992-02-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0566996U JPH0566996U (en) | 1993-09-03 |
| JP2583242Y2 true JP2583242Y2 (en) | 1998-10-22 |
Family
ID=11827299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1992013227U Expired - Fee Related JP2583242Y2 (en) | 1992-02-07 | 1992-02-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2583242Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4522399B2 (en) * | 2006-11-06 | 2010-08-11 | 富士通セミコンダクター株式会社 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6430878U (en) * | 1987-08-19 | 1989-02-27 | ||
| JP2612468B2 (en) * | 1988-05-12 | 1997-05-21 | イビデン株式会社 | Substrate for mounting electronic components |
| JPH03212960A (en) * | 1990-01-18 | 1991-09-18 | Toshiba Chem Corp | Semiconductor device |
-
1992
- 1992-02-07 JP JP1992013227U patent/JP2583242Y2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0566996U (en) | 1993-09-03 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |