JPH0566996U - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0566996U JPH0566996U JP013227U JP1322792U JPH0566996U JP H0566996 U JPH0566996 U JP H0566996U JP 013227 U JP013227 U JP 013227U JP 1322792 U JP1322792 U JP 1322792U JP H0566996 U JPH0566996 U JP H0566996U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- hole
- semiconductor element
- semiconductor device
- sealing material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
(57)【要約】
【目的】 スルーホールが設けられた基板において、実
装密度の向上が図れる半導体装置を提供する。
【構成】 表面に配線パターン１７を形成した基板１１
と、この基板１１上に搭載し、かつボンディングワイヤ
ー１５にてパッド１７ａと接続した半導体素子１２と、
基板１１上で半導体素子１２とボンディングワイヤー１
５とを封止する状態に塗布した封止材１３とから成る半
導体装置１において、基板１１上の封止材１３の塗布領
域内にスルーホール１４を設け、このスルーホール１４
のホール１４ａ内に樹脂１６を埋め込んだものである。
(57) [Summary] [Object] To provide a semiconductor device capable of improving the mounting density in a substrate provided with through holes. [Structure] Substrate 11 having wiring pattern 17 formed on its surface
And a semiconductor element 12 mounted on this substrate 11 and connected to a pad 17a by a bonding wire 15,
The semiconductor element 12 and the bonding wire 1 on the substrate 11
5, the through hole 14 is provided in the application area of the sealing material 13 on the substrate 11, and the through hole 14
The resin 16 is embedded in the hole 14a.
Description
【０００１】[0001]
本考案は、半導体素子の搭載領域内や封止材の塗布領域内にスルーホールが設 けられた半導体装置に関するものである。 The present invention relates to a semiconductor device having through holes formed in a mounting area of a semiconductor element or a coating area of a sealing material.
【０００２】[0002]
電子機器の小型化や薄型化を図る観点から、基板上にベアチップ等の半導体素 子を直接搭載した表面実装型の半導体装置がある。これを図２に基づいて説明す る。 この半導体装置１は、基板１１上の半導体素子１２を搭載する位置に搭載領域 Ｓが設けられ、この搭載領域Ｓ上にダイボンド材１２ａを介してベアチップ状の 半導体素子１２が搭載されている。 搭載された半導体素子１２は、ボンディングワイヤー１５により配線パターン １７のパッド１７ａと接続されており、この半導体素子１２とボンディングワイ ヤー１５とを保護するために、熱硬化性樹脂等から成る封止材１３がこの半導体 素子１２とボンディングワイヤー１５とを封止する状態に塗布されている。 また、基板１１の封止材１３の塗布領域Ｒより外側には配線パターン１７と導 通状態のスルーホール１４が設けられており、このスルーホール１４を介して基 板１１の両面に半導体素子１２やチップ部品（図示せず）等を接続することで、 実装密度の向上を図っている。 From the viewpoint of miniaturization and thinning of electronic devices, there is a surface-mounting type semiconductor device in which a semiconductor element such as a bare chip is directly mounted on a substrate. This will be described with reference to FIG. In this semiconductor device 1, a mounting area S is provided at a position on the substrate 11 where the semiconductor element 12 is mounted, and a bare chip-shaped semiconductor element 12 is mounted on the mounting area S via a die bond material 12a. The mounted semiconductor element 12 is connected to the pad 17a of the wiring pattern 17 by a bonding wire 15. In order to protect the semiconductor element 12 and the bonding wire 15, a sealing material made of thermosetting resin or the like is used. 13 is applied so as to seal the semiconductor element 12 and the bonding wire 15. In addition, a through hole 14 that is in communication with the wiring pattern 17 is provided outside the application region R of the sealing material 13 of the substrate 11, and the semiconductor element 12 is provided on both surfaces of the substrate 11 via the through hole 14. By connecting chip components (not shown), etc., the mounting density is improved.
【０００３】[0003]
しかしながら、この半導体装置には次のような問題がある。 すなわち、基板上の封止材の塗布領域内にスルーホールを設けた場合、塗布し た封止材がこのスルーホールを通り、基板の裏面側に漏れてしまう。 また、半導体素子の搭載領域内にスルーホールを設けた場合には、ダイボンド 材がスルーホールから基板の裏面側に漏れてしまう。 このため、基板上の封止材の塗布領域および半導体素子の搭載領域にはスルー ホールを設置することができない、いわゆる禁止領域となっている。 したがって、この禁止領域以外にスルーホールを設けなければならず、配線パ ターンの設計上、大きな制約を受けることになる。 とくに、半導体素子の実装面積が大きい場合には、部品の実装密度の低下を招 き、基板の縮小化が困難となる。 よって、本考案はスルーホールが設けられた基板において、実装密度の向上が 図れる半導体装置を提供することを目的とする。 However, this semiconductor device has the following problems. That is, when a through hole is provided in the application area of the sealing material on the substrate, the applied sealing material passes through the through hole and leaks to the back surface side of the substrate. Further, when the through hole is provided in the mounting area of the semiconductor element, the die bonding material leaks from the through hole to the back surface side of the substrate. For this reason, a through hole cannot be installed in the area where the sealing material is applied on the substrate and the area where the semiconductor element is mounted, which is a so-called prohibited area. Therefore, a through hole must be provided in a region other than this prohibited area, which imposes a large restriction on the design of the wiring pattern. In particular, when the mounting area of a semiconductor element is large, the mounting density of components is reduced, and it is difficult to reduce the size of the substrate. Therefore, an object of the present invention is to provide a semiconductor device capable of improving mounting density on a substrate provided with through holes.
【０００４】[0004]
本考案は上記の課題を解決するために成された半導体装置である。 すなわち、表面に配線パターンを形成した基板と、この基板上に搭載し、かつ ボンディングワイヤーにて配線パターンと接続した半導体素子と、基板上で半導 体素子とボンディングワイヤーとを封止する状態に塗布した封止材とから成る半 導体装置において、基板上の封止材の塗布領域内にスルーホールを設け、このス ルーホールのホール内に樹脂を埋め込んだものである。 The present invention is a semiconductor device made to solve the above problems. In other words, a substrate having a wiring pattern formed on its surface, a semiconductor element mounted on this substrate and connected to the wiring pattern by a bonding wire, and a semiconductor element and a bonding wire on the substrate are sealed. In a semiconductor device consisting of the applied sealing material, a through hole is provided in the area where the sealing material is applied on the substrate, and resin is embedded in the hole of this through hole.
【０００５】[0005]
基板上の封止材の塗布領域内に設けたスルーホールのホール内に樹脂が埋め込 まれているため、この塗布領域内に塗布した封止材がスルーホールを通って基板 の裏面側に漏れることがない。 したがって、半導体素子の搭載領域内に設けたスルーホールにおいても、ダイ ボンド材が基板の裏面側へ漏れることがない。 これにより、基板のスルーホールを設置できない、いわゆる禁止領域にもスル ーホールを設けることができるため、配線パターンの設計自由度が増加するとと もに、基板の縮小化を図ることができる。 Since the resin is embedded in the through-hole provided in the sealing material application area on the substrate, the sealing material applied in this application area leaks to the back side of the substrate through the through-hole. Never. Therefore, the die bonding material does not leak to the back side of the substrate even in the through hole provided in the mounting area of the semiconductor element. As a result, the through hole can be provided in the so-called prohibited area where the through hole of the substrate cannot be installed, so that the degree of freedom in designing the wiring pattern can be increased and the size of the substrate can be reduced.
【０００６】[0006]
以下に本考案の半導体装置の実施例を図に基づいて説明する。 図１は本考案の半導体装置を説明する断面図である。この半導体装置１は、主 に配線パターン１７が形成された基板１１と、この基板１１上の搭載領域Ｓに搭 載され、かつボンディングワイヤー１５にて配線パターン１７と接続された半導 体素子１２と、基板１１上で半導体素子１２とボンディングワイヤー１５とを封 止する状態に塗布された封止材１３とから成るものである。 なお、本実施例において、基板１１上の半導体素子１２が搭載された一部分を 用いて説明するが、他の半導体素子１２が搭載された部分についても同様である 。 An embodiment of the semiconductor device of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view illustrating a semiconductor device of the present invention. This semiconductor device 1 mainly includes a substrate 11 on which a wiring pattern 17 is formed, and a semiconductor element 12 mounted on a mounting area S on the substrate 11 and connected to the wiring pattern 17 by a bonding wire 15. And a sealing material 13 applied on the substrate 11 so as to seal the semiconductor element 12 and the bonding wire 15. In addition, in the present embodiment, description will be made using a part of the substrate 11 on which the semiconductor element 12 is mounted, but the same applies to a part on which another semiconductor element 12 is mounted.
【０００７】 半導体素子１２は、基板１１上の搭載領域Ｓに塗布された絶縁性の高いダイボ ンド材１２ａを介して接続されている。したがって、半導体素子１２の裏面を用 いた基板１１との電気的な接地は成されない。 基板１１上で封止材１３を塗布する塗布領域Ｒ内には、配線パターン１７と導 通状態にあるスルーホール１４が設けられている。このスルーホール１４は半導 体素子１２の搭載領域Ｓ内にも設けられており、各スルーホール１４のホール１ ４ａ内にはレジスト材等の樹脂１６が埋め込まれている。The semiconductor element 12 is connected to the mounting area S on the substrate 11 via a high-insulating die bond material 12 a. Therefore, no electrical grounding is performed with the substrate 11 using the back surface of the semiconductor element 12. A through hole 14 is provided in the application region R where the sealing material 13 is applied on the substrate 11 so as to be in communication with the wiring pattern 17. This through hole 14 is also provided in the mounting area S of the semiconductor element 12, and a resin 16 such as a resist material is embedded in the hole 14a of each through hole 14.
【０００８】 これにより、基板１１上で塗布領域Ｒ内に封止材１３を塗布した場合、この封 止材１３がスルーホール１４のホール１４ａを通って基板１１の裏面側に漏れる ことがない。 さらに、基板１１上の搭載領域Ｓに塗布したダイボンド材１２ａがスルーホー ル１４のホール１４ａを通って基板１１の裏面側に漏れることがない。 また、樹脂１６を搭載領域Ｓの全体を覆う状態に塗布すれば、この搭載領域Ｓ の表面が平滑となり、ダイボンド材１２ａによる半導体素子１２と基板１１との 密着性が向上する。As a result, when the sealing material 13 is applied to the application region R on the substrate 11, the sealing material 13 does not leak to the back surface side of the substrate 11 through the hole 14 a of the through hole 14. Further, the die bond material 12a applied to the mounting area S on the substrate 11 does not leak to the back surface side of the substrate 11 through the hole 14a of the through hole 14. If the resin 16 is applied so as to cover the entire mounting region S, the surface of the mounting region S 2 becomes smooth, and the adhesion between the semiconductor element 12 and the substrate 11 by the die bond material 12a is improved.
【０００９】 次に、この半導体装置１の製造方法について簡単に説明する。 先ず、エポキシ基板等の基板１１に所定の配線パターン１７を印刷法等を用い て形成し、必要な箇所にスルーホール１４を設ける。なお、このスルーホール１ ４の設置位置に関して特に制限はない。Next, a method of manufacturing the semiconductor device 1 will be briefly described. First, a predetermined wiring pattern 17 is formed on the substrate 11 such as an epoxy substrate by using a printing method or the like, and the through holes 14 are provided at necessary places. There are no particular restrictions on the installation position of the through hole 14.
【００１０】 次いで、基板１１上の封止材１３の塗布領域Ｒにレジスト材等の樹脂１６を塗 布する。そして、ボンディングワイヤー１５を接続するためのパッド１７ａ上に 塗布された樹脂１６を除去する。Next, a resin 16 such as a resist material is applied to the application area R of the sealing material 13 on the substrate 11. Then, the resin 16 applied on the pad 17a for connecting the bonding wire 15 is removed.
【００１１】 次に、樹脂１６が塗布された状態の搭載領域Ｓに絶縁ペースト等のダイボンド 材１２ａを塗布する。このとき、搭載領域Ｓ内にスルーホール１４が設けられて いても、そのホール１４ａ内が樹脂１６にて埋め込まれているため、基板１１の 裏面側に樹脂１６が漏れることはない。そして、このダイボンド材１２ａにより ベアチップ状の半導体素子１２を搭載領域Ｓ上に接着する。Next, a die bonding material 12a such as an insulating paste is applied to the mounting area S where the resin 16 has been applied. At this time, even if the through hole 14 is provided in the mounting area S, the resin 16 does not leak to the back surface side of the substrate 11 because the hole 14a is filled with the resin 16. Then, the bare chip-shaped semiconductor element 12 is bonded onto the mounting region S by the die bonding material 12a.
【００１２】 次に、半導体素子１２と配線パターン１７のパッド１７ａとを熱圧着法等によ りボンディングワイヤー１５を用いて接続する。 最後に、基板１１上の塗布領域Ｒにエポキシ樹脂等の熱硬化性樹脂から成る封 止材１３を滴下法等により塗布し、ベアチップ状の半導体素子１２とボンディン グワイヤー１５を保護する。 この塗布の際、塗布領域Ｒ内に設けられたスルーホール１４のホール１４ａ内 にも前述の樹脂１６が埋め込まれているため、封止材１３が基板１１の裏面側に 漏れることはない。 なお、基板１１の裏面に回路構成に応じたチップ部品（図示せず）を接続する ことにより、両面実装型の半導体装置１となる。Next, the semiconductor element 12 and the pad 17 a of the wiring pattern 17 are connected by the bonding wire 15 by a thermocompression bonding method or the like. Finally, a sealing material 13 made of a thermosetting resin such as an epoxy resin is applied to the application region R on the substrate 11 by a dropping method or the like to protect the bare chip semiconductor element 12 and the bonding wire 15. At the time of this coating, the resin 16 is also embedded in the holes 14a of the through holes 14 provided in the coating region R, so that the sealing material 13 does not leak to the back surface side of the substrate 11. By connecting a chip component (not shown) according to the circuit configuration to the back surface of the substrate 11, the double-sided mounting type semiconductor device 1 is obtained.
【００１３】 このような方法により製造した半導体装置１は、従来スルーホール１４の設置 禁止領域であった塗布領域Ｒ内にスルーホール１４を設けることが可能となる。 したがって、配線パターン１７やスルーホール１４のレイアウト設計を自由に 行うことができ、半導体装置１の基板面積を従来の基板面積と比べて約６０％程 度にすることが可能となる。In the semiconductor device 1 manufactured by such a method, the through hole 14 can be provided in the coating region R, which is a region where the installation of the through hole 14 is conventionally prohibited. Therefore, the layout design of the wiring patterns 17 and the through holes 14 can be freely performed, and the substrate area of the semiconductor device 1 can be set to about 60% of the conventional substrate area.
【００１４】[0014]
【考案の効果】 以上説明したように、本考案の半導体装置によれば次のような効果がある。 すなわち、封止材の塗布領域内にスルーホールを設けることが可能となるため 、半導体素子やチップ部品等を実装する基板の実装密度の大幅な向上と、基板の 縮小化を図ることが可能となる。 これにより、半導体素子の搭載領域内にもスルーホールを設けることができる 。したがって、実装面積の大きい半導体素子を用いた場合において、本考案はと くに有効である。As described above, the semiconductor device of the present invention has the following effects. In other words, since it is possible to provide through holes in the area where the encapsulant is applied, it is possible to greatly improve the mounting density of the substrate on which semiconductor elements, chip components, etc. are mounted and to reduce the size of the substrate. Become. As a result, the through hole can be provided in the mounting area of the semiconductor element. Therefore, the present invention is very effective when a semiconductor element having a large mounting area is used.
【図１】本考案の半導体装置を説明する断面図である。FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.
【図２】従来の半導体装置を説明する断面図である。FIG. 2 is a cross-sectional view illustrating a conventional semiconductor device.
１ 半導体装置 １１ 基板 １２ 半導体素子 １２ａ ダイボンド材 １３ 封止材 １４ スルーホール １４ａ ホール １５ ボンディングワイ
ヤー １６ 樹脂 １７ 配線パターン １７ａ パッド1 Semiconductor Device 11 Substrate 12 Semiconductor Element 12a Die Bonding Material 13 Sealing Material 14 Through Hole 14a Hole 15 Bonding Wire 16 Resin 17 Wiring Pattern 17a Pad
Claims (1)
基板上に搭載され、かつボンディングワイヤーにて前記
配線パターンと接続された半導体素子と、前記基板上で
前記半導体素子と前記ボンディングワイヤーとを封止す
る状態に塗布された封止材とから成る半導体装置におい
て、 前記基板上の前記封止材の塗布領域内には前記配線パタ
ーンと導通状態のスルーホールが設けられており、前記
スルーホールのホール内に樹脂が埋め込まれていること
を特徴とする半導体装置。1. A substrate provided with a wiring pattern, a semiconductor element mounted on the substrate and connected to the wiring pattern by a bonding wire, and the semiconductor element and the bonding wire on the substrate. In a semiconductor device including a sealing material applied in a sealing state, a through hole in a conductive state with the wiring pattern is provided in an application area of the sealing material on the substrate. A semiconductor device, in which a resin is embedded in the hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1992013227U JP2583242Y2 (en) | 1992-02-07 | 1992-02-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1992013227U JP2583242Y2 (en) | 1992-02-07 | 1992-02-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0566996U true JPH0566996U (en) | 1993-09-03 |
| JP2583242Y2 JP2583242Y2 (en) | 1998-10-22 |
Family
ID=11827299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1992013227U Expired - Fee Related JP2583242Y2 (en) | 1992-02-07 | 1992-02-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2583242Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007027804A (en) * | 2006-11-06 | 2007-02-01 | Fujitsu Ltd | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6430878U (en) * | 1987-08-19 | 1989-02-27 | ||
| JPH01286344A (en) * | 1988-05-12 | 1989-11-17 | Ibiden Co Ltd | Substrate for mounting electronic parts |
| JPH03212960A (en) * | 1990-01-18 | 1991-09-18 | Toshiba Chem Corp | Semiconductor device |
-
1992
- 1992-02-07 JP JP1992013227U patent/JP2583242Y2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6430878U (en) * | 1987-08-19 | 1989-02-27 | ||
| JPH01286344A (en) * | 1988-05-12 | 1989-11-17 | Ibiden Co Ltd | Substrate for mounting electronic parts |
| JPH03212960A (en) * | 1990-01-18 | 1991-09-18 | Toshiba Chem Corp | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007027804A (en) * | 2006-11-06 | 2007-02-01 | Fujitsu Ltd | Semiconductor device |
| JP4522399B2 (en) * | 2006-11-06 | 2010-08-11 | 富士通セミコンダクター株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2583242Y2 (en) | 1998-10-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |