JP2000200972A - Multilayer build up wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mutilayer build up wiring board, wherein the insulation deterioration of an inter-layer resin insulation layer is little and chip-mounting regions can be formed flat. SOLUTION: Mesh holes 35b are formed in a chip-mounting region C of a planar layer 34U and lands 36a of through-holes 36 and vias 60a are provided in the mesh holes 35b. Hence, the moisture absorbed in an interlayer resin insulation layer and a core board can be evaporated through gaps K of the mesh holes 34b, and the insulation of the interlayer resin insulation layer and the core board can be enhanced. The lands 36a and the vias 60a are formed in the mesh holes 34b at the chip mounting region C, hence no irregularity is formed, and the chip mounting region C can be made flat.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a build-up wiring layer in which interlayer resin insulation layers and conductor layers are alternately laminated,
The present invention relates to a multilayer build-up wiring board formed on both surfaces of a core substrate, and more particularly to a multilayer build-up wiring board having a plane layer formed as a power supply conductor layer (power supply layer) or a grounding conductor layer (ground layer). It is.

[0002]

2. Description of the Related Art In a multilayer build-up wiring board in which a plurality of conductive layers (conductive circuits) are insulated by interlayer resin insulating layers, one conductive circuit is connected to a ground layer or
It is used as a power supply layer for the purpose of reducing noise and the like. In such a multilayer build-up wiring board,
As shown in FIG. 13A, a ground conductor layer (ground layer) or a plane layer 459 constituting a power supply conductor layer (power supply layer) is often formed in a mesh pattern having mesh holes 459a. Here, the mesh hole 45
The reason for providing 9a is that the plane layer 459 is formed of copper having low connectivity with the resin, so that it is disposed below the interlayer resin insulation layer (not shown) disposed above the plane layer and below. The connectivity with the resin core substrate (not shown) is improved by directly contacting the interlayer resin insulation layer with the core substrate at the mesh holes 459a. In addition, the mesh hole 459a
This is for facilitating the emission of a gas composed of moisture and the like absorbed into the interlayer resin insulating layer through the insulating layer.

[0003] Various proposals have been made regarding the formation position of the mesh hole 459a. For example, JP
In No. 0-200271, as shown in FIG. 13 (B), no mesh hole is provided in a region facing the chip mounting region shown in FIG. 13C, and the mesh is provided only outside the chip mounting region. A technique has been proposed in which the holes 459a are provided so that the chip mounting area is not uneven, and the chip mounting area of the multilayer printed wiring board is formed flat.

[0004]

As described above, since the gas in the interlayer resin insulating layer escapes through the mesh holes, unless the mesh holes are formed in the chip mounting region as in the above-described technique, the chip mounting region is not provided. Water does not emanate from the lower interlayer resin insulation layer, and the interlayer resin insulation layer peels off,
In this portion, the insulation resistance of the interlayer resin insulation layer was reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a multilayer build-up wiring board in which the insulation deterioration of an interlayer resin insulation layer is small and a chip mounting area can be formed flat. Is to do.

[0006]

In order to achieve the above object, a first aspect of the present invention is to provide a chip mounting area in which an interlayer resin insulating layer and a conductor layer are alternately laminated, and a chip mounting area for mounting a chip is provided on an uppermost layer. In a multilayer build-up wiring board in which conductive layers are connected by via holes, a mesh hole is provided in a plane layer formed as the conductive layer, and a mesh hole in a region opposed to the chip mounting region via an interlayer resin insulating layer. And at least a part thereof is provided with a through hole or a land of a via hole and a pad connected to the via hole.

According to a second aspect of the present invention, there is provided a multi-layer build in which an interlayer resin insulating layer and a conductor layer are alternately laminated, a chip mounting area for mounting a chip is provided on the uppermost layer, and the conductor layers are connected by via holes. In the up-wiring board, a mesh hole is provided in a plane layer formed as the conductor layer, and at least a part of the mesh hole in a region opposed to the chip mounting region via an interlayer resin insulating layer. The technical feature is that the land of the via hole is located in the country.

According to a third aspect of the present invention, there is provided a multilayer build-up wiring board in which an interlayer resin insulating layer and a conductor layer are alternately laminated, and a chip mounting area for mounting a chip is formed on the uppermost layer. A mesh hole is provided in the plane layer, and at least a part of the mesh hole in a region opposed to the chip mounting region via the interlayer resin insulating layer, and the solid conductor layer is provided in the hole. Technical features.

According to a fourth aspect of the present invention, there is provided a multi-layer build-up wiring in which an interlayer resin insulating layer and a conductor layer are alternately laminated on a substrate having a through hole, and a chip mounting area for mounting a chip is provided on the uppermost layer. In the plate, a mesh hole is provided in the plane layer formed as the conductor layer, and at least a part of the mesh hole in a region facing the chip mounting region via the interlayer resin insulating layer, and It is a technical feature that a land of a through hole is provided in the vehicle.

According to the first aspect of the present invention, a mesh hole is formed in a region of the plane layer opposed to the uppermost chip mounting region via the interlayer resin insulating layer, and at least a part of the mesh holes is formed. Of the through holes or via holes and pads to be connected to the via holes are provided at an interval from the periphery of the mesh hole, so that the pads are arranged on the plane layer by the mesh holes provided on the outer periphery of these lands. Since the interlayer resin insulation layer and the interlayer resin insulation layer (or resin core substrate) provided below are brought into direct contact, the adhesiveness can be improved. Further, a gas composed of moisture absorbed in the interlayer resin insulating layer can be radiated through the mesh holes provided on the outer periphery of these lands, so that the insulating property of the interlayer resin insulating layer can be improved. Further, since lands and via holes are formed in the mesh holes in the chip mounting area, no irregularities are formed, and the chip mounting area can be made flat.

According to the second aspect of the present invention, a mesh hole is formed in a region of the plane layer opposed to the uppermost chip mounting region via the interlayer resin insulating layer, and at least a part of the mesh hole is formed. In order to provide the land of the via hole in the hole of the mesh hole with the periphery of the mesh hole, the mesh hole provided on the outer periphery of the land of the via hole forms an interlayer resin insulating layer and a lower layer which are disposed above the plane layer. The interlayer resin insulation layer (or resin core substrate)
Direct contact makes it possible to enhance the adhesiveness. In addition, a gas consisting of moisture or the like absorbed in the interlayer resin insulating layer can be radiated through the mesh holes provided on the outer periphery of the land of the via hole, so that the insulating property of the interlayer resin insulating layer can be improved. Further, since the via holes are formed in the mesh holes in the chip mounting area, no irregularities are formed, and the chip mounting area can be made flat.

According to the third aspect of the present invention, a mesh hole is formed in a region of the plane layer facing the uppermost chip mounting region via the interlayer resin insulating layer, and at least a part of the mesh holes is formed. In order to provide the solid conductor layer at an interval with the periphery of the mesh hole, the solid conductor layer is disposed on the interlayer resin insulating layer and the lower layer disposed on the plane layer by the mesh hole provided on the outer periphery of the solid conductor layer. The direct contact with the interlayer resin insulation layer (or resin core substrate) can improve the adhesiveness. In addition, a gas consisting of moisture or the like absorbed in the interlayer resin insulating layer can be radiated through the mesh holes provided on the outer periphery of the solid conductor layer, so that the insulating property of the interlayer resin insulating layer can be improved. Further, since the solid conductor layer is formed in the mesh hole in the chip mounting area, no irregularities are formed, and the chip mounting area can be made flat.

According to the fourth aspect of the present invention, a mesh hole is formed in a region of the plane layer opposed to the uppermost chip mounting region via the interlayer resin insulating layer, and at least a part of the mesh holes is formed. In order to provide the land of the through hole at an interval with the periphery of the mesh hole, the interlayer resin insulating layer provided on the upper layer of the plane layer and the interlayer resin provided on the lower layer by the mesh hole provided on the outer periphery of the land are provided. Since the insulating layer (or the resin core substrate) is brought into direct contact, the adhesiveness can be improved. Further, a gas consisting of moisture or the like absorbed in the interlayer resin insulating layer can be radiated through the mesh holes provided on the outer periphery of the land, so that the insulating property of the interlayer resin insulating layer can be improved. Furthermore,
Since lands are formed in the mesh holes in the chip mounting area, no irregularities are formed, and the chip mounting area can be made flat. In the present invention, the plane layer only needs to face the chip mounting area via at least one or more interlayer resin insulating layers.

In the present invention, it is desirable to use an adhesive for electroless plating as the interlayer resin insulating layer. The most suitable adhesive for electroless plating is one in which heat-resistant resin particles soluble in a cured acid or oxidizing agent are dispersed in an uncured heat-resistant resin hardly soluble in an acid or oxidizing agent. is there. By treating with an acid or an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus-shaped anchor can be formed on the surface.

In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles which have been particularly hardened include a heat-resistant resin powder having an average particle diameter of 10 μm or less, and an average particle diameter of 2 μm.
Aggregated particles obtained by aggregating the following heat-resistant resin powder, a heat-resistant powder resin powder having an average particle size of 2 to 10 μm and an average particle size of 2 μm
m and a mixture with a heat-resistant resin powder having a mean particle size of 2 or less.
Pseudo particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 μm or less to the surface of a 10 μm heat-resistant resin powder, and an average particle diameter of 0.1 to
0.8μm heat resistant resin powder and average particle size 0.8μ
m, and a mixture with a heat-resistant resin powder of less than 2 μm,
It is desirable to use a heat-resistant resin powder having an average particle size of 0.1 to 1.0 μm. This is because they can form more complex anchors.

The depth of the roughened surface is Rmax = 0.01 to 2
0 μm is preferred. This is to ensure adhesion. Particularly, in the semi-additive method, the thickness is preferably 0.1 to 5 μm. This is because the electroless plating film can be removed while ensuring adhesion.

The heat-resistant resin hardly soluble in an acid or an oxidizing agent is selected from a “resin composite composed of a thermosetting resin and a thermoplastic resin” or a “resin composite composed of a photosensitive resin and a thermoplastic resin”. It is desirable to become. This is because the former has high heat resistance, and the latter can form an opening for a via hole by photolithography.

As the thermosetting resin, epoxy resin, phenol resin, polyimide resin and the like can be used. In the case of photosensitization, methacrylic acid, acrylic acid, or the like is subjected to an acrylate reaction with a thermosetting group. Particularly, acrylate of epoxy resin is most suitable. As the epoxy resin, a novolak type epoxy resin such as a phenol novolak type and a cresol novolak type, and an alicyclic epoxy resin modified with dicyclopentadiene can be used.

As the thermoplastic resin, polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PP
E), polyetherimide (PI) and the like can be used.
The mixing ratio of the thermosetting resin (photosensitive resin) and the thermoplastic resin is: thermosetting resin (photosensitive resin) / thermoplastic resin = 95
/ 5 to 50/50 is preferred. This is because a high toughness value can be secured without impairing the heat resistance.

The mixing weight ratio of the heat-resistant resin particles is 5 to 50% by weight based on the solid content of the heat-resistant resin matrix.
Desirably, the content is 10 to 40% by weight. As the heat-resistant resin particles, amino resin (melamine resin, urea resin, guanamine resin), epoxy resin and the like are preferable. The adhesive may be composed of two layers having different compositions.

As the solder resist layer to be added to the surface of the multilayer build-up wiring board, various resins can be used. For example, bisphenol A epoxy resin, acrylate of bisphenol A epoxy resin, novolak epoxy resin, novolak A resin obtained by curing an acrylate of a type epoxy resin with an amine curing agent or an imidazole curing agent can be used.

On the other hand, such a solder resist layer is
Since it is composed of a resin having a rigid skeleton, peeling may occur. Therefore, the provision of the reinforcing layer can also prevent the solder resist layer from peeling off.

Here, as the acrylate of the novolak type epoxy resin, an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolak with acrylic acid, methacrylic acid or the like can be used.

The above-mentioned imidazole curing agent is desirably liquid at 25 ° C. This is because a liquid can be uniformly mixed. As such a liquid imidazole curing agent,
1-benzyl-2-methylimidazole (product name: 1B2MZ),
1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN) and 4-methyl-2-ethylimidazole (product name: 2E4MZ) can be used.

The amount of the imidazole curing agent is desirably 1 to 10% by weight based on the total solid content of the solder resist composition. The reason for this is that if the added amount is within this range, uniform mixing is easy.

The composition before curing of the solder resist is as follows:
It is desirable to use a glycol ether-based solvent as the solvent. The solder resist layer using such a composition does not generate free acid and does not oxidize the copper pad surface. It is also less harmful to the human body.

As such a glycol ether-based solvent, one having the following structural formula, particularly preferably at least one selected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG) is used. This is because these solvents can completely dissolve benzophenone and Michler's ketone as reaction initiators by heating at about 30 to 50 ° C. CH ₃ O-(CH ₂ CH _{2 O) n -CH 3 (n =} 1~5) solvent of glycol ether is a good 10 to 70 weight% relative to the total weight of the resist composition.

In addition to the solder resist composition described above, various antifoaming agents and leveling agents, thermosetting resins for improving heat resistance and base resistance and imparting flexibility,
A photosensitive monomer or the like can be added to improve the resolution. For example, as the leveling agent, one made of a polymer of an acrylate ester is preferable. The initiator is preferably Irgacure I907 manufactured by Ciba-Geigy, and the photosensitizer is DETX-S manufactured by Nippon Kayaku. further,
A dye or pigment may be added to the solder resist composition. This is because the wiring pattern can be hidden. It is desirable to use phthalocyanine green as this dye.

As the thermosetting resin as an additional component, a bisphenol type epoxy resin can be used. This bisphenol type epoxy resin includes a bisphenol A type epoxy resin and a bisphenol F type epoxy resin, and when importance is attached to base resistance, the former is required to reduce viscosity (when importance is attached to coating properties). The latter is better.

As the photosensitive monomer as an additional component, a polyvalent acrylic monomer can be used.
This is because the polyvalent acrylic monomer can improve the resolution. For example, Nippon Kayaku's DPE-6A and Kyoeisha Chemical's R-
604 can be used. Further, these solder resist compositions are preferably 0.5 to 10 Pa · s at 25 ° C., more preferably 1 to 10 Pa · s. This is because the viscosity is easy to apply with a roll coater.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer build-up wiring board according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings. First, the configuration of the multilayer build-up wiring board 10 according to the first embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 6 is a cross-sectional view of the multilayer printed wiring board 10 before mounting the IC chip, and FIG.
7 shows a state in which the IC chip 90 is mounted on the multilayer printed wiring board 10 shown in FIG.

As shown in FIG. 6, in the multilayer build-up wiring board 10, a through hole 36 is formed in the core substrate 30, and a plane layer 34U serving as a power supply layer is formed on the surface (IC chip side) of the core substrate 30. A plain layer 34D serving as a ground layer is formed on the back surface (daughter board side). On the plane layers 34U and 34D, a lower interlayer resin insulation layer 50 having via holes 60 and conductive circuits 58 is provided. On the lower interlayer resin insulation layer 50, an upper interlayer resin insulation layer 150 in which a via hole 160 and a conductor circuit 158 (only the back side is shown) is formed.

As shown in FIG. 7, solder bumps 76U for connection to the lands 92 of the IC chip 90 are provided on the upper surface side of the multilayer printed wiring board. Solder bump 76
U is connected to the through hole 36 via the via hole 160 and the via hole 60. On the other hand, a solder bump 76D for connection to the land 96 of the daughter board 94 is provided on the lower surface side. The solder bump 76
D is connected to the through hole 36 via the via hole 160 and the via hole 60.

FIG. 8 shows a cross section taken along the line DD of FIG. 7, that is, the plane of the plane layer 34U formed on the surface of the core substrate 30. 8 corresponds to FIG. As shown in FIG. 8A, the plane layer 34U has a region facing the region where the IC chip 90 in FIG. 7 is mounted via an interlayer resin insulating layer (hereinafter, referred to as a “chip mounting region”). Outside, a mesh hole 35a having a diameter of 250 μm has a pitch P
(560 μm). On the other hand, a gourd-shaped mesh hole 35b is formed inside the chip mounting area C. FIG. 8 is an enlarged view of the mesh hole 35b.
It is shown in (B). In the mesh hole 35b, 5 to 50 μm
The land 36a of the through hole 36 and the via hole (bottom portion of the via hole) 60a are provided with a gap K of m. The land 36a and the pad connected to the via hole are connected via a conductor circuit 34c.

In the multilayer printed wiring board 10 of the first embodiment, a mesh hole 35b is formed in the chip mounting area C of the plane layer 34U, and the land 36a of the through hole 36 and the via hole are connected to the mesh hole 35b. In order to provide the pad 60a, the pad 60a is disposed below the interlayer resin insulating layer 50 disposed above the plane layer 34U at the gap K between the mesh holes 36b provided on the outer periphery of the pad 60a connected to the land 36a and the via hole. Since the resin core substrate 30 to be provided is brought into direct contact, the adhesiveness can be improved. Further, a gas consisting of moisture or the like absorbed by the interlayer resin insulating layer 50 and the core substrate 30 can be radiated through the gap K of the mesh hole 35b provided on the outer periphery of the pad 60a connected to the land 36a and the via hole. It is possible to enhance the insulating properties between the interlayer resin insulating layer 50 and the core substrate 30 and prevent the interlayer resin insulating layer from peeling off. Further, since the pads 60a for connecting the lands 36a and the via holes are formed in the mesh holes 35b of the chip mounting area C, the chip mounting area C can be made flat without unevenness. That is, if the mesh hole 35a is also provided in the chip mounting region C, the inside of the hole remains as a recess and irregularities are formed. In the present embodiment, the pad 60a to which the land 36a and the via hole are connected is provided in the hole. By setting it, it can be made flat. As shown in FIG. 8 (C), the land 36a and the pad connected to the via hole may be integrated into a gourd type, a Daruma type, or a teardrop type.

Hereinafter, a method for manufacturing a multilayer build-up wiring board according to the first embodiment of the present invention will be described with reference to the drawings. Here, A.E. used in the method for manufacturing a multilayer build-up wiring board of the first embodiment is described. Adhesive for electroless plating, B. Interlayer resin insulation, C.I. Resin filler, D.I. The composition of the solder resist composition will be described.

A. Raw material composition for preparation of adhesive for electroless plating (adhesive for upper layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
35% by weight of a resin solution dissolved in DMDG at a concentration of 3.15% and a photosensitive monomer (Toa Gosei Co., Aronix M315) 3.15
Parts by weight, 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, S-65)
3.6 parts by weight of NMP were obtained by stirring and mixing.

[Resin Composition] 12 parts by weight of polyether sulfone (PES), epoxy resin particles (manufactured by Sanyo Chemical Co., Ltd.)
After mixing 7.2 parts by weight of a polymer pole having an average particle size of 1.0 μm and 3.09 parts by weight of a polymer pole having an average particle size of 0.5 μm, 30 parts by weight of NMP was further added, followed by stirring and mixing with a bead mill.

[Curing Agent Composition] 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of a photoinitiator (Irgacure I-907, manufactured by Ciba Geigy), and a photosensitizer (manufactured by Nippon Kayaku) , DETX-S) 0.2 parts by weight and NMP 1.5 parts by weight.

B. Raw material composition for preparing interlayer resin insulation agent (adhesive for lower layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
% Of a resin solution dissolved in DMDG at a concentration of 35%, 4 parts by weight of a photosensitive monomer (Alonix M315, manufactured by Toagosei Co., Ltd.), 0.5 parts by weight of an antifoaming agent (S-65, manufactured by San Nopco), N
3.6 parts by weight of MP were obtained by stirring and mixing.

[Resin composition] 12 parts by weight of polyether sulfone (PES), epoxy resin particles (manufactured by Sanyo Chemical Co., Ltd.)
After mixing 14.49 parts by weight of a polymer pole having an average particle size of 0.5 μm, 30 parts by weight of NMP were further added,
It was obtained by stirring and mixing with a bead mill.

[Curing Agent Composition] 2 parts by weight of imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of photoinitiator (Irgacure I-907, manufactured by Ciba-Geigy), photosensitizer (manufactured by Nippon Kayaku) , DETX-S) 0.2 parts by weight and NMP 1.5 parts by weight with stirring.

C. Raw material composition for resin filler preparation [Resin composition] 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U), having an average particle diameter of 1.6 μm coated with a silane coupling agent on the surface SiO ₂ spherical particles (Admatech, CRS
1101-CE, where the maximum particle size is 170 parts by weight of the inner layer copper pattern described below (15 μm or less) and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) by stirring and mixing. The viscosity of the mixture is 23 ±
It was obtained by adjusting to 45,000 to 49,000 cps at 1 ° C. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN) 6.5 parts by weight.

D. Solder resist composition 60% by weight of cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in DMDG was sensitized with 50% of epoxy groups of acrylated oligomer (molecular weight 4000).
6.67 g, 15.0 g of 80 wt% bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Chemicals,
2E4MZ-CN) 1.6 g, photosensitive acrylic monomer (Nippon Kayaku, R604) 3 g, polyvalent acrylic monomer (Kyoeisha Chemical, DPE6A) 1.5 g, dispersion defoamer (Sannopco) , S-65), and 2 g of benzophenone (Kanto Chemical) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Chemical) as a photosensitizer were added to the mixture. 2.0P at 25 ° C
A solder resist composition adjusted to a · s was obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type).
Rotor No.4 for 60rpm, rotor for 6rpm
No.3.

Subsequently, a manufacturing process of the multilayer build-up wiring board according to the first embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. In the first embodiment, a multilayer build-up wiring board is formed by a semi-additive method.

(1) As shown in FIG. 1A, an 18 μm copper foil 3 is formed on both sides of a substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm.
2 was used as a starting material. First, the copper clad laminate 30A is drilled,
The through holes 36 and the plane layers 34U, 3U are formed by performing an electroless plating process and etching them in a pattern.
4D is formed, and the core substrate 30 shown in FIG. 1B is formed. As described above with reference to FIG.
U and 34D are formed with mesh holes 35a and 35b,
As described above, the lands 36a of the through holes 36 and the conductor circuits 34 are provided in the mesh holes 35b in the chip mounting area C.
c and a via hole bottom 60a.

(2) Plane layer 34 and through hole 3
After the substrate 30 on which 6 was formed was washed with water and dried, NaOH (10 g / l), NaClO ₂ (40
g / l), Na ₃ PO ₄ (6 g / l), as a reducing bath,
A roughened layer 38 was provided on the surfaces of the plain layers 34U and 34D and the through holes 36 by oxidation-reduction treatment using NaOH (10 g / l) and NaBH ₄ (6 g / l) (FIG. 1).
(C)).

(3) The raw material composition for preparing the resin filler C was mixed and kneaded to obtain a resin filler.

(4) The resin filler 40 obtained in the above (3) is applied to both surfaces of the substrate 30 using a roll coater within 24 hours after the preparation, whereby the mesh holes of the conductor circuit (plain layer) 34 are formed. 35a, 35b and the inside of the through hole 36, and dried at 70 ° C. for 20 minutes. The other surface is filled with the resin filler 40 in the mesh hole 35a or the through hole 36 in the same manner. Heat drying was performed for 20 minutes (see FIG. 1 (D)).

(5) One surface of the substrate 30 after the treatment of (4) is subjected to belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku) to form the plain layers 34U and 34D.
Then, the resin filler 40 was polished so as not to remain on the surface of the lands 36a and the lands 36a of the through holes 36, and then buffing was performed to remove the scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate (see FIG. 2E). Then at 100 ° C for 1
The resin filler 40 was cured by performing a heat treatment at 120 ° C. for 3 hours, at 150 ° C. for 1 hour, and at 180 ° C. for 7 hours.

The surface layer of the resin filler 40 filled in the through holes 36 and the like and the plane layer 34
After removing the roughened layer 38 on the upper surface of the U and 34D and smoothing both surfaces of the substrate 30, the resin filler 40 and the plain layer 34U,
A wiring board was obtained in which the side surfaces of 34D were firmly adhered through the roughened layer 38, and the inner wall surfaces of the through holes 36 and the resin filler 40 were firmly adhered through the roughened layer 38. That is,
By this step, the surface of the resin filler 40 and the plain layer 3
The surfaces of 4U and 34D are on the same plane.

(6) The substrate 30 having the plane layers 34U and 34D formed thereon is alkali-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst. After activating
3.2 × 10 ⁻² mol / l copper sulfate, nickel sulfate
9 × 10 ⁻³ mol / l, complexing agent 5.4 × 10 ⁻² mo
1 / l, sodium hypophosphite 3.3 × 10 ⁻¹ mol
/ L, boric acid 5.0 × 10 ^-1 mol / l, surfactant (Surfir 465, manufactured by Nissin Chemical Industry) 0.1 g /
1, immersion in an electroless plating solution consisting of PH = 9, immersion 1
After one minute, the plane layers 34U and 34D, the land 36a of the through hole 36, and the surface of the bottom 60a of the via hole are subjected to vertical and horizontal vibrations once every four seconds.
A coating layer of a needle-like alloy made of u-Ni-P and a roughened layer 42 were provided (see FIG. 2F).

Furthermore, tin borofluoride 0.1 mol /
1, thiourea 1.0 mol / l, temperature 35 ° C., PH =
A Cu—Sn substitution reaction was performed under the conditions of 1.2, and a 0.3 μm-thick Sn layer (not shown) was provided on the surface of the roughened layer.

(7) The raw material composition for preparing the interlayer resin insulating agent (B) was stirred and mixed, and the viscosity was adjusted to 1.5 Pa · s to obtain an interlayer resin insulating agent (for lower layer). Next, the raw material composition for preparing the adhesive for electroless plating of A was stirred and mixed, and the viscosity was adjusted to 7 Pa · s to obtain an adhesive solution for electroless plating (for the upper layer).

(8) On both surfaces of the substrate of (6), the interlayer resin insulating material (for lower layer) having a viscosity of 1.5 Pa · s
4 was coated with a roll coater within 24 hours after preparation, left in a horizontal state for 20 minutes, dried at 60 ° C. for 30 minutes (prebaked), and then the viscosity of 7 Pa · obtained in the above (7) was obtained. s
Of the photosensitive adhesive solution (for upper layer) 46 is applied within 24 hours after preparation, and left in a horizontal state for 20 minutes.
The adhesive layer 50α having a thickness of 35 μm was formed (see FIG. 2G).

(9) The substrate 3 on which the adhesive layer was formed in the above (8)
The photomask film 51 (FIG. 3 (H)) on which a black circle 51a of 85 μmφ was printed was brought into close contact with both sides of the “0”, and exposed at 500 mJ / cm ² using an ultrahigh pressure mercury lamp. This is DMT
The substrate 30 is exposed to 3,000 mJ / cm ² by an ultra-high pressure mercury lamp, and heated (post-baked) at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and then at 150 ° C. for 3 hours. In this manner, an interlayer resin insulating layer (two-layer structure) 50 having a thickness of 35 μm and having an opening (via hole formation opening) 48 of 85 μm φ excellent in dimensional accuracy corresponding to a photomask film was formed (FIG. I)). Note that a tin plating layer (not shown) was partially exposed in the opening 48 serving as a via hole.

(10) The substrate 30 in which the opening 48 is formed is immersed in chromic acid for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer 50, thereby obtaining the interlayer resin insulating layer 50. Was roughened (see FIG. 3 (J)), and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water.

(11) A palladium catalyst (manufactured by Atotech) is applied to the surface of the substrate 30 whose surface has been roughened in the step (10), so that a catalyst nucleus is formed on the surface of the interlayer resin insulating layer 50. Thereafter, the substrate 30 is immersed in an electroless copper plating aqueous solution having the following composition to form a 0.6 μm-thick electroless plating film 52 as a whole (see FIG. 3K). [Electroless plating aqueous solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. 30 minutes at liquid temperature

(12) A commercially available photosensitive dry film is stuck on the electroless copper plating film 52 formed in the above (11), a mask is placed thereon, and exposure is performed at 100 mJ / cm ² , followed by 0.8% sodium carbonate. Developed, 15μm thick plating resist 54
(See FIG. 3 (L)).

(13) Next, electrolytic copper plating was performed on the non-resist-formed portion under the following conditions to form an electrolytic copper plating film 56 having a thickness of 15 μm (see FIG. 4 (M)). [Electroplating conditions] Current density 1A / dm ² hours 30 minutes Temperature Room temperature

(14) After stripping and removing the plating resist 54 with 5% KOH, the electroless plating film 52 under the plating resist is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to remove the electroless plating film. Plating film 52 and electrolytic copper plating film 5
An 18 μm-thick conductor circuit 58 and via hole 60 made of 6 were formed (FIG. 4 (N)).

(15) The same processing as in (6) is performed, and the conductor circuit 5
A roughened surface 62 made of Cu-Ni-P was formed on the surfaces of the via holes 60 and the via holes 60, and the surfaces thereof were further substituted with Sn (see FIG. 4 (O)).

(16) By repeating the steps (7) to (15), the interlayer resin insulating layer 150, the via hole 160, and the conductor circuit 158 of the upper layer are further formed to complete the multilayer build-up wiring board. (See FIG. 4 (P)). In addition,
In the step of forming the upper conductor circuit, Sn substitution was not performed.

(17) Then, the above-described multilayer build-up distribution
Form solder bumps on the wire plate. The group obtained in the above (16)
The above D.C. Solder resist explained in
The composition 70α is applied in a thickness of 45 μm (FIG. 5)
(Q)). Then dry at 70 ° C for 20 minutes and 70 ° C for 30 minutes
After processing, a circular pattern (mask pattern) is drawn
5mm thick photomask film (not shown)
Placed in close contact, 1000mJ / cm ²Exposure with ultraviolet light
Perform DMTG development processing. And then at 80 ° C for 1 hour, 100
1 hour at 120 ° C, 1 hour at 120 ° C, 3 hours at 150 ° C
Heat the solder pad (via hole and its
(Including opening part) has an opening (opening diameter 200μm) 71
Forming a solder resist layer (thickness: 20 μm) 70
(See FIG. 5 (R)).

(18) Next, nickel chloride 2.31 × 10 ^-1 mo
1 / l, sodium hypophosphite 2.8 × 10 ^-1 mol /
1 and 1.85 × 10 ⁻¹ mol / l of sodium citrate, and the substrate 3 was placed in an electroless nickel plating solution having a pH of 4.5.
0 was immersed for 20 minutes to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. Further, the substrate was treated with potassium cyanide 4.1 × 10 ⁻² mol / l, ammonium chloride 1.87 × 10 ⁻¹ mol / l, sodium citrate 1.
16 × 10 ⁻¹ mol / l, sodium hypophosphite 1.7 × 10
Immersion in an electroless gold plating solution of ^-1 mol / l at 80 ° C. for 7 minutes and 20 seconds to form a film having a thickness of 0.2 mm on the nickel plating layer.
By forming the gold plating layer 74 of 03 μm, the solder pad 75 is formed in the via hole 160 and the conductor circuit 158 (only the back side is shown) (see FIG. 5 (S)).

(19) Then, solder paste is printed in the opening 71 of the solder resist layer 70 and reflowed at 200 ° C., so that the solder bumps (solder bodies) 76U and 76D
To complete the multilayer build-up wiring board 10 (see FIG. 6).

The IC chip 90 is mounted on the solder bumps 76U of the completed multilayer printed wiring board 10 so that the pads 92 of the IC chip 90 correspond to the solder bumps 76U and reflow is performed. Then, the IC chip 90 and the multilayer printed wiring board 10
Is filled with an underfill 88. The multilayer printed wiring board 10 on which the IC chip 90 is mounted is mounted so as to correspond to the bumps 96 on the daughter board 94, reflowed, and attached to the daughter board 94. Thereafter, an underfill 88 is filled between the multilayer printed wiring board 10 and the daughter board 94.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 9 shows the second
1 shows a cross-sectional view of a multilayer printed wiring board 110 of the embodiment. In the above-described first embodiment, the plane layers 34U and 34D are provided on both surfaces of the core substrate 30. However, in the multilayer printed wiring board 110 of the second embodiment, the plane layers 58U and 34U are provided on the interlayer resin insulating layer 50. 58D are formed.

That is, in the multilayer build-up wiring board 110 of the second embodiment, the conductor circuit 34 is formed on the front and back surfaces of the core substrate 30, and the lower interlayer resin insulation layer 50 is formed on the conductor circuit 34. Have been. Plain layers 58U and 58D are formed on lower interlayer resin insulation layer 50. Here, the plane layer 58 on the front side (IC chip side) is used as a power supply layer, and the plane layer 58 on the back side (daughter board side) is used as a ground layer. Above the plane layers 58U and 58D, an upper interlayer resin insulation layer 150 is formed, and via holes 160 and conductor circuits 158 are provided.

FIG. 1 is a sectional view taken along the line FF of FIG. 9, that is, the plane of the plane layer 58U formed on the surface of the interlayer resin insulating layer 50.
0 (A). A cross section taken along line GG of FIG. 10A corresponds to FIG. As shown in FIG. 10, a mesh hole 59a having a diameter of 200 μm is formed in the plane layer 58U outside the chip mounting area C. On the other hand, a gourd-shaped mesh hole 59b is formed inside the chip mounting area C. FIG. 10B shows the mesh hole 359b in an enlarged manner. In the mesh hole 59b, a via hole 60 formed in the interlayer resin insulation layer 50 with a gap K of several tens μm is provided.
Pads (bottoms of via holes) 160a connected to via holes formed in interlayer resin insulating layer 150 are provided. That is, the via hole land 60 and the via hole connecting pad 160a are integrally formed.

The multilayer printed wiring board 110 of the second embodiment
Then, a mesh hole 59b is formed in the chip mounting area C of the plane layer 58U, and a via hole land 60 and a pad 160a for connecting the via hole are provided in the mesh hole 59b.
0, the plane layer 58 is formed by the gap K between the mesh holes 59b provided on the outer periphery of the pad 160a connecting the via hole.
Since the interlayer resin insulating layer 150 provided above U and the interlayer resin insulating layer 50 provided below are brought into direct contact with each other, the adhesiveness can be improved. The via hole land 60 and the via hole connecting pad 160
Since a gas consisting of moisture or the like absorbed by the interlayer resin insulating layers 150 and 50 can be radiated through the gap K between the mesh holes 59b provided on the outer periphery of the interlayer resin insulating layers 50 and 50,
It is possible to enhance the insulation of the substrate 50 and prevent the interlayer resin insulation layer from peeling off. Further, since the land 60 of the via hole and the pad 160a connected to the via hole are formed in the mesh hole 59b of the chip mounting region C, no irregularities are formed, and the chip mounting region C can be made flat. In addition, as shown in FIG. 11C, the connection portion between the land 60 of the via hole and the pad 160a to which the via hole is connected may be eliminated, and the shape may be a dwarf type or a teardrop type.

Next, the structure of the multilayer printed wiring board according to the third embodiment will be described with reference to FIG. 11. FIG. 11 shows a plane layer 34 formed on the front side of the core substrate.
It is a top view which shows U. Here, in the first embodiment described above with reference to FIG. 8, a mesh hole 35b in which a land 36a of a through hole and a pad 60 to which a via hole is connected is provided in the chip mounting area C. . On the other hand, in the third embodiment, in the chip mounting area C,
In addition to the gourd-shaped mesh hole 35b, a circular mesh hole 35c is provided, and a solid conductor layer 34d is provided in the mesh hole 35c. Note that FIG.
As shown in (B), the solid conductor layer 34d may be connected to the surrounding plane layer 34U at at least one location.

In the multilayer printed wiring board according to the third embodiment,
A mesh hole 35 is formed in the chip mounting area C of the plane layer 34U.
In order to form c and to provide the solid conductor layer 34d in the mesh hole 35c, the solid conductor layer 34d is disposed above the plane layer 34U at a gap between the mesh holes 35c provided on the outer periphery of the solid conductor layer 34d. Since the interlayer resin insulating layer 50 and the resin core substrate 30 provided in the lower layer are brought into direct contact with each other, the adhesiveness can be improved. Further, a gas consisting of moisture or the like absorbed by the interlayer resin insulating layer 50 and the core substrate 30 can be diffused through the gap of the mesh hole 35c provided on the outer periphery of the solid conductor layer 34d. It is possible to enhance the insulating properties of the core substrate 30 and prevent peeling of the interlayer resin insulating layer. Furthermore,
Since the solid conductor layer 34d is formed in the mesh hole 35c of the chip mounting area C, no irregularities are formed, and the chip mounting area C can be flattened.

Next, the configuration of the multilayer printed wiring board according to the fourth embodiment will be described with reference to FIG. 12. FIG. 12A is a plan view showing a plane layer 34U formed on the front side of the core substrate. It is. Here, in the first embodiment described above with reference to FIG. 8, the mesh holes 35b in which the lands 36a of the through holes and the pads 60 to which the via holes are connected are formed in the chip mounting area C.
On the other hand, in the fourth embodiment, a circular mesh hole 35d is provided in the chip mounting area C, and only the land 36a of the through hole is provided in the mesh hole 35d. FIG. 12B shows a cross section of the interlayer resin insulating layer 50 and the core substrate 30 of the fourth embodiment. In the fourth embodiment, the through holes 36 formed in the core substrate 30 are formed.
A via hole 60 is formed immediately above the land 36a.

In the multilayer printed wiring board according to the fourth embodiment,
A mesh hole 35 is formed in the chip mounting area C of the plane layer 34U.
d and the land 36a is provided in the mesh hole 35d, the interlayer resin insulating layer 50 disposed above the plane layer 34U at the gap between the mesh holes 35d provided on the outer periphery of the land 36a. Since the resin core substrate 30 provided in the lower layer is brought into direct contact with the resin core substrate 30, the adhesiveness can be improved. Further, since the gas composed of the moisture and the like absorbed by the interlayer resin insulating layer 50 and the core substrate 30 can be diffused through the gap of the mesh hole 35d provided on the outer periphery of the land 36a, the interlayer resin insulating layer 50 and the core substrate 30 It is possible to enhance the insulating property of the substrate and to prevent peeling of the interlayer resin insulating layer. Further, the chip mounting area C
In order to form the land 36a in the mesh hole 34d,
No irregularities are formed, and the chip mounting area C can be flattened.
As shown in FIG. 12C, the land 36a of the through hole and the via hole 60 may be connected via a conductor layer (lid plating) 36e covering the through hole.

[Brief description of the drawings]

1 (A), 1 (B), 1 (C), 1
(D) is a manufacturing process diagram of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIG. 2 (E), FIG. 2 (F), FIG. 2 (G), FIG.
(H) is a manufacturing process diagram of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIG. 3 (I), FIG. 3 (J), FIG. 3 (K), FIG.
(L) is a manufacturing process diagram of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIGS. 4 (M), 4 (N), 4 (O), 4
(P) is a manufacturing process diagram of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIGS. 5 (Q), 5 (R), and 5 (S) are manufacturing process diagrams of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIG. 6 is a sectional view of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view of the multilayer build-up wiring board according to the first embodiment of the present invention.

8 (A) is a sectional view taken along the line DD of FIG. 7, and FIG. 8 (B) is an enlarged view of the mesh hole of FIG. 8 (A);
FIG. 8C is an enlarged view of a mesh hole according to a modification.

FIG. 9 is a sectional view of a multilayer build-up wiring board according to a second embodiment of the present invention.

10 (A) is a sectional view taken along line FF of FIG. 9, FIG. 10 (B) is an enlarged view of the mesh hole shown in FIG. 10 (A), and FIG. It is an enlarged view of a mesh hole concerning a modification.

FIG. 11 (A) is a plan view of a plane layer of a multilayer build-up wiring board according to a third embodiment of the present invention, and FIG. 11 (B) is a mesh hole shown in FIG. 11 (A). It is an enlarged view of the modification of.

FIG. 12A is a plan view of a plane layer of a multilayer build-up wiring board according to a fourth embodiment of the present invention, and FIG. 12B is a cross-sectional view of the multilayer printed wiring board. FIG. 12C is a cross-sectional view of a multilayer printed wiring board according to a modification.

13 (A) and 13 (B) are plan views of plane layers of a multilayer build-up wiring board according to the related art.

[Explanation of symbols]

Reference Signs List 30 core substrate 34U, 34D plane layer 34d solid layer 35a, 35b, 35c, 35d mesh hole 36 via hole 36a land of via hole 50 interlayer resin insulating layer 58 conductive circuit 58U, 58D plane layer 59a, 59b mesh hole 60 via hole 60a Bottom of via hole (pad connected to via hole) 150 interlayer resin insulation layer 160 via hole 160a bottom of via hole

Claims (4)

[Claims] 1. A multilayer build-up wiring board in which an interlayer resin insulating layer and a conductor layer are alternately laminated, a chip mounting area for mounting a chip on an uppermost layer is provided, and the conductor layers are connected by via holes. A mesh hole is provided in the plane layer formed as the conductor layer, and at least a part of the mesh hole in a region opposed to the chip mounting region via an interlayer resin insulating layer, and a through hole or a via is formed in the hole. A multilayer build-up wiring board comprising a pad for connecting a land of a hole and a via hole. 2. A multilayer build-up wiring board in which an interlayer resin insulating layer and a conductor layer are alternately laminated, a chip mounting area for mounting a chip on an uppermost layer is provided, and the conductor layers are connected by via holes. A mesh hole is provided in the plane layer formed as the conductor layer, and at least a part of the mesh hole in a region opposed to the chip mounting region via an interlayer resin insulating layer, and a land of a via hole is formed in the hole. The multilayer build-up wiring board characterized by having arranged. 3. A multilayer build-up wiring board having an interlayer resin insulating layer and a conductor layer alternately laminated and having a chip mounting area for mounting a chip on the uppermost layer, wherein the plane layer formed as the conductor layer is A mesh hole, and at least a part of a mesh hole in a region opposed to the chip mounting region via an interlayer resin insulating layer, wherein a solid conductor layer is provided in the hole. Multilayer build-up wiring board. 4. A multilayer build-up wiring board comprising a substrate having a through hole, an interlayer resin insulating layer and a conductor layer alternately laminated on each other, and having a chip mounting area for mounting a chip on an uppermost layer. A mesh hole is provided in the plane layer formed as a layer, and at least a part of the mesh hole in a region opposed to the chip mounting region via the interlayer resin insulating layer, and a land of a through hole is formed in the hole. The multilayer build-up wiring board characterized by having arranged.