JP2000151898A - Ccd analog signal processing circuit, droop reduction method for dc storage capacitor and printed circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a leakage current to the printed circuit board and to allow the printed circuit board to employ a small sized inexpensive ceramic capacitor for an external DC storage capacitor. SOLUTION: Plural lead pins 2 are provided to one side of a package of a rectangular CCD analog signal processing IC 1 that converts only an image signal component in response to an input luminous quantity among output signals of a CCD linear image sensor into digital data, one of the lead pins 2 placed nearly in the middle is used for a DC storage capacitor connection terminal CH and nothing connects with the two terminals adjacent to both sides of the DC storage capacitor connection terminal CH and they are configured to be non-connection terminals NC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital copying machine,
The present invention relates to a CCD analog signal processing circuit that converts only an image signal component corresponding to an input light amount among output signals of a CCD linear image sensor in a scanner or a facsimile into digital data.

The present invention also relates to a method for reducing a droop of a DC holding capacitor in a CCD analog signal processing circuit and a printed circuit board.

[0003]

2. Description of the Related Art This type of CCD analog signal processing IC
However, when the number of lead pins is small, the mounting space on the printed circuit board does not matter much, and the distance between the lead pins can be sufficiently secured (for example, 1.
27mm and 0.8mm). In addition, conventional analog IC
Most are bipolar type, large terminal current, and long DC holding time, so an inexpensive, large-capacity electrolytic capacitor is used as an external DC holding capacitor. The leakage current to the printed circuit board was not a problem.
As a conventional example of this kind, for example, Japanese Patent Laid-Open No.
No. 3,224, JP-A-5-316338, and JP-A-6-46256.

[0004]

However, in recent years, digital-analog mixing of analog ICs has been advanced, and with this, the distance between lead pins has been reduced due to the increase in the number of pins. In addition, the terminal current becomes very small due to the change from the bipolar type to the MOS type, and the DC holding time is shortened in order to satisfy the demand for high-speed operation. There is an increasing demand for using ceramic capacitors that are low in unit price and small in shape and have low self-leakage current. Therefore, in such a situation, a leak current to the printed circuit board, which has not been a problem in the past, becomes a serious problem.

The present invention has been made in view of the above-mentioned problems, and a CCD analog signal processing circuit capable of reducing a leak current to a printed circuit board and using a small and inexpensive ceramic capacitor as an external DC holding capacitor. An object of the present invention is to provide a method for reducing droop of a DC holding capacitor and a printed circuit board.

[0006]

According to a first aspect of the present invention, there is provided a CCD analog signal for converting only an image signal component corresponding to an input light amount into digital data from an output signal of a CCD linear image sensor. In a CCD analog signal processing circuit in which a DC holding capacitor is externally attached to a processing IC, a pad-to-pad leak current for reducing a pad-to-pad leak current on a printed circuit board to which the CCD analog signal processing IC and a terminal of the DC holding capacitor are connected. It is characterized by comprising a current reducing means.

The second means is such that the inter-pad leakage current reducing means in the first means does not connect the second terminals on both sides adjacent to the first terminal of the IC to which the DC holding capacitor is connected. It is characterized by being configured as a terminal.

The third means is characterized in that in the second means, the third terminals on both sides adjacent to the second terminal are terminals for buffering the first terminal voltage.

In the fourth means, the inter-pad leak current reducing means in the first means is configured to connect the second terminals adjacent to the first terminal of the IC to which the DC holding capacitor is connected with the second terminals. The present invention is characterized in that the terminal voltage is a terminal for buffering one terminal voltage.

In a fifth aspect, the inter-pad leakage current reducing means in the first means is arranged such that a first terminal of the IC to which the DC holding capacitor is connected is disposed at an end of one side of an IC package. And a second terminal adjacent to the first terminal on the same side as a non-connection terminal.

A sixth means is the fifth means, wherein the third terminal adjacent to the second terminal on the same side is a terminal for buffering the first terminal voltage.

In a seventh aspect, the inter-pad leak current reducing means in the first means is arranged such that a first terminal of the IC to which the DC holding capacitor is connected is disposed at an end of one side of an IC package. And a second terminal adjacent to the first terminal on the same side as a terminal for buffering the first terminal voltage.

Eighth means includes third, fourth, sixth and seventh means.
A band limiting filter is provided between the first terminal and a terminal for buffering the first terminal voltage.

The ninth means is the third, fourth, sixth, seventh and eighth means wherein the buffer offset cancellation is provided between the first terminal and the terminal for buffering the first terminal voltage. Means are provided.

The tenth means is the third, fourth, sixth, seventh, eighth, and ninth means, wherein the first DC holding capacitor is mounted between the pads on which the DC holding capacitor is mounted without a resist. A wiring for connecting a terminal for buffering the voltage of the terminal is provided.

According to an eleventh means, a DC holding capacitor is externally connected to a CCD analog signal processing IC which converts only an image signal component corresponding to an input light amount among output signals of a CCD linear image sensor into digital data. CCD
A method for reducing droop of the DC holding capacitor in an analog signal processing circuit, the method comprising reducing a leak current between pads on a printed circuit board to which terminals of the CCD analog signal processing IC and the DC holding capacitor are connected. It is characterized in that the droop of the DC holding capacitor is reduced.

In a twelfth aspect, in the eleventh aspect, the DC holding capacitor is connected to a first terminal of the IC, and second terminals on both sides adjacent to the first terminal are disconnected. Thereby, the inter-pad leakage current is reduced.

The thirteenth means is that, in the twelfth means, the third terminals on both sides adjacent to the second terminal are terminals for buffering the first terminal voltage.
It is characterized in that inter-pad leakage current is reduced.

Fourteenth means is the eleventh means, wherein the DC holding capacitor is connected to a first terminal of the IC, and second terminals on both sides adjacent to the first terminal are connected to the first terminal. By using a terminal for buffering a voltage, a leakage current between pads is reduced.

In a fifteenth means, in the eleventh means, the DC holding capacitor is connected to a first terminal disposed at an end of one side of the package of the IC, and adjacent to the first terminal on the same side. By setting the second terminal to be a non-connection terminal, the inter-pad leak current is reduced.

The sixteenth means is the eleventh means,
A third terminal adjacent to the second terminal on the same side is a terminal for buffering the first terminal voltage, thereby reducing inter-pad leakage current.

Seventeenth means is that, in the eleventh means, the DC holding capacitor is connected to a first terminal arranged at one end of one side of the package of the IC, and adjacent to the first terminal on the same side. The second terminal to be used is a terminal for buffering the first terminal voltage, thereby reducing inter-pad leakage current.

The eighteenth means includes the thirteenth, fourteenth and sixteenth
And a seventeenth means is characterized in that a band limiting filter is provided between the first terminal and a terminal for buffering the first terminal voltage.

The nineteenth means includes the thirteenth, fourteenth, and first
6. In the seventeenth and eighteenth means, a buffer offset canceling means is provided between the first terminal and a terminal for buffering the first terminal voltage.

The twentieth means includes the thirteenth, fourteenth, and first
In the sixth, seventeenth, eighteenth, and nineteenth means, between the pads on which the DC holding capacitor is mounted, a wiring for connecting a terminal for buffering the voltage of the first terminal is provided, and no resist is provided. It is characterized by doing so.

According to a twenty-first means, a DC holding capacitor is externally connected to a CCD analog signal processing IC for converting only an image signal component corresponding to an input light amount among output signals of a CCD linear image sensor into digital data. In the printed circuit board, wiring for connecting a terminal for buffering a terminal voltage of the IC to which the DC holding capacitor is connected without a resist is provided between pads on which the DC holding capacitor is mounted. And

The twenty-second means is formed in a slit shape without the resist between the pads in the twenty-first means.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. Note that, in the following description, the same reference numerals are given to respective units that can be regarded as equivalent, and redundant description will be omitted.

<First Embodiment> FIG. 1 shows a C according to the present invention.
FIG. 2 is a configuration diagram illustrating an embodiment of a method for reducing droop of a CD analog signal processing circuit and a DC holding capacitor.

In FIG. 1, CCD analog signal processing I
C1 converts only an image signal component corresponding to an input light amount among output signals of a CCD linear image sensor (not shown) into digital data. A plurality of lead pins 2 are provided on one side of the rectangular package 1a of the IC 1, and one of the substantially center pins of the lead pins 2 is used as a DC holding capacitor connection terminal CH. The DC holding capacitor connection terminal C
Nothing is connected to the two terminals adjacent to both sides of H, and the terminal is configured as a non-connection terminal NC.

Here, the relationship between the pitch of the lead pins 2 and the distance between the pads on the printed circuit board on which the DC holding capacitor C1 is mounted is as follows. However, the distance between the pads is an approximate value.

Lead pitch = 1.27 mm: distance between pads = 0.5 mm = 0.8 mm: = 0.5 mm = 0.65 mm: = 0.3 mm = 0.5 mm: = 0.2 mm CCD analog signal processing IC 1 and The printed circuit board on which the DC holding capacitor C1 is mounted greatly differs depending on the use environment when the insulation resistance is lowered due to dirt or the like. However, empirically, if it is 1 MΩ / mm (distance between the electrodes), there is a problem. Absent. In consideration of this, the relationship between the lead pitch and the insulation resistance between pads is as follows.

Lead pitch = 1.27 mm: insulation resistance between pads = 0.5 MΩ = 0.8 mm: = 0.5 MΩ = 0.65 mm: = 0.3 MΩ = 0.5 mm: = 0.2 MΩ Although not absolute, there is the danger of a fairly small insulation resistance. Therefore, as shown in FIG. 1, when two terminals adjacent to both sides of the DC holding capacitor connection terminal CH are set to the non-connection terminal NC, the number of pads is about twice as large as when the other signal terminals are used. The insulation resistance between them can be secured.

As an example, considering a case where the lead pitch is 0.5 mm, the DC holding voltage is 1.65 V, and the terminals on both sides of the non-connection terminal NC are connected to the ground (GND), the leak current = (1.65) −0) / (200 k + 200 k) × 2 = 8.25 μA. On the other hand, when the non-connection terminal NC is not provided, the leak current = (1.65-0) / (200 k) × 2 = 16.5 μA.

<Second Embodiment> Next, a second embodiment will be described with reference to FIG. In this embodiment, the DC holding capacitor C1 is connected to the DC holding capacitor connection terminal C.
H, and CCD analog signal processing IC
Voltage follower (BU) in package 1a
F). Two terminals adjacent to both sides of the DC holding capacitor connection terminal CH are used as buffering output terminals BO of a voltage follower (BUF). In this embodiment, the inter-pad insulation resistance does not double, but the voltage applied to the insulation resistance is only the offset voltage of the voltage follower (BUF). As an example, assuming that the lead pitch is 0.5 mm, the DC holding voltage is 1.65 V, and the offset voltage of the voltage follower (BUF) is 30 mV, the leak current = {1.65- (1.65 ± 0.03)} / 200 k × 2 = 300 nA, so that the leakage current can be greatly reduced.

<Third Embodiment> Next, a third embodiment will be described with reference to FIG. In this embodiment, of the plurality of lead pins 2a provided on one side of the rectangular CCD analog signal processing IC package 1, the terminal provided at the end is used as a DC holding capacitor connection terminal CH, and is connected to the same side. , One terminal adjacent to the DC holding capacitor connection terminal CH is configured as a non-connection terminal NC.

According to this configuration, not only SOP (small outline package) or SSOP having lead pins 2a and 2b provided on two sides of the package, but also QFP (quad flat package) having lead pins 2 provided on four sides. Package). in this case,
Since the distance from the DC holding capacitor connection terminal CH to the terminal 2b on the other side closest to the DC holding capacitor connection terminal CH is several times to ten times the distance to the non-connection terminal NC adjacent to the DC holding capacitor connection terminal CH on the same side, The insulation resistance up to the lead other than the side where the DC holding capacitor connection terminal CH is provided can be neglected.
As compared with the configuration shown in the first embodiment (FIG. 1), the leak current is about half.

<Fourth Embodiment> A fourth embodiment shown in FIG. 4 has a configuration in which the second and third embodiments are combined, and has a rectangular CCD analog signal processing IC package 1.
Among the plurality of lead pins 2a provided on one side of a, the terminal provided at the end is used as the DC holding capacitor connection terminal CH, and one terminal adjacent to the DC holding capacitor connection terminal CH on the same side is It is used as a buffering output terminal BO of a voltage follower (BUF). In this case, similarly, FIG.
The leakage current is about half as compared with the configuration shown in FIG. Each part not particularly described is configured in the same manner as in the second and third embodiments.

<Fifth Embodiment> A fifth embodiment shown in FIG. 5 is a configuration in which the first and second embodiments are combined, and one of the lead pins 2 substantially at the center is connected to a DC holding capacitor connection terminal CH. In addition, nothing is connected to the two terminals adjacent to both sides of the DC holding capacitor connection terminal CH so as to be configured as a non-connection terminal NC. Further, two terminals adjacent to both sides of the non-connection terminal NC are connected to each other. It is used as a buffering output terminal BO of a voltage follower (BUF). Parts not particularly described are configured in the same manner as in the first and second embodiments.

In the fifth embodiment, the inter-pad insulation resistance is doubled and the second
As in the embodiment, the voltage applied to the insulation resistance is only the offset voltage of the voltage follower (BUF). The leak current under the same conditions as the first and second embodiments is as follows: leak current = {1.65− (1.65 ± 0.03)} / 200 k × 2/2 = 150 nA

<Sixth Embodiment> A sixth embodiment shown in FIG. 6 has a configuration in which the third and fourth embodiments are combined, and includes a plurality of lead pins 2 provided on one side of the package 1. The terminal provided at the most end is used as a DC holding capacitor connection terminal CH, and one terminal adjacent to the DC holding capacitor connection terminal CH on the same side is configured as a non-connection terminal NC, and is connected to the non-connection terminal NC. One adjacent terminal is used as a buffering output terminal BO of a voltage follower (BUF). Parts not particularly described are configured in the same manner as in the first and second embodiments.

In the sixth embodiment, as in the first and second embodiments, the insulation resistance between pads is doubled, and the voltage applied to the insulation resistance is reduced by a voltage follower (BU).
Only the offset voltage of F) is obtained, and the leak current is about half that of the fifth embodiment.

<Seventh Embodiment> Next, a seventh embodiment will be described with reference to FIG. In this embodiment, in the case where an AC passes through the DC holding capacitor connection terminal CH in FIGS. 2, 4, 5, and 6, for example, in the case of an AC coupling capacitor of an AC coupling circuit with a clamp, a voltage follower (BUF) is used. Is configured to limit the frequency band of a signal input to the RL by an RC filter circuit. Note that the cut-off frequency fc of this RC filter circuit (resistance value = RF, capacitance = CF) is fc = 1 / (2π · RF · CF), whereby the voltage follower (BUF) rises and falls when falling. Even if the rates are unbalanced, the average voltage of the buffering output terminal BO is only the offset voltage of the voltage follower (BUF), so that the unbalanced slew rate does not affect the leak.

<Eighth Embodiment> Next, an eighth embodiment will be described with reference to FIG. In this embodiment, a voltage follower (BUF) that outputs the signal of the DC holding capacitor connection terminal CH to the buffering output terminal BO
Is reduced.

In FIG. 8, a DC holding capacitor connection terminal CH is connected to an RC filter circuit (RF, CF) and a switch S.
W2, connected to a non-inverting terminal of a voltage follower (BUF) via an offset holding capacitor CC,
The reference voltage Vr is applied to the non-inverting terminal of the voltage follower (BUF) via the switch SW1. The output (buffering output terminal BO) of the voltage follower (BUF) is connected to the inverting terminal of the voltage follower (BUF) and connected between the switch SW2 and the offset holding capacitor CC via the switch SW3. I have. An offset cancel signal is applied as a control signal to the non-inverting control terminals of the switches SW1 and SW3 and the inverting control terminal of the switch SW2.

In such a configuration, when the offset cancel signal is H, the switches SW1 and SW3 are on and the switch SW2 is off. In this state, the reference voltage Vr is applied to the non-inverting terminal of the voltage follower (BUF) via the switch SW1, thereby charging the offset holding capacitor CC.

On the other hand, when the offset cancel signal is L, the switches SW1 and SW3 are off and the switch S
W2 is on. In this state, after the voltage of the DC holding capacitor connection terminal CH is band-limited by the RC filter circuit, it is applied to the non-inverting terminal of the voltage follower (BUF) via the offset holding capacitor CC. It becomes higher than the voltage of the holding capacitor connection terminal CH by the offset voltage of the voltage follower (BUF). In addition, the voltage follower (BU)
F) lowers the input voltage by the offset voltage and outputs it to the buffering output terminal BO, so that the potential difference from the DC holding capacitor connection terminal CH to the buffering output terminal BO is canceled.

Here, the offset should ideally be "0", but actually, the holding voltage of the offset holding capacitor CC fluctuates due to the feedthrough of the switch, so that it is about several tens μV to several hundred μV. Offset voltage is generated. In any case, since the offset voltage can be made extremely small, the leak current can be reduced to about several tenths to about 1/100 of that of the circuits shown in FIGS.

<Ninth Embodiment> Next, a ninth embodiment will be described with reference to FIG. Here, in the first to eighth embodiments, only the leak between the pads of the IC1 has been described as a problem, but the leak between the pads of the DC holding capacitor C1 also exists, which is particularly shown in the seventh embodiment (FIG. 7). As described above, in the case where the AC passes through the DC holding capacitor connection terminal CH, for example, in the case of an AC coupling capacitor of an AC coupling circuit with a clamp, since the voltage between the terminals of the DC holding capacitor C1 is large, this leakage is remarkable. .

FIG. 10 shows the minimum pad spacing, leakage current, and inter-pad leakage current for each chip size using the DC holding capacitor C1 as a chip component. The figures are not absolute but approximate. The pad-to-pad leak current is calculated with the voltage between terminals of the capacitor C1 being 6V.
As shown in FIG. 10, the insulation resistance between the pads of the DC holding capacitor C1 is considerably large as compared with that of the IC1, but the voltage applied to the capacitor C1 is large.

Therefore, as shown in FIG. 9, in the ninth embodiment, two buffering output terminals BO are wired between the pads 11-1 and 11-2 for the capacitor C1. The resist 12 is not provided in a slit shape on the wiring between 11-1 and 11-2.
Therefore, a current flowing between the pads 11-1 and 11-2 flows to the buffering output terminal BO via this wiring, and does not flow to the DC holding capacitor connection terminal CH. However, the leak current between the pads 11-1 to which the buffering output terminal BO and the DC holding capacitor are connected is substantially the same as the leak current between the pads of the IC1, but compared with the leak current between the original pads of the IC1. Then, the value is about two digits smaller.

[0052]

As described above, according to the first aspect of the present invention, the inter-pad leak current for reducing the inter-pad leak current on the printed circuit board to which the terminals of the CCD analog signal processing IC and the DC holding capacitor are connected. Since the reduction means is provided, the leakage current to the printed circuit board can be reduced, and a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the second aspect of the present invention, since the second terminals on both sides adjacent to the first terminal of the IC to which the DC holding capacitor is connected are not connected, the leakage current to the printed circuit board is reduced. Thus, a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the third aspect of the present invention, since the third terminals on both sides adjacent to the second terminal are terminals for buffering the first terminal voltage, the leakage current to the printed circuit board is reduced. Thus, a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the fourth aspect of the present invention, the second terminals on both sides adjacent to the first terminal of the IC to which the DC holding capacitor is connected are terminals for buffering the first terminal voltage. Therefore, the leakage current to the printed circuit board can be reduced, and a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the fifth aspect of the present invention, the first terminal of the IC to which the DC holding capacitor is connected is a terminal arranged at an end of one side of the IC package, and the first side is connected to the first terminal on the same side. Since the adjacent second terminal is a non-connection terminal, leakage current to the printed circuit board can be reduced, and a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the sixth aspect of the present invention, since the third terminal adjacent to the second terminal on the same side is a terminal for buffering the first terminal voltage, a leakage current to the printed circuit board is provided. And a small and inexpensive ceramic capacitor can be used as the external DC holding capacitor.

According to the invention described in claim 7, the first terminal of the IC to which the DC holding capacitor is connected is a terminal arranged at an end of one side of the IC package, and the first terminal is located on the same side. Since the second terminal adjacent to the terminal is a terminal for buffering the first terminal voltage, the leakage current to the printed circuit board is reduced, and a small and inexpensive ceramic capacitor is used as an external DC holding capacitor. be able to.

According to the eighth aspect of the present invention, since the band limiting filter is provided between the first terminal and the terminal for buffering the first terminal voltage, the leakage current to the printed circuit board is reduced, A small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the ninth aspect of the present invention, since the buffer offset canceling means is provided between the first terminal and the terminal for buffering the first terminal voltage, the leakage current to the printed circuit board can be reduced. Thus, a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the tenth aspect of the present invention, a wiring for connecting a terminal for buffering the voltage of the first terminal is provided between pads on which the DC holding capacitor is mounted, and a resist is not provided. Therefore, the leakage current to the printed circuit board can be reduced, and a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the eleventh aspect of the present invention, the leak current between the pads on the printed board to which the terminals of the CCD analog signal processing IC and the DC holding capacitor are connected is reduced, so that the leak current to the printed board is reduced. And a small and inexpensive ceramic capacitor can be used as the external DC holding capacitor.

According to the twelfth aspect of the present invention, the DC holding capacitor is connected to the first terminal of the IC, and the second terminals on both sides adjacent to the first terminal are non-connection terminals. Since the leakage current during the period is reduced, the leakage current to the printed circuit board can be reduced, and a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the thirteenth aspect of the present invention, the third terminal on both sides adjacent to the second terminal is a terminal for buffering the first terminal voltage, thereby reducing the inter-pad leakage current. Therefore, the leakage current to the printed circuit board can be reduced, and a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the present invention, the DC holding capacitor is connected to the first terminal of the IC, and the second terminals on both sides adjacent to the first terminal buffer the first terminal voltage. By reducing the leakage current between the pads, the leakage current to the printed circuit board can be reduced, and a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the fifteenth aspect of the present invention, the DC holding capacitor is connected to the first terminal disposed at one end of one side of the package of the IC, and the second side adjacent to the first terminal on the same side. By making the terminal of non-connection terminal,
Since the leak current between the pads is reduced, the leak current to the printed circuit board is reduced, and a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the sixteenth aspect, the third terminal adjacent to the second terminal on the same side is a terminal for buffering the first terminal voltage, thereby reducing the inter-pad leak current. Thus, the leakage current to the printed circuit board can be reduced, and a small and inexpensive ceramic capacitor can be used as the external DC holding capacitor.

According to the seventeenth aspect of the present invention, the DC holding capacitor is connected to the first terminal disposed at one end of one side of the package of the IC, and the second side adjacent to the first terminal on the same side. Since the terminal is a terminal for buffering the first terminal voltage, the leakage current between the pads is reduced. Therefore, the leakage current to the printed circuit board is reduced, and the external DC holding capacitor is small in size. Inexpensive ceramic capacitors can be used.

According to the eighteenth aspect of the present invention, since the band-limiting filter is provided between the first terminal and the terminal for buffering the first terminal voltage, the leakage current to the printed circuit board can be reduced. A small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the nineteenth aspect of the present invention, since the buffer offset canceling means is provided between the first terminal and the terminal for buffering the first terminal voltage, the leakage current to the printed circuit board can be reduced. Thus, a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the twentieth aspect of the present invention, a wiring for connecting a terminal for buffering the voltage of the first terminal is provided between pads on which a DC holding capacitor is mounted, and a resist is not provided. Therefore, the leakage current to the printed circuit board can be reduced, and a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the twenty-first aspect of the present invention, a wiring for connecting a terminal for buffering a terminal voltage of an IC to which the DC holding capacitor is connected is provided between pads on which the DC holding capacitor is mounted, and a resist is provided. , The leakage current to the printed circuit board can be reduced, and a small and inexpensive ceramic capacitor can be used as an external DC holding capacitor.

According to the twenty-second aspect of the present invention, since the resist between the pads is not provided in the form of a slit, the leakage current to the printed circuit board is reduced, and a small and inexpensive ceramic is used as an external DC holding capacitor. Capacitors can be used.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a CCD analog signal processing circuit and a droop reduction method of a DC holding capacitor according to the present invention.

FIG. 2 is a configuration diagram showing a CCD analog signal processing circuit and a droop reduction method of a DC holding capacitor according to a second embodiment.

FIG. 3 is a configuration diagram illustrating a method for reducing a droop of a CCD analog signal processing circuit and a DC holding capacitor according to a third embodiment.

FIG. 4 is a configuration diagram showing a CCD analog signal processing circuit and a droop reduction method of a DC holding capacitor according to a fourth embodiment.

FIG. 5 is a configuration diagram showing a CCD analog signal processing circuit and a droop reduction method of a DC holding capacitor according to a fifth embodiment.

FIG. 6 is a configuration diagram showing a CCD analog signal processing circuit and a droop reduction method of a DC holding capacitor according to a sixth embodiment.

FIG. 7 is a configuration diagram illustrating a method for reducing droop of a CCD analog signal processing circuit and a DC holding capacitor according to a seventh embodiment.

FIG. 8 is a configuration diagram illustrating a method for reducing droop of a CCD analog signal processing circuit and a DC holding capacitor according to an eighth embodiment.

FIG. 9 is a configuration diagram illustrating a CCD analog signal processing circuit, a droop reduction method for a DC holding capacitor, and a printed circuit board according to a ninth embodiment.

FIG. 10 is an explanatory diagram showing a minimum pad interval, a leakage current, and an inter-pad leakage current for each chip size of a DC holding capacitor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CCD analog signal processing IC 1a Package 2, 2a, 2b Lead pin C1 DC holding capacitor CH DC holding capacitor connecting terminal NC No connection terminal BO Buffering terminal BUF Voltage follower 11-1, 11-2 Pad 12 Resist

Claims (22)

[Claims] 1. A CCD analog signal processing wherein a DC holding capacitor is externally connected to a CCD analog signal processing IC for converting only an image signal component corresponding to an input light amount into digital data among output signals of a CCD linear image sensor. A CCD analog signal processing circuit, comprising: a circuit for reducing a leak current between pads on a printed circuit board to which terminals of the CCD analog signal processing IC and a DC holding capacitor are connected. . 2. The pad-to-pad leak current reducing means is configured by setting second terminals on both sides adjacent to a first terminal of the IC to which the DC holding capacitor is connected as non-connection terminals. 2. The CCD analog signal processing circuit according to claim 1, wherein: 3. The CCD analog signal processing circuit according to claim 2, wherein third terminals on both sides adjacent to said second terminal are terminals for buffering said first terminal voltage. 4. A terminal for buffering the first terminal voltage at a second terminal on both sides adjacent to a first terminal of the IC to which the DC holding capacitor is connected, the inter-pad leak current reducing means. 2. The CCD analog signal processing circuit according to claim 1, wherein: 5. The inter-pad leakage current reducing means, wherein the first terminal of the IC to which the DC holding capacitor is connected is a terminal arranged at an end of one side of an IC package, and 2. The CCD analog signal processing circuit according to claim 1, wherein said second terminal adjacent to said terminal is made a non-connection terminal. 6. The CCD analog signal processing circuit according to claim 5, wherein a third terminal adjacent to said second terminal on the same side is a terminal for buffering said first terminal voltage. 7. The inter-pad leakage current reducing means, wherein the first terminal of the IC to which the DC holding capacitor is connected is a terminal arranged at an end of one side of an IC package, and 2. The device according to claim 1, wherein a second terminal adjacent to said first terminal is a terminal for buffering said first terminal voltage.
The described CCD analog signal processing circuit. 8. A filter according to claim 3, wherein a band-limiting filter is provided between said first terminal and a terminal for buffering said first terminal voltage. 2. A CCD analog signal processing circuit according to 1. 9. An offset canceling means for a buffer is provided between the first terminal and a terminal for buffering the first terminal voltage.
9. The CCD analog signal processing circuit according to any one of 6, 7, and 8. 10. A wiring for connecting a terminal for buffering the voltage of the first terminal without providing a resist, between pads on which the DC holding capacitor is mounted. 3, 4, 6, 7, 8 and 9
3. The CCD analog signal processing circuit according to claim 1. 11. A CCD analog signal processing wherein a DC holding capacitor is externally connected to a CCD analog signal processing IC for converting only an image signal component corresponding to an input light amount into digital data among output signals of a CCD linear image sensor. A method for reducing the droop of the DC holding capacitor in a circuit, comprising: reducing a leak current between pads on a printed circuit board to which terminals of the CCD analog signal processing IC and the DC holding capacitor are connected. A droop reducing method for a DC holding capacitor, characterized in that the droop is reduced. 12. A method of reducing a leak current between pads,
12. The method according to claim 11, wherein the DC holding capacitor is connected to a first terminal of the IC, and the second terminals on both sides adjacent to the first terminal are disconnected. Method to reduce droop of DC holding capacitor. 13. The method of reducing a leak current between pads,
The third terminals on both sides adjacent to the second terminal are connected to the first terminal.
13. The method for reducing droop of a DC holding capacitor according to claim 12, wherein the method is performed by setting a terminal for buffering the terminal voltage. 14. The method according to claim 14, wherein the leakage current between the pads is reduced.
This is accomplished by connecting the DC holding capacitor to a first terminal of the IC and making the second terminals on both sides adjacent to the first terminal terminals for buffering the first terminal voltage. The method for reducing droop of a DC holding capacitor according to claim 11, wherein: 15. The method of reducing the leakage current between the pads,
The DC holding capacitor is connected to a first terminal disposed at an end of one side of the package of the IC, and a second terminal adjacent to the first terminal on the same side is set as a non-connection terminal. 12. The method for reducing droop of a DC holding capacitor according to claim 11, wherein: 16. The method of reducing the leakage current between the pads,
16. The method according to claim 15, wherein the third terminal adjacent to the second terminal on the same side is used as a terminal for buffering the first terminal voltage. . 17. The method of reducing leakage current between pads,
The DC holding capacitor is connected to a first terminal disposed at an end of one side of the package of the IC, and a second terminal adjacent to the first terminal on the same side buffers the voltage of the first terminal. The method for reducing droop of a DC holding capacitor according to claim 11, wherein the method is performed by using a terminal to be ringed. 18. A band limiting filter is provided between the first terminal and a terminal for buffering the voltage of the first terminal.
The method for reducing droop of a DC holding capacitor according to any one of the preceding claims. 19. A buffer offset canceling means is provided between the first terminal and a terminal for buffering the first terminal voltage.
19. The method for reducing droop of a DC holding capacitor according to any one of 14, 16, 17 and 18. 20. A wiring for connecting a terminal for buffering a voltage of the first terminal without a resist, between pads on which the DC holding capacitor is mounted. 13, 14, 16, 17, 1
The method for reducing droop of a DC holding capacitor according to any one of claims 8 and 19. 21. A printed circuit board in which a DC holding capacitor is externally connected to a CCD analog signal processing IC that converts only an image signal component corresponding to an input light amount into digital data among output signals of a CCD linear image sensor. A printed circuit board provided with a wiring for connecting a terminal for buffering a terminal voltage of the IC to which the DC holding capacitor is connected without a resist, between pads on which the DC holding capacitor is mounted; . 22. The printed circuit board according to claim 21, wherein the state without the resist between the pads is formed in a slit shape.